llvm.org GIT mirror llvm / a0240d6
AMDGPU: Remove SI_fs_constant and SI_fs_interp intrinsics Update test uses with expansion in terms of new intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295269 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 3 years ago
14 changed file(s) with 715 addition(s) and 450 deletion(s). Raw diff Collapse all Expand all
254254 }
255255 }
256256
257 static bool isIntrinsicSourceOfDivergence(const TargetIntrinsicInfo *TII,
258 const IntrinsicInst *I) {
257 static bool isIntrinsicSourceOfDivergence(const IntrinsicInst *I) {
259258 switch (I->getIntrinsicID()) {
260 default:
261 return false;
262 case Intrinsic::not_intrinsic:
263 // This means we have an intrinsic that isn't defined in
264 // IntrinsicsAMDGPU.td
265 break;
266
267259 case Intrinsic::amdgcn_workitem_id_x:
268260 case Intrinsic::amdgcn_workitem_id_y:
269261 case Intrinsic::amdgcn_workitem_id_z:
304296 case Intrinsic::amdgcn_ps_live:
305297 case Intrinsic::amdgcn_ds_swizzle:
306298 return true;
307 }
308
309 StringRef Name = I->getCalledFunction()->getName();
310 switch (TII->lookupName((const char *)Name.bytes_begin(), Name.size())) {
311299 default:
312300 return false;
313 case AMDGPUIntrinsic::SI_fs_interp:
314 case AMDGPUIntrinsic::SI_fs_constant:
315 return true;
316301 }
317302 }
318303
356341 if (isa(V) || isa(V))
357342 return true;
358343
359 if (const IntrinsicInst *Intrinsic = dyn_cast(V)) {
360 const TargetMachine &TM = getTLI()->getTargetMachine();
361 return isIntrinsicSourceOfDivergence(TM.getIntrinsicInfo(), Intrinsic);
362 }
344 if (const IntrinsicInst *Intrinsic = dyn_cast(V))
345 return isIntrinsicSourceOfDivergence(Intrinsic);
363346
364347 // Assume all function calls are a source of divergence.
365348 if (isa(V) || isa(V))
26832683 Op.getOperand(1),
26842684 Op.getOperand(2),
26852685 Op.getOperand(3));
2686
2687 case AMDGPUIntrinsic::SI_fs_constant: {
2688 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
2689 SDValue Glue = M0.getValue(1);
2690 return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32,
2691 DAG.getConstant(2, DL, MVT::i32), // P0
2692 Op.getOperand(1), Op.getOperand(2), Glue);
2693 }
26942686 case AMDGPUIntrinsic::SI_packf16:
26952687 if (Op.getOperand(1).isUndef() && Op.getOperand(2).isUndef())
26962688 return DAG.getUNDEF(MVT::i32);
26972689 return Op;
2698 case AMDGPUIntrinsic::SI_fs_interp: {
2699 SDValue IJ = Op.getOperand(4);
2700 SDValue I = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
2701 DAG.getConstant(0, DL, MVT::i32));
2702 SDValue J = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
2703 DAG.getConstant(1, DL, MVT::i32));
2704 I = DAG.getNode(ISD::BITCAST, DL, MVT::f32, I);
2705 J = DAG.getNode(ISD::BITCAST, DL, MVT::f32, J);
2706 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
2707 SDValue Glue = M0.getValue(1);
2708 SDValue P1 = DAG.getNode(AMDGPUISD::INTERP_P1, DL,
2709 DAG.getVTList(MVT::f32, MVT::Glue),
2710 I, Op.getOperand(1), Op.getOperand(2), Glue);
2711 Glue = SDValue(P1.getNode(), 1);
2712 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, P1, J,
2713 Op.getOperand(1), Op.getOperand(2), Glue);
2714 }
27152690 case Intrinsic::amdgcn_interp_mov: {
27162691 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
27172692 SDValue Glue = M0.getValue(1);
182182 def int_SI_image_load : Image;
183183 def int_SI_image_load_mip : Image;
184184 def int_SI_getresinfo : Image;
185
186 /* Interpolation Intrinsics */
187
188 def int_SI_fs_constant : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
189 def int_SI_fs_interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], [IntrNoMem]>;
190185 } // End TargetPrefix = "SI", isTarget = 1
191186
192187 let TargetPrefix = "amdgcn", isTarget = 1 in {
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test/Analysis/DivergenceAnalysis/AMDGPU/interp-intrinsics.ll less more
None ; RUN: opt -mtriple amdgcn--- -analyze -divergence %s | FileCheck %s
1
2 ; CHECK-LABEL: 'fs_interp'
3 ; CHECK: DIVERGENT: %v = call float @llvm.SI.fs.interp(
4 define amdgpu_ps void @fs_interp(i32 inreg %prim_mask, <2 x i32> %interp_param) #1 {
5 %v = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %prim_mask, <2 x i32> %interp_param)
6 store volatile float %v, float addrspace(1)* undef
7 ret void
8 }
9
10 ; CHECK-LABEL: 'fs_constant'
11 ; CHECK: DIVERGENT: %v = call float @llvm.SI.fs.constant(
12 define amdgpu_ps void @fs_constant(i32 inreg %prim_mask, <2 x i32> %interp_param) #1 {
13 %v = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %prim_mask)
14 store volatile float %v, float addrspace(1)* undef
15 ret void
16 }
17
18 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #0
19 declare float @llvm.SI.fs.constant(i32, i32, i32) #0
20
21 attributes #0 = { nounwind readnone }
None ; RUN: llc -march=amdgcn < %s | FileCheck %s
1 ; REQUIRES: asserts
0 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
21 ;
32 ; This testcase used to cause the following crash:
43 ;
1716 ;
1817 ; Test for a valid output:
1918 ; CHECK: image_sample_c_d_o
20
21 target triple = "amdgcn--"
22
2319 define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([17 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg, [16 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg1, [32 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg2, [16 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg3, [16 x <4 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg4, float inreg %arg5, i32 inreg %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <3 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, <2 x i32> %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, i32 %arg20, float %arg21, i32 %arg22) #0 {
2420 main_body:
25 %tmp = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %arg6, <2 x i32> %arg8)
26 %tmp23 = fadd float %tmp, 0xBFA99999A0000000
27 %tmp24 = fadd float %tmp, 0x3FA99999A0000000
21 %i.i = extractelement <2 x i32> %arg8, i32 0
22 %j.i = extractelement <2 x i32> %arg8, i32 1
23 %i.f.i = bitcast i32 %i.i to float
24 %j.f.i = bitcast i32 %j.i to float
25 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 3, i32 0, i32 %arg6) #1
26 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 3, i32 0, i32 %arg6) #1
27 %tmp23 = fadd float %p2.i, 0xBFA99999A0000000
28 %tmp24 = fadd float %p2.i, 0x3FA99999A0000000
2829 %tmp25 = bitcast float %tmp23 to i32
2930 %tmp26 = insertelement <16 x i32> , i32 %tmp25, i32 1
3031 %tmp27 = insertelement <16 x i32> %tmp26, i32 undef, i32 2
5354 ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp49
5455 }
5556
56 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
57 declare float @llvm.SI.load.const(<16 x i8>, i32) #1
58 declare <4 x float> @llvm.SI.image.sample.c.d.o.v16i32(<16 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
57 ; Function Attrs: nounwind readnone
58 declare float @llvm.SI.load.const(<16 x i8>, i32) #0
5959
60 attributes #0 = { "InitialPSInputAddr"="36983" "target-cpu"="tonga" }
61 attributes #1 = { nounwind readnone }
60 ; Function Attrs: nounwind readnone
61 declare <4 x float> @llvm.SI.image.sample.c.d.o.v16i32(<16 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
62
63 ; Function Attrs: nounwind readnone
64 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #0
65
66 ; Function Attrs: nounwind readnone
67 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #0
68
69 ; Function Attrs: nounwind readnone
70 declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #0
71
72 attributes #0 = { nounwind readnone }
73 attributes #1 = { nounwind }
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test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll less more
None ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
1 ;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
2 ;RUN: llc < %s -march=amdgcn -mcpu=stoney -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
3 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
4
5 ;GCN-LABEL: {{^}}main:
6 ;GCN-NOT: s_wqm
7 ;GCN: s_mov_b32 m0
8 ;GCN-DAG: v_interp_mov_f32
9 ;GCN-DAG: v_interp_p1_f32
10 ;GCN-DAG: v_interp_p2_f32
11
12 define amdgpu_ps void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) {
13 main_body:
14 %5 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
15 %6 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %4)
16 %7 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %4)
17 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %6, float %7, float %7)
18 ret void
19 }
20
21 ; Thest that v_interp_p1 uses different source and destination registers
22 ; on 16 bank LDS chips.
23
24 ; 16BANK-LABEL: {{^}}v_interp_p1_bank16_bug:
25 ; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]]
26
27 define amdgpu_ps void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) {
28 main_body:
29 %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
30 %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
31 %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
32 %25 = call float @fabs(float %22)
33 %26 = call float @fabs(float %23)
34 %27 = call float @fabs(float %24)
35 %28 = call i32 @llvm.SI.packf16(float %25, float %26)
36 %29 = bitcast i32 %28 to float
37 %30 = call i32 @llvm.SI.packf16(float %27, float 1.000000e+00)
38 %31 = bitcast i32 %30 to float
39 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31)
40 ret void
41 }
42
43 ; Function Attrs: readnone
44 declare float @fabs(float) #1
45
46 ; Function Attrs: nounwind readnone
47 declare i32 @llvm.SI.packf16(float, float) #0
48
49 ; Function Attrs: nounwind readnone
50 declare float @llvm.SI.fs.constant(i32, i32, i32) #0
51
52 ; Function Attrs: nounwind readnone
53 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #0
54
55 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
56
57 attributes #0 = { nounwind readnone }
58 attributes #1 = { readnone }
None ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
1 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefixes=GCN,VI %s
0 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
1 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
2 ; RUN: llc -march=amdgcn -mcpu=kabini -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,16BANK %s
3 ; RUN: llc -march=amdgcn -mcpu=stoney -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,16BANK %s
4
25
36 ; GCN-LABEL: {{^}}v_interp:
47 ; GCN-NOT: s_wqm
169172 ret void
170173 }
171174
172 ; Function Attrs: nounwind readnone
175 ; Thest that v_interp_p1 uses different source and destination registers
176 ; on 16 bank LDS chips.
177
178 ; GCN-LABEL: {{^}}v_interp_p1_bank16_bug:
179 ; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]]
180 define amdgpu_ps void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg13, [17 x <4 x i32>] addrspace(2)* byval %arg14, [34 x <8 x i32>] addrspace(2)* byval %arg15, float inreg %arg16, i32 inreg %arg17, <2 x i32> %arg18, <2 x i32> %arg19, <2 x i32> %arg20, <3 x i32> %arg21, <2 x i32> %arg22, <2 x i32> %arg23, <2 x i32> %arg24, float %arg25, float %arg26, float %arg27, float %arg28, float %arg29, float %arg30, i32 %arg31, float %arg32, float %arg33) {
181 main_body:
182 %i.i = extractelement <2 x i32> %arg19, i32 0
183 %j.i = extractelement <2 x i32> %arg19, i32 1
184 %i.f.i = bitcast i32 %i.i to float
185 %j.f.i = bitcast i32 %j.i to float
186 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg17) #1
187 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg17) #1
188 %i.i7 = extractelement <2 x i32> %arg19, i32 0
189 %j.i8 = extractelement <2 x i32> %arg19, i32 1
190 %i.f.i9 = bitcast i32 %i.i7 to float
191 %j.f.i10 = bitcast i32 %j.i8 to float
192 %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 0, i32 %arg17) #1
193 %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 0, i32 %arg17) #1
194 %i.i1 = extractelement <2 x i32> %arg19, i32 0
195 %j.i2 = extractelement <2 x i32> %arg19, i32 1
196 %i.f.i3 = bitcast i32 %i.i1 to float
197 %j.f.i4 = bitcast i32 %j.i2 to float
198 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 0, i32 %arg17) #1
199 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 0, i32 %arg17) #1
200 %tmp = call float @llvm.fabs.f32(float %p2.i)
201 %tmp34 = call float @llvm.fabs.f32(float %p2.i12)
202 %tmp35 = call float @llvm.fabs.f32(float %p2.i6)
203 %tmp36 = call i32 @llvm.SI.packf16(float %tmp, float %tmp34)
204 %tmp37 = bitcast i32 %tmp36 to float
205 %tmp38 = call i32 @llvm.SI.packf16(float %tmp35, float 1.000000e+00)
206 %tmp39 = bitcast i32 %tmp38 to float
207 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp37, float %tmp39, float %tmp37, float %tmp39)
208 ret void
209 }
210
211 declare float @llvm.fabs.f32(float) #0
173212 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #0
174
175 ; Function Attrs: nounwind readnone
176213 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #0
177
178214 declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #0
179
215 declare i32 @llvm.SI.packf16(float, float) #0
180216 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
181217
182218 attributes #0 = { nounwind readnone }
219 attributes #1 = { nounwind }
1717 ; GCN-NEXT: s_or_b64 exec, exec, [[XOR_EXEC]]
1818 ; GCN-NEXT: [[FINAL_BB]]:
1919 ; GCN-NEXT: .Lfunc_end0
20 define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <8 x i32>] addrspace(2)* byval, i32 addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
20 define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([9 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <8 x i32>] addrspace(2)* byval %arg2, i32 addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, i32 %arg18, i32 %arg19, float %arg20, i32 %arg21) #0 {
2121 main_body:
22 %p83 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
23 %p87 = fmul float undef, %p83
22 %i.i = extractelement <2 x i32> %arg7, i32 0
23 %j.i = extractelement <2 x i32> %arg7, i32 1
24 %i.f.i = bitcast i32 %i.i to float
25 %j.f.i = bitcast i32 %j.i to float
26 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 1, i32 0, i32 %arg5) #2
27 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 1, i32 0, i32 %arg5) #2
28 %p87 = fmul float undef, %p2.i
2429 %p88 = fadd float %p87, undef
2530 %p93 = fadd float %p88, undef
2631 %p97 = fmul float %p93, undef
4449 }
4550
4651 ; Function Attrs: nounwind readnone
47 declare float @llvm.SI.load.const(<16 x i8>, i32) #1
52 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
4853
4954 ; Function Attrs: nounwind readnone
50 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
55 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
56
57 ; Function Attrs: nounwind readnone
58 declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1
59
60 ; Function Attrs: nounwind readnone
61 declare float @llvm.SI.load.const(<16 x i8>, i32) #1
5162
5263 ; Function Attrs: nounwind readnone
5364 declare float @llvm.fabs.f32(float) #1
6071
6172 attributes #0 = { "InitialPSInputAddr"="36983" }
6273 attributes #1 = { nounwind readnone }
74 attributes #2 = { nounwind }
0 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
11 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s
22
3 ; This test checks that no VGPR to SGPR copies are created by the register
4 ; allocator.
5
6
7 declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
8
3 ; Function Attrs: nounwind readnone
4 declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
95
106 ; CHECK-LABEL: {{^}}phi1:
117 ; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0
128 ; CHECK: v_mov_b32_e32 v{{[0-9]}}, [[DST]]
13 define amdgpu_ps void @phi1(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
9 define amdgpu_ps void @phi1(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #1 {
1410 main_body:
1511 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0
1612 %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
5753 %tmp37 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp36, !tbaa !0
5854 %tmp38 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg1, i32 0
5955 %tmp39 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp38, !tbaa !0
60 %tmp40 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg3, <2 x i32> %arg5)
61 %tmp41 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg3, <2 x i32> %arg5)
62 %tmp42 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %arg3, <2 x i32> %arg5)
63 %tmp43 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %arg3, <2 x i32> %arg5)
64 %tmp44 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %arg3, <2 x i32> %arg5)
65 %tmp45 = bitcast float %tmp40 to i32
66 %tmp46 = bitcast float %tmp41 to i32
56 %i.i = extractelement <2 x i32> %arg5, i32 0
57 %j.i = extractelement <2 x i32> %arg5, i32 1
58 %i.f.i = bitcast i32 %i.i to float
59 %j.f.i = bitcast i32 %j.i to float
60 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #0
61 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #0
62 %i.i19 = extractelement <2 x i32> %arg5, i32 0
63 %j.i20 = extractelement <2 x i32> %arg5, i32 1
64 %i.f.i21 = bitcast i32 %i.i19 to float
65 %j.f.i22 = bitcast i32 %j.i20 to float
66 %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 1, i32 0, i32 %arg3) #0
67 %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 1, i32 0, i32 %arg3) #0
68 %i.i13 = extractelement <2 x i32> %arg5, i32 0
69 %j.i14 = extractelement <2 x i32> %arg5, i32 1
70 %i.f.i15 = bitcast i32 %i.i13 to float
71 %j.f.i16 = bitcast i32 %j.i14 to float
72 %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 0, i32 1, i32 %arg3) #0
73 %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 0, i32 1, i32 %arg3) #0
74 %i.i7 = extractelement <2 x i32> %arg5, i32 0
75 %j.i8 = extractelement <2 x i32> %arg5, i32 1
76 %i.f.i9 = bitcast i32 %i.i7 to float
77 %j.f.i10 = bitcast i32 %j.i8 to float
78 %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 1, i32 %arg3) #0
79 %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 1, i32 %arg3) #0
80 %i.i1 = extractelement <2 x i32> %arg5, i32 0
81 %j.i2 = extractelement <2 x i32> %arg5, i32 1
82 %i.f.i3 = bitcast i32 %i.i1 to float
83 %j.f.i4 = bitcast i32 %j.i2 to float
84 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 1, i32 %arg3) #0
85 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 1, i32 %arg3) #0
86 %tmp45 = bitcast float %p2.i to i32
87 %tmp46 = bitcast float %p2.i24 to i32
6788 %tmp47 = insertelement <2 x i32> undef, i32 %tmp45, i32 0
6889 %tmp48 = insertelement <2 x i32> %tmp47, i32 %tmp46, i32 1
6990 %tmp39.bc = bitcast <16 x i8> %tmp39 to <4 x i32>
7091 %tmp49 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp48, <8 x i32> %tmp37, <4 x i32> %tmp39.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
7192 %tmp50 = extractelement <4 x float> %tmp49, i32 2
72 %tmp51 = call float @fabs(float %tmp50)
73 %tmp52 = fmul float %tmp42, %tmp42
74 %tmp53 = fmul float %tmp43, %tmp43
93 %tmp51 = call float @llvm.fabs.f32(float %tmp50)
94 %tmp52 = fmul float %p2.i18, %p2.i18
95 %tmp53 = fmul float %p2.i12, %p2.i12
7596 %tmp54 = fadd float %tmp53, %tmp52
76 %tmp55 = fmul float %tmp44, %tmp44
97 %tmp55 = fmul float %p2.i6, %p2.i6
7798 %tmp56 = fadd float %tmp54, %tmp55
7899 %tmp57 = call float @llvm.amdgcn.rsq.f32(float %tmp56)
79 %tmp58 = fmul float %tmp42, %tmp57
80 %tmp59 = fmul float %tmp43, %tmp57
81 %tmp60 = fmul float %tmp44, %tmp57
100 %tmp58 = fmul float %p2.i18, %tmp57
101 %tmp59 = fmul float %p2.i12, %tmp57
102 %tmp60 = fmul float %p2.i6, %tmp57
82103 %tmp61 = fmul float %tmp58, %tmp22
83104 %tmp62 = fmul float %tmp59, %tmp23
84105 %tmp63 = fadd float %tmp62, %tmp61
89110 %tmp68 = fadd float %tmp67, %tmp66
90111 %tmp69 = fmul float %tmp26, %tmp68
91112 %tmp70 = fmul float %tmp27, %tmp68
92 %tmp71 = call float @fabs(float %tmp69)
113 %tmp71 = call float @llvm.fabs.f32(float %tmp69)
93114 %tmp72 = fcmp olt float 0x3EE4F8B580000000, %tmp71
94115 %tmp73 = sext i1 %tmp72 to i32
95116 %tmp74 = bitcast i32 %tmp73 to float
109130
110131 ENDIF: ; preds = %IF, %main_body
111132 %temp4.0 = phi float [ %tmp83, %IF ], [ %tmp31, %main_body ]
112 %tmp84 = call float @fabs(float %tmp70)
133 %tmp84 = call float @llvm.fabs.f32(float %tmp70)
113134 %tmp85 = fcmp olt float 0x3EE4F8B580000000, %tmp84
114135 %tmp86 = sext i1 %tmp85 to i32
115136 %tmp87 = bitcast i32 %tmp86 to float
155176
156177 ; We just want ot make sure the program doesn't crash
157178 ; CHECK-LABEL: {{^}}loop:
158 define amdgpu_ps void @loop(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
179 define amdgpu_ps void @loop(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #1 {
159180 main_body:
160181 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0
161182 %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
192213 br label %LOOP
193214 }
194215
195 ; Function Attrs: nounwind readnone
196 declare float @llvm.SI.load.const(<16 x i8>, i32) #1
197
198 ; Function Attrs: readonly
199 declare float @fabs(float) #2
200
201 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
202
203 ; Function Attrs: nounwind readnone
204 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
205
206 ; Function Attrs: nounwind readnone
207 declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <8 x i32>, <16 x i8>, i32) #1
208
209 ; Function Attrs: readnone
210 declare float @llvm.amdgcn.rsq.f32(float) #1
211
212 declare float @llvm.exp2.f32(float) #1
213
214 ; Function Attrs: nounwind readnone
215 declare float @llvm.pow.f32(float, float) #1
216
217 ; Function Attrs: nounwind readnone
218 declare i32 @llvm.SI.packf16(float, float) #1
219
220216 ; This checks for a bug in the FixSGPRCopies pass where VReg96
221217 ; registers were being identified as an SGPR regclass which was causing
222218 ; an assertion failure.
233229 ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SAMPLE_LO]]:[[SAMPLE_HI]]{{\]}}
234230 ; CHECK: exp
235231 ; CHECK: s_endpgm
236 define amdgpu_ps void @sample_v3([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
232 define amdgpu_ps void @sample_v3([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #1 {
237233 entry:
238234 %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0
239235 %tmp21 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
297293 ; This test is just checking that we don't crash / assertion fail.
298294 ; CHECK-LABEL: {{^}}copy2:
299295 ; CHECK: s_endpgm
300 define amdgpu_ps void @copy2([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
296 define amdgpu_ps void @copy2([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #1 {
301297 entry:
302298 br label %LOOP68
303299
333329 ; [[END]]:
334330 ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]{{\]}}
335331 ; CHECK: s_endpgm
336 define amdgpu_ps void @sample_rsrc([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
332 define amdgpu_ps void @sample_rsrc([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #1 {
337333 bb:
338334 %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg1, i32 0, i32 0
339 %tmp22 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !2
335 %tmp22 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !3
340336 %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp22, i32 16)
341337 %tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %arg3, i32 0, i32 0
342 %tmp26 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp25, !tbaa !2
338 %tmp26 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp25, !tbaa !3
343339 %tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %arg2, i32 0, i32 0
344 %tmp28 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp27, !tbaa !2
345 %tmp29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg5, <2 x i32> %arg7)
346 %tmp30 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg5, <2 x i32> %arg7)
340 %tmp28 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp27, !tbaa !3
341 %i.i = extractelement <2 x i32> %arg7, i32 0
342 %j.i = extractelement <2 x i32> %arg7, i32 1
343 %i.f.i = bitcast i32 %i.i to float
344 %j.f.i = bitcast i32 %j.i to float
345 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #1
346 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #1
347 %i.i1 = extractelement <2 x i32> %arg7, i32 0
348 %j.i2 = extractelement <2 x i32> %arg7, i32 1
349 %i.f.i3 = bitcast i32 %i.i1 to float
350 %j.f.i4 = bitcast i32 %j.i2 to float
351 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg5) #1
352 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg5) #1
347353 %tmp31 = bitcast float %tmp23 to i32
348354 %tmp36 = icmp ne i32 %tmp31, 0
349355 br i1 %tmp36, label %bb38, label %bb80
350356
351357 bb38: ; preds = %bb
352 %tmp52 = bitcast float %tmp29 to i32
353 %tmp53 = bitcast float %tmp30 to i32
358 %tmp52 = bitcast float %p2.i to i32
359 %tmp53 = bitcast float %p2.i6 to i32
354360 %tmp54 = insertelement <2 x i32> undef, i32 %tmp52, i32 0
355361 %tmp55 = insertelement <2 x i32> %tmp54, i32 %tmp53, i32 1
356362 %tmp56 = bitcast <8 x i32> %tmp26 to <8 x i32>
358364 br label %bb71
359365
360366 bb80: ; preds = %bb
361 %tmp81 = bitcast float %tmp29 to i32
362 %tmp82 = bitcast float %tmp30 to i32
367 %tmp81 = bitcast float %p2.i to i32
368 %tmp82 = bitcast float %p2.i6 to i32
363369 %tmp82.2 = add i32 %tmp82, 1
364370 %tmp83 = insertelement <2 x i32> undef, i32 %tmp81, i32 0
365371 %tmp84 = insertelement <2 x i32> %tmp83, i32 %tmp82.2, i32 1
377383 ; Check the the resource descriptor is stored in an sgpr.
378384 ; CHECK-LABEL: {{^}}mimg_srsrc_sgpr:
379385 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
380 define amdgpu_ps void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #0 {
381 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
386 define amdgpu_ps void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #1 {
387 bb:
388 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1
382389 %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i32 0, i32 %tid
383390 %tmp8 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp7, align 32, !tbaa !0
384391 %tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> , <8 x i32> %tmp8, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
392399 ; Check the the sampler is stored in an sgpr.
393400 ; CHECK-LABEL: {{^}}mimg_ssamp_sgpr:
394401 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
395 define amdgpu_ps void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(2)* byval %arg) #0 {
396 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
402 define amdgpu_ps void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(2)* byval %arg) #1 {
403 bb:
404 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1
397405 %tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg, i32 0, i32 %tid
398406 %tmp8 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp7, align 16, !tbaa !0
399407 %tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> , <8 x i32> undef, <4 x i32> %tmp8, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
404412 ret void
405413 }
406414
407 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
408
409 attributes #0 = { nounwind }
410 attributes #1 = { nounwind readnone }
415 ; Function Attrs: nounwind readnone
416 declare float @llvm.SI.load.const(<16 x i8>, i32) #0
417
418 ; Function Attrs: nounwind readnone
419 declare float @llvm.fabs.f32(float) #0
420
421 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
422
423 ; Function Attrs: nounwind readnone
424 declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <8 x i32>, <16 x i8>, i32) #0
425
426 ; Function Attrs: nounwind readnone
427 declare float @llvm.amdgcn.rsq.f32(float) #0
428
429 ; Function Attrs: nounwind readnone
430 declare float @llvm.exp2.f32(float) #0
431
432 ; Function Attrs: nounwind readnone
433 declare float @llvm.pow.f32(float, float) #0
434
435 ; Function Attrs: nounwind readnone
436 declare i32 @llvm.SI.packf16(float, float) #0
437
438 ; Function Attrs: nounwind readnone
439 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
440
441 ; Function Attrs: nounwind readnone
442 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #0
443
444 ; Function Attrs: nounwind readnone
445 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #0
446
447 ; Function Attrs: nounwind readnone
448 declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #0
449
450 attributes #0 = { nounwind readnone }
451 attributes #1 = { nounwind }
411452 attributes #2 = { nounwind readonly }
412453
413454 !0 = !{!1, !1, i64 0, i32 1}
414 !1 = !{!"const", !3}
415 !2 = !{!1, !1, i64 0}
416 !3 = !{!"tbaa root"}
455 !1 = !{!"const", !2}
456 !2 = !{!"tbaa root"}
457 !3 = !{!1, !1, i64 0}
55
66 ; CHECK: {{^}}main:
77 ; CHECK: image_sample_b v{{\[[0-9]:[0-9]\]}}, v{{\[[0-9]:[0-9]\]}}, s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0xf
8 define amdgpu_ps void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) {
8 define amdgpu_ps void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
99 main_body:
1010 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0
1111 %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0
1414 %tmp23 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp22, !tbaa !0
1515 %tmp24 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg1, i32 0
1616 %tmp25 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp24, !tbaa !0
17 %tmp26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg3, <2 x i32> %arg5)
18 %tmp27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg3, <2 x i32> %arg5)
17 %i.i = extractelement <2 x i32> %arg5, i32 0
18 %j.i = extractelement <2 x i32> %arg5, i32 1
19 %i.f.i = bitcast i32 %i.i to float
20 %j.f.i = bitcast i32 %j.i to float
21 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #0
22 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #0
23 %i.i1 = extractelement <2 x i32> %arg5, i32 0
24 %j.i2 = extractelement <2 x i32> %arg5, i32 1
25 %i.f.i3 = bitcast i32 %i.i1 to float
26 %j.f.i4 = bitcast i32 %j.i2 to float
27 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg3) #0
28 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg3) #0
1929 %tmp28 = bitcast float %tmp21 to i32
20 %tmp29 = bitcast float %tmp26 to i32
21 %tmp30 = bitcast float %tmp27 to i32
30 %tmp29 = bitcast float %p2.i to i32
31 %tmp30 = bitcast float %p2.i6 to i32
2232 %tmp31 = insertelement <4 x i32> undef, i32 %tmp28, i32 0
2333 %tmp32 = insertelement <4 x i32> %tmp31, i32 %tmp29, i32 1
2434 %tmp33 = insertelement <4 x i32> %tmp32, i32 %tmp30, i32 2
3747 declare float @llvm.SI.load.const(<16 x i8>, i32) #1
3848
3949 ; Function Attrs: nounwind readnone
40 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
41
4250 declare <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
43
4451
4552 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
4653
54 ; Function Attrs: nounwind readnone
55 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
4756
57 ; Function Attrs: nounwind readnone
58 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
59
60 ; Function Attrs: nounwind readnone
61 declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1
62
63 attributes #0 = { nounwind }
4864 attributes #1 = { nounwind readnone }
4965
5066 !0 = !{!1, !1, i64 0, i32 1}
1515 ; CHECK: s_waitcnt vmcnt(0)
1616 ; CHECK: exp
1717 ; CHECK: s_endpgm
18 define amdgpu_ps void @main([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
18 define amdgpu_ps void @main([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) {
1919 main_body:
2020 %tmp = bitcast [34 x <8 x i32>] addrspace(2)* %arg3 to <32 x i8> addrspace(2)*
2121 %tmp22 = load <32 x i8>, <32 x i8> addrspace(2)* %tmp, align 32, !tbaa !0
2222 %tmp23 = bitcast [17 x <4 x i32>] addrspace(2)* %arg2 to <16 x i8> addrspace(2)*
2323 %tmp24 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp23, align 16, !tbaa !0
24 %tmp25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg5, <2 x i32> %arg11)
25 %tmp26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg5, <2 x i32> %arg11)
26 %tmp27 = bitcast float %tmp25 to i32
27 %tmp28 = bitcast float %tmp26 to i32
24 %i.i = extractelement <2 x i32> %arg11, i32 0
25 %j.i = extractelement <2 x i32> %arg11, i32 1
26 %i.f.i = bitcast i32 %i.i to float
27 %j.f.i = bitcast i32 %j.i to float
28 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #1
29 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #1
30 %i.i1 = extractelement <2 x i32> %arg11, i32 0
31 %j.i2 = extractelement <2 x i32> %arg11, i32 1
32 %i.f.i3 = bitcast i32 %i.i1 to float
33 %j.f.i4 = bitcast i32 %j.i2 to float
34 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg5) #1
35 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg5) #1
36 %tmp27 = bitcast float %p2.i to i32
37 %tmp28 = bitcast float %p2.i6 to i32
2838 %tmp29 = insertelement <2 x i32> undef, i32 %tmp27, i32 0
2939 %tmp30 = insertelement <2 x i32> %tmp29, i32 %tmp28, i32 1
3040 %tmp22.bc = bitcast <32 x i8> %tmp22 to <8 x i32>
4353 }
4454
4555 ; Function Attrs: nounwind readnone
46 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
47
48 declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
49
56 declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
5057
5158 ; Function Attrs: nounwind readnone
52 declare i32 @llvm.SI.packf16(float, float) #1
59 declare i32 @llvm.SI.packf16(float, float) #0
5360
5461 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
5562
56 attributes #1 = { nounwind readnone }
63 ; Function Attrs: nounwind readnone
64 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #0
65
66 ; Function Attrs: nounwind readnone
67 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #0
68
69 attributes #0 = { nounwind readnone }
70 attributes #1 = { nounwind }
5771
5872 !0 = !{!1, !1, i64 0, i32 1}
5973 !1 = !{!"const", !2}
22
33 ; These tests check that the compiler won't crash when it needs to spill
44 ; SGPRs.
5
65
76 @ddxy_lds = external addrspace(3) global [64 x i32]
87
9695 %tmp89 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp88, !tbaa !0
9796 %tmp90 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 7
9897 %tmp91 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp90, !tbaa !0
99 %tmp92 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg4, <2 x i32> %arg6)
100 %tmp93 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg4, <2 x i32> %arg6)
101 %tmp94 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %arg4, <2 x i32> %arg6)
102 %tmp95 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %arg4, <2 x i32> %arg6)
103 %tmp96 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %arg4, <2 x i32> %arg6)
104 %tmp97 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %arg4, <2 x i32> %arg6)
105 %tmp98 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %arg4, <2 x i32> %arg6)
106 %tmp99 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %arg4, <2 x i32> %arg6)
107 %tmp100 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %arg4, <2 x i32> %arg6)
108 %tmp101 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %arg4, <2 x i32> %arg6)
109 %tmp102 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %arg4, <2 x i32> %arg6)
110 %tmp103 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %arg4, <2 x i32> %arg6)
111 %tmp104 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %arg4, <2 x i32> %arg6)
112 %tmp105 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %arg4, <2 x i32> %arg6)
113 %tmp106 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %arg4, <2 x i32> %arg6)
114 %tmp107 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %arg4, <2 x i32> %arg6)
115 %tmp108 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %arg4, <2 x i32> %arg6)
98 %i.i = extractelement <2 x i32> %arg6, i32 0
99 %j.i = extractelement <2 x i32> %arg6, i32 1
100 %i.f.i = bitcast i32 %i.i to float
101 %j.f.i = bitcast i32 %j.i to float
102 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg4) #1
103 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg4) #1
104 %i.i91 = extractelement <2 x i32> %arg6, i32 0
105 %j.i92 = extractelement <2 x i32> %arg6, i32 1
106 %i.f.i93 = bitcast i32 %i.i91 to float
107 %j.f.i94 = bitcast i32 %j.i92 to float
108 %p1.i95 = call float @llvm.amdgcn.interp.p1(float %i.f.i93, i32 1, i32 0, i32 %arg4) #1
109 %p2.i96 = call float @llvm.amdgcn.interp.p2(float %p1.i95, float %j.f.i94, i32 1, i32 0, i32 %arg4) #1
110 %i.i85 = extractelement <2 x i32> %arg6, i32 0
111 %j.i86 = extractelement <2 x i32> %arg6, i32 1
112 %i.f.i87 = bitcast i32 %i.i85 to float
113 %j.f.i88 = bitcast i32 %j.i86 to float
114 %p1.i89 = call float @llvm.amdgcn.interp.p1(float %i.f.i87, i32 0, i32 1, i32 %arg4) #1
115 %p2.i90 = call float @llvm.amdgcn.interp.p2(float %p1.i89, float %j.f.i88, i32 0, i32 1, i32 %arg4) #1
116 %i.i79 = extractelement <2 x i32> %arg6, i32 0
117 %j.i80 = extractelement <2 x i32> %arg6, i32 1
118 %i.f.i81 = bitcast i32 %i.i79 to float
119 %j.f.i82 = bitcast i32 %j.i80 to float
120 %p1.i83 = call float @llvm.amdgcn.interp.p1(float %i.f.i81, i32 1, i32 1, i32 %arg4) #1
121 %p2.i84 = call float @llvm.amdgcn.interp.p2(float %p1.i83, float %j.f.i82, i32 1, i32 1, i32 %arg4) #1
122 %i.i73 = extractelement <2 x i32> %arg6, i32 0
123 %j.i74 = extractelement <2 x i32> %arg6, i32 1
124 %i.f.i75 = bitcast i32 %i.i73 to float
125 %j.f.i76 = bitcast i32 %j.i74 to float
126 %p1.i77 = call float @llvm.amdgcn.interp.p1(float %i.f.i75, i32 2, i32 1, i32 %arg4) #1
127 %p2.i78 = call float @llvm.amdgcn.interp.p2(float %p1.i77, float %j.f.i76, i32 2, i32 1, i32 %arg4) #1
128 %i.i67 = extractelement <2 x i32> %arg6, i32 0
129 %j.i68 = extractelement <2 x i32> %arg6, i32 1
130 %i.f.i69 = bitcast i32 %i.i67 to float
131 %j.f.i70 = bitcast i32 %j.i68 to float
132 %p1.i71 = call float @llvm.amdgcn.interp.p1(float %i.f.i69, i32 0, i32 2, i32 %arg4) #1
133 %p2.i72 = call float @llvm.amdgcn.interp.p2(float %p1.i71, float %j.f.i70, i32 0, i32 2, i32 %arg4) #1
134 %i.i61 = extractelement <2 x i32> %arg6, i32 0
135 %j.i62 = extractelement <2 x i32> %arg6, i32 1
136 %i.f.i63 = bitcast i32 %i.i61 to float
137 %j.f.i64 = bitcast i32 %j.i62 to float
138 %p1.i65 = call float @llvm.amdgcn.interp.p1(float %i.f.i63, i32 1, i32 2, i32 %arg4) #1
139 %p2.i66 = call float @llvm.amdgcn.interp.p2(float %p1.i65, float %j.f.i64, i32 1, i32 2, i32 %arg4) #1
140 %i.i55 = extractelement <2 x i32> %arg6, i32 0
141 %j.i56 = extractelement <2 x i32> %arg6, i32 1
142 %i.f.i57 = bitcast i32 %i.i55 to float
143 %j.f.i58 = bitcast i32 %j.i56 to float
144 %p1.i59 = call float @llvm.amdgcn.interp.p1(float %i.f.i57, i32 2, i32 2, i32 %arg4) #1
145 %p2.i60 = call float @llvm.amdgcn.interp.p2(float %p1.i59, float %j.f.i58, i32 2, i32 2, i32 %arg4) #1
146 %i.i49 = extractelement <2 x i32> %arg6, i32 0
147 %j.i50 = extractelement <2 x i32> %arg6, i32 1
148 %i.f.i51 = bitcast i32 %i.i49 to float
149 %j.f.i52 = bitcast i32 %j.i50 to float
150 %p1.i53 = call float @llvm.amdgcn.interp.p1(float %i.f.i51, i32 0, i32 3, i32 %arg4) #1
151 %p2.i54 = call float @llvm.amdgcn.interp.p2(float %p1.i53, float %j.f.i52, i32 0, i32 3, i32 %arg4) #1
152 %i.i43 = extractelement <2 x i32> %arg6, i32 0
153 %j.i44 = extractelement <2 x i32> %arg6, i32 1
154 %i.f.i45 = bitcast i32 %i.i43 to float
155 %j.f.i46 = bitcast i32 %j.i44 to float
156 %p1.i47 = call float @llvm.amdgcn.interp.p1(float %i.f.i45, i32 1, i32 3, i32 %arg4) #1
157 %p2.i48 = call float @llvm.amdgcn.interp.p2(float %p1.i47, float %j.f.i46, i32 1, i32 3, i32 %arg4) #1
158 %i.i37 = extractelement <2 x i32> %arg6, i32 0
159 %j.i38 = extractelement <2 x i32> %arg6, i32 1
160 %i.f.i39 = bitcast i32 %i.i37 to float
161 %j.f.i40 = bitcast i32 %j.i38 to float
162 %p1.i41 = call float @llvm.amdgcn.interp.p1(float %i.f.i39, i32 2, i32 3, i32 %arg4) #1
163 %p2.i42 = call float @llvm.amdgcn.interp.p2(float %p1.i41, float %j.f.i40, i32 2, i32 3, i32 %arg4) #1
164 %i.i31 = extractelement <2 x i32> %arg6, i32 0
165 %j.i32 = extractelement <2 x i32> %arg6, i32 1
166 %i.f.i33 = bitcast i32 %i.i31 to float
167 %j.f.i34 = bitcast i32 %j.i32 to float
168 %p1.i35 = call float @llvm.amdgcn.interp.p1(float %i.f.i33, i32 0, i32 4, i32 %arg4) #1
169 %p2.i36 = call float @llvm.amdgcn.interp.p2(float %p1.i35, float %j.f.i34, i32 0, i32 4, i32 %arg4) #1
170 %i.i25 = extractelement <2 x i32> %arg6, i32 0
171 %j.i26 = extractelement <2 x i32> %arg6, i32 1
172 %i.f.i27 = bitcast i32 %i.i25 to float
173 %j.f.i28 = bitcast i32 %j.i26 to float
174 %p1.i29 = call float @llvm.amdgcn.interp.p1(float %i.f.i27, i32 1, i32 4, i32 %arg4) #1
175 %p2.i30 = call float @llvm.amdgcn.interp.p2(float %p1.i29, float %j.f.i28, i32 1, i32 4, i32 %arg4) #1
176 %i.i19 = extractelement <2 x i32> %arg6, i32 0
177 %j.i20 = extractelement <2 x i32> %arg6, i32 1
178 %i.f.i21 = bitcast i32 %i.i19 to float
179 %j.f.i22 = bitcast i32 %j.i20 to float
180 %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 2, i32 4, i32 %arg4) #1
181 %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 2, i32 4, i32 %arg4) #1
182 %i.i13 = extractelement <2 x i32> %arg6, i32 0
183 %j.i14 = extractelement <2 x i32> %arg6, i32 1
184 %i.f.i15 = bitcast i32 %i.i13 to float
185 %j.f.i16 = bitcast i32 %j.i14 to float
186 %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 0, i32 5, i32 %arg4) #1
187 %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 0, i32 5, i32 %arg4) #1
188 %i.i7 = extractelement <2 x i32> %arg6, i32 0
189 %j.i8 = extractelement <2 x i32> %arg6, i32 1
190 %i.f.i9 = bitcast i32 %i.i7 to float
191 %j.f.i10 = bitcast i32 %j.i8 to float
192 %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 5, i32 %arg4) #1
193 %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 5, i32 %arg4) #1
194 %i.i1 = extractelement <2 x i32> %arg6, i32 0
195 %j.i2 = extractelement <2 x i32> %arg6, i32 1
196 %i.f.i3 = bitcast i32 %i.i1 to float
197 %j.f.i4 = bitcast i32 %j.i2 to float
198 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 5, i32 %arg4) #1
199 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 5, i32 %arg4) #1
116200 %mbcnt.lo.0 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
117201 %tmp109 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo.0)
118202 %tmp110 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp109
119 %tmp111 = bitcast float %tmp92 to i32
203 %tmp111 = bitcast float %p2.i to i32
120204 store i32 %tmp111, i32 addrspace(3)* %tmp110
121 %tmp112 = bitcast float %tmp93 to i32
205 %tmp112 = bitcast float %p2.i96 to i32
122206 store i32 %tmp112, i32 addrspace(3)* %tmp110
123207 %mbcnt.lo.1 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
124208 %tmp113 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo.1)
127211 %tmp116 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp115
128212 %tmp117 = add i32 %tmp115, 1
129213 %tmp118 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp117
130 %tmp119 = bitcast float %tmp92 to i32
214 %tmp119 = bitcast float %p2.i to i32
131215 store i32 %tmp119, i32 addrspace(3)* %tmp114
132216 %tmp120 = load i32, i32 addrspace(3)* %tmp116
133217 %tmp121 = bitcast i32 %tmp120 to float
134218 %tmp122 = load i32, i32 addrspace(3)* %tmp118
135219 %tmp123 = bitcast i32 %tmp122 to float
136220 %tmp124 = fsub float %tmp123, %tmp121
137 %tmp125 = bitcast float %tmp93 to i32
221 %tmp125 = bitcast float %p2.i96 to i32
138222 store i32 %tmp125, i32 addrspace(3)* %tmp114
139223 %tmp126 = load i32, i32 addrspace(3)* %tmp116
140224 %tmp127 = bitcast i32 %tmp126 to float
147231 %tmp134 = insertelement <4 x float> %tmp133, float %tmp130, i32 3
148232 %tmp135 = extractelement <4 x float> %tmp134, i32 0
149233 %tmp136 = extractelement <4 x float> %tmp134, i32 1
150 %tmp137 = fmul float %tmp59, %tmp92
151 %tmp138 = fmul float %tmp59, %tmp93
152 %tmp139 = fmul float %tmp59, %tmp93
153 %tmp140 = fmul float %tmp59, %tmp93
234 %tmp137 = fmul float %tmp59, %p2.i
235 %tmp138 = fmul float %tmp59, %p2.i96
236 %tmp139 = fmul float %tmp59, %p2.i96
237 %tmp140 = fmul float %tmp59, %p2.i96
154238 %mbcnt.lo.2 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
155239 %tmp141 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo.2)
156240 %tmp142 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp141
203287 %tmp180 = insertelement <4 x float> %tmp179, float %tmp176, i32 3
204288 %tmp181 = extractelement <4 x float> %tmp180, i32 0
205289 %tmp182 = extractelement <4 x float> %tmp180, i32 1
206 %tmp183 = fdiv float 1.000000e+00, %tmp96
290 %tmp183 = fdiv float 1.000000e+00, %p2.i78
207291 %tmp184 = fmul float %tmp32, %tmp183
208292 %tmp185 = fcmp uge float 1.000000e+00, %tmp184
209293 %tmp186 = select i1 %tmp185, float %tmp184, float 1.000000e+00
210294 %tmp187 = fmul float %tmp186, %tmp29
211 %tmp188 = call float @ceil(float %tmp187)
295 %tmp188 = call float @llvm.ceil.f32(float %tmp187)
212296 %tmp189 = fcmp uge float 3.000000e+00, %tmp188
213297 %tmp190 = select i1 %tmp189, float 3.000000e+00, float %tmp188
214298 %tmp191 = fdiv float 1.000000e+00, %tmp190
215299 %tmp192 = fdiv float 1.000000e+00, %tmp29
216300 %tmp193 = fmul float %tmp190, %tmp192
217301 %tmp194 = fmul float %tmp30, %tmp193
218 %tmp195 = fmul float %tmp94, %tmp94
219 %tmp196 = fmul float %tmp95, %tmp95
302 %tmp195 = fmul float %p2.i90, %p2.i90
303 %tmp196 = fmul float %p2.i84, %p2.i84
220304 %tmp197 = fadd float %tmp196, %tmp195
221 %tmp198 = fmul float %tmp96, %tmp96
305 %tmp198 = fmul float %p2.i78, %p2.i78
222306 %tmp199 = fadd float %tmp197, %tmp198
223307 %tmp200 = call float @llvm.amdgcn.rsq.f32(float %tmp199)
224 %tmp201 = fmul float %tmp94, %tmp200
225 %tmp202 = fmul float %tmp95, %tmp200
308 %tmp201 = fmul float %p2.i90, %tmp200
309 %tmp202 = fmul float %p2.i84, %tmp200
226310 %tmp203 = fmul float %tmp201, %tmp28
227311 %tmp204 = fmul float %tmp202, %tmp28
228312 %tmp205 = fmul float %tmp203, -1.000000e+00
230314 %tmp207 = fmul float %tmp205, %tmp31
231315 %tmp208 = fmul float %tmp206, %tmp31
232316 %tmp209 = fsub float -0.000000e+00, %tmp207
233 %tmp210 = fadd float %tmp92, %tmp209
317 %tmp210 = fadd float %p2.i, %tmp209
234318 %tmp211 = fsub float -0.000000e+00, %tmp208
235 %tmp212 = fadd float %tmp93, %tmp211
319 %tmp212 = fadd float %p2.i96, %tmp211
236320 %tmp213 = fmul float %tmp205, %tmp191
237321 %tmp214 = fmul float %tmp206, %tmp191
238322 %tmp215 = fmul float -1.000000e+00, %tmp191
428512 %tmp377 = extractelement <4 x float> %tmp375, i32 1
429513 %tmp378 = extractelement <4 x float> %tmp375, i32 2
430514 %tmp379 = extractelement <4 x float> %tmp375, i32 3
431 %tmp380 = fsub float -0.000000e+00, %tmp94
432 %tmp381 = fsub float -0.000000e+00, %tmp95
433 %tmp382 = fsub float -0.000000e+00, %tmp96
515 %tmp380 = fsub float -0.000000e+00, %p2.i90
516 %tmp381 = fsub float -0.000000e+00, %p2.i84
517 %tmp382 = fsub float -0.000000e+00, %p2.i78
434518 %tmp383 = fmul float %tmp358, %tmp380
435519 %tmp384 = fmul float %tmp359, %tmp381
436520 %tmp385 = fadd float %tmp384, %tmp383
448532 %tmp397 = fadd float %tmp381, %tmp396
449533 %tmp398 = fsub float -0.000000e+00, %tmp393
450534 %tmp399 = fadd float %tmp382, %tmp398
451 %tmp400 = fmul float %tmp395, %tmp97
452 %tmp401 = fmul float %tmp395, %tmp98
453 %tmp402 = fmul float %tmp395, %tmp99
454 %tmp403 = fmul float %tmp397, %tmp100
535 %tmp400 = fmul float %tmp395, %p2.i72
536 %tmp401 = fmul float %tmp395, %p2.i66
537 %tmp402 = fmul float %tmp395, %p2.i60
538 %tmp403 = fmul float %tmp397, %p2.i54
455539 %tmp404 = fadd float %tmp403, %tmp400
456 %tmp405 = fmul float %tmp397, %tmp101
540 %tmp405 = fmul float %tmp397, %p2.i48
457541 %tmp406 = fadd float %tmp405, %tmp401
458 %tmp407 = fmul float %tmp397, %tmp102
542 %tmp407 = fmul float %tmp397, %p2.i42
459543 %tmp408 = fadd float %tmp407, %tmp402
460 %tmp409 = fmul float %tmp399, %tmp103
544 %tmp409 = fmul float %tmp399, %p2.i36
461545 %tmp410 = fadd float %tmp409, %tmp404
462 %tmp411 = fmul float %tmp399, %tmp104
546 %tmp411 = fmul float %tmp399, %p2.i30
463547 %tmp412 = fadd float %tmp411, %tmp406
464 %tmp413 = fmul float %tmp399, %tmp105
548 %tmp413 = fmul float %tmp399, %p2.i24
465549 %tmp414 = fadd float %tmp413, %tmp408
466550 %tmp415 = bitcast float %tmp135 to i32
467551 %tmp416 = bitcast float %tmp181 to i32
506590 %tmp454 = extractelement <4 x float> %tmp452, i32 1
507591 %tmp455 = extractelement <4 x float> %tmp452, i32 2
508592 %tmp456 = extractelement <4 x float> %tmp452, i32 3
509 %tmp457 = call float @fabs(float %tmp455)
593 %tmp457 = call float @llvm.fabs.f32(float %tmp455)
510594 %tmp458 = fdiv float 1.000000e+00, %tmp457
511595 %tmp459 = fmul float %tmp453, %tmp458
512596 %tmp460 = fadd float %tmp459, 1.500000e+00
530614 %tmp477 = fadd float %tmp476, %tmp329
531615 %tmp478 = fmul float %tmp432, %tmp473
532616 %tmp479 = fadd float %tmp478, %tmp330
533 %tmp480 = fmul float %tmp106, %tmp106
534 %tmp481 = fmul float %tmp107, %tmp107
617 %tmp480 = fmul float %p2.i18, %p2.i18
618 %tmp481 = fmul float %p2.i12, %p2.i12
535619 %tmp482 = fadd float %tmp481, %tmp480
536 %tmp483 = fmul float %tmp108, %tmp108
620 %tmp483 = fmul float %p2.i6, %p2.i6
537621 %tmp484 = fadd float %tmp482, %tmp483
538622 %tmp485 = call float @llvm.amdgcn.rsq.f32(float %tmp484)
539 %tmp486 = fmul float %tmp106, %tmp485
540 %tmp487 = fmul float %tmp107, %tmp485
541 %tmp488 = fmul float %tmp108, %tmp485
623 %tmp486 = fmul float %p2.i18, %tmp485
624 %tmp487 = fmul float %p2.i12, %tmp485
625 %tmp488 = fmul float %p2.i6, %tmp485
542626 %tmp489 = fmul float %tmp376, %tmp39
543627 %tmp490 = fmul float %tmp377, %tmp40
544628 %tmp491 = fmul float %tmp378, %tmp41
559643 %tmp506 = fadd float %tmp487, %tmp505
560644 %tmp507 = fsub float -0.000000e+00, %tmp502
561645 %tmp508 = fadd float %tmp488, %tmp507
562 %tmp509 = fmul float %tmp94, %tmp94
563 %tmp510 = fmul float %tmp95, %tmp95
646 %tmp509 = fmul float %p2.i90, %p2.i90
647 %tmp510 = fmul float %p2.i84, %p2.i84
564648 %tmp511 = fadd float %tmp510, %tmp509
565 %tmp512 = fmul float %tmp96, %tmp96
649 %tmp512 = fmul float %p2.i78, %p2.i78
566650 %tmp513 = fadd float %tmp511, %tmp512
567651 %tmp514 = call float @llvm.amdgcn.rsq.f32(float %tmp513)
568 %tmp515 = fmul float %tmp94, %tmp514
569 %tmp516 = fmul float %tmp95, %tmp514
570 %tmp517 = fmul float %tmp96, %tmp514
652 %tmp515 = fmul float %p2.i90, %tmp514
653 %tmp516 = fmul float %p2.i84, %tmp514
654 %tmp517 = fmul float %p2.i78, %tmp514
571655 %tmp518 = fmul float %tmp504, %tmp515
572656 %tmp519 = fmul float %tmp506, %tmp516
573657 %tmp520 = fadd float %tmp519, %tmp518
816900 %tmp160 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp159, !tbaa !0
817901 %tmp161 = fcmp ugt float %arg17, 0.000000e+00
818902 %tmp162 = select i1 %tmp161, float 1.000000e+00, float 0.000000e+00
819 %tmp163 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg4, <2 x i32> %arg6)
820 %tmp164 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg4, <2 x i32> %arg6)
821 %tmp165 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %arg4, <2 x i32> %arg6)
822 %tmp166 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %arg4, <2 x i32> %arg6)
823 %tmp167 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %arg4, <2 x i32> %arg6)
824 %tmp168 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %arg4, <2 x i32> %arg6)
825 %tmp169 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %arg4, <2 x i32> %arg6)
826 %tmp170 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %arg4, <2 x i32> %arg6)
827 %tmp171 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %arg4, <2 x i32> %arg6)
828 %tmp172 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %arg4, <2 x i32> %arg6)
829 %tmp173 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %arg4, <2 x i32> %arg6)
830 %tmp174 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %arg4, <2 x i32> %arg6)
831 %tmp175 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %arg4, <2 x i32> %arg6)
832 %tmp176 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %arg4, <2 x i32> %arg6)
833 %tmp177 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %arg4, <2 x i32> %arg6)
834 %tmp178 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %arg4, <2 x i32> %arg6)
835 %tmp179 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %arg4, <2 x i32> %arg6)
836 %tmp180 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %arg4, <2 x i32> %arg6)
837 %tmp181 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %arg4, <2 x i32> %arg6)
838 %tmp182 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %arg4, <2 x i32> %arg6)
839 %tmp183 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %arg4, <2 x i32> %arg6)
840 %tmp184 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %arg4, <2 x i32> %arg6)
841 %tmp185 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %arg4, <2 x i32> %arg6)
842 %tmp186 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %arg4, <2 x i32> %arg6)
843 %tmp187 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %arg4, <2 x i32> %arg6)
844 %tmp188 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %arg4, <2 x i32> %arg6)
845 %tmp189 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %arg4, <2 x i32> %arg6)
846 %tmp190 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %arg4, <2 x i32> %arg6)
847 %tmp191 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %arg4, <2 x i32> %arg6)
848 %tmp192 = call float @llvm.SI.fs.interp(i32 1, i32 7, i32 %arg4, <2 x i32> %arg6)
849 %tmp193 = call float @llvm.SI.fs.interp(i32 2, i32 7, i32 %arg4, <2 x i32> %arg6)
850 %tmp194 = call float @llvm.SI.fs.interp(i32 3, i32 7, i32 %arg4, <2 x i32> %arg6)
903 %i.i = extractelement <2 x i32> %arg6, i32 0
904 %j.i = extractelement <2 x i32> %arg6, i32 1
905 %i.f.i = bitcast i32 %i.i to float
906 %j.f.i = bitcast i32 %j.i to float
907 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg4) #1
908 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg4) #1
909 %i.i181 = extractelement <2 x i32> %arg6, i32 0
910 %j.i182 = extractelement <2 x i32> %arg6, i32 1
911 %i.f.i183 = bitcast i32 %i.i181 to float
912 %j.f.i184 = bitcast i32 %j.i182 to float
913 %p1.i185 = call float @llvm.amdgcn.interp.p1(float %i.f.i183, i32 1, i32 0, i32 %arg4) #1
914 %p2.i186 = call float @llvm.amdgcn.interp.p2(float %p1.i185, float %j.f.i184, i32 1, i32 0, i32 %arg4) #1
915 %i.i175 = extractelement <2 x i32> %arg6, i32 0
916 %j.i176 = extractelement <2 x i32> %arg6, i32 1
917 %i.f.i177 = bitcast i32 %i.i175 to float
918 %j.f.i178 = bitcast i32 %j.i176 to float
919 %p1.i179 = call float @llvm.amdgcn.interp.p1(float %i.f.i177, i32 2, i32 0, i32 %arg4) #1
920 %p2.i180 = call float @llvm.amdgcn.interp.p2(float %p1.i179, float %j.f.i178, i32 2, i32 0, i32 %arg4) #1
921 %i.i169 = extractelement <2 x i32> %arg6, i32 0
922 %j.i170 = extractelement <2 x i32> %arg6, i32 1
923 %i.f.i171 = bitcast i32 %i.i169 to float
924 %j.f.i172 = bitcast i32 %j.i170 to float
925 %p1.i173 = call float @llvm.amdgcn.interp.p1(float %i.f.i171, i32 3, i32 0, i32 %arg4) #1
926 %p2.i174 = call float @llvm.amdgcn.interp.p2(float %p1.i173, float %j.f.i172, i32 3, i32 0, i32 %arg4) #1
927 %i.i163 = extractelement <2 x i32> %arg6, i32 0
928 %j.i164 = extractelement <2 x i32> %arg6, i32 1
929 %i.f.i165 = bitcast i32 %i.i163 to float
930 %j.f.i166 = bitcast i32 %j.i164 to float
931 %p1.i167 = call float @llvm.amdgcn.interp.p1(float %i.f.i165, i32 0, i32 1, i32 %arg4) #1
932 %p2.i168 = call float @llvm.amdgcn.interp.p2(float %p1.i167, float %j.f.i166, i32 0, i32 1, i32 %arg4) #1
933 %i.i157 = extractelement <2 x i32> %arg6, i32 0
934 %j.i158 = extractelement <2 x i32> %arg6, i32 1
935 %i.f.i159 = bitcast i32 %i.i157 to float
936 %j.f.i160 = bitcast i32 %j.i158 to float
937 %p1.i161 = call float @llvm.amdgcn.interp.p1(float %i.f.i159, i32 1, i32 1, i32 %arg4) #1
938 %p2.i162 = call float @llvm.amdgcn.interp.p2(float %p1.i161, float %j.f.i160, i32 1, i32 1, i32 %arg4) #1
939 %i.i151 = extractelement <2 x i32> %arg6, i32 0
940 %j.i152 = extractelement <2 x i32> %arg6, i32 1
941 %i.f.i153 = bitcast i32 %i.i151 to float
942 %j.f.i154 = bitcast i32 %j.i152 to float
943 %p1.i155 = call float @llvm.amdgcn.interp.p1(float %i.f.i153, i32 2, i32 1, i32 %arg4) #1
944 %p2.i156 = call float @llvm.amdgcn.interp.p2(float %p1.i155, float %j.f.i154, i32 2, i32 1, i32 %arg4) #1
945 %i.i145 = extractelement <2 x i32> %arg6, i32 0
946 %j.i146 = extractelement <2 x i32> %arg6, i32 1
947 %i.f.i147 = bitcast i32 %i.i145 to float
948 %j.f.i148 = bitcast i32 %j.i146 to float
949 %p1.i149 = call float @llvm.amdgcn.interp.p1(float %i.f.i147, i32 3, i32 1, i32 %arg4) #1
950 %p2.i150 = call float @llvm.amdgcn.interp.p2(float %p1.i149, float %j.f.i148, i32 3, i32 1, i32 %arg4) #1
951 %i.i139 = extractelement <2 x i32> %arg6, i32 0
952 %j.i140 = extractelement <2 x i32> %arg6, i32 1
953 %i.f.i141 = bitcast i32 %i.i139 to float
954 %j.f.i142 = bitcast i32 %j.i140 to float
955 %p1.i143 = call float @llvm.amdgcn.interp.p1(float %i.f.i141, i32 0, i32 2, i32 %arg4) #1
956 %p2.i144 = call float @llvm.amdgcn.interp.p2(float %p1.i143, float %j.f.i142, i32 0, i32 2, i32 %arg4) #1
957 %i.i133 = extractelement <2 x i32> %arg6, i32 0
958 %j.i134 = extractelement <2 x i32> %arg6, i32 1
959 %i.f.i135 = bitcast i32 %i.i133 to float
960 %j.f.i136 = bitcast i32 %j.i134 to float
961 %p1.i137 = call float @llvm.amdgcn.interp.p1(float %i.f.i135, i32 1, i32 2, i32 %arg4) #1
962 %p2.i138 = call float @llvm.amdgcn.interp.p2(float %p1.i137, float %j.f.i136, i32 1, i32 2, i32 %arg4) #1
963 %i.i127 = extractelement <2 x i32> %arg6, i32 0
964 %j.i128 = extractelement <2 x i32> %arg6, i32 1
965 %i.f.i129 = bitcast i32 %i.i127 to float
966 %j.f.i130 = bitcast i32 %j.i128 to float
967 %p1.i131 = call float @llvm.amdgcn.interp.p1(float %i.f.i129, i32 2, i32 2, i32 %arg4) #1
968 %p2.i132 = call float @llvm.amdgcn.interp.p2(float %p1.i131, float %j.f.i130, i32 2, i32 2, i32 %arg4) #1
969 %i.i121 = extractelement <2 x i32> %arg6, i32 0
970 %j.i122 = extractelement <2 x i32> %arg6, i32 1
971 %i.f.i123 = bitcast i32 %i.i121 to float
972 %j.f.i124 = bitcast i32 %j.i122 to float
973 %p1.i125 = call float @llvm.amdgcn.interp.p1(float %i.f.i123, i32 3, i32 2, i32 %arg4) #1
974 %p2.i126 = call float @llvm.amdgcn.interp.p2(float %p1.i125, float %j.f.i124, i32 3, i32 2, i32 %arg4) #1
975 %i.i115 = extractelement <2 x i32> %arg6, i32 0
976 %j.i116 = extractelement <2 x i32> %arg6, i32 1
977 %i.f.i117 = bitcast i32 %i.i115 to float
978 %j.f.i118 = bitcast i32 %j.i116 to float
979 %p1.i119 = call float @llvm.amdgcn.interp.p1(float %i.f.i117, i32 0, i32 3, i32 %arg4) #1
980 %p2.i120 = call float @llvm.amdgcn.interp.p2(float %p1.i119, float %j.f.i118, i32 0, i32 3, i32 %arg4) #1
981 %i.i109 = extractelement <2 x i32> %arg6, i32 0
982 %j.i110 = extractelement <2 x i32> %arg6, i32 1
983 %i.f.i111 = bitcast i32 %i.i109 to float
984 %j.f.i112 = bitcast i32 %j.i110 to float
985 %p1.i113 = call float @llvm.amdgcn.interp.p1(float %i.f.i111, i32 1, i32 3, i32 %arg4) #1
986 %p2.i114 = call float @llvm.amdgcn.interp.p2(float %p1.i113, float %j.f.i112, i32 1, i32 3, i32 %arg4) #1
987 %i.i103 = extractelement <2 x i32> %arg6, i32 0
988 %j.i104 = extractelement <2 x i32> %arg6, i32 1
989 %i.f.i105 = bitcast i32 %i.i103 to float
990 %j.f.i106 = bitcast i32 %j.i104 to float
991 %p1.i107 = call float @llvm.amdgcn.interp.p1(float %i.f.i105, i32 2, i32 3, i32 %arg4) #1
992 %p2.i108 = call float @llvm.amdgcn.interp.p2(float %p1.i107, float %j.f.i106, i32 2, i32 3, i32 %arg4) #1
993 %i.i97 = extractelement <2 x i32> %arg6, i32 0
994 %j.i98 = extractelement <2 x i32> %arg6, i32 1
995 %i.f.i99 = bitcast i32 %i.i97 to float
996 %j.f.i100 = bitcast i32 %j.i98 to float
997 %p1.i101 = call float @llvm.amdgcn.interp.p1(float %i.f.i99, i32 3, i32 3, i32 %arg4) #1
998 %p2.i102 = call float @llvm.amdgcn.interp.p2(float %p1.i101, float %j.f.i100, i32 3, i32 3, i32 %arg4) #1
999 %i.i91 = extractelement <2 x i32> %arg6, i32 0
1000 %j.i92 = extractelement <2 x i32> %arg6, i32 1
1001 %i.f.i93 = bitcast i32 %i.i91 to float
1002 %j.f.i94 = bitcast i32 %j.i92 to float
1003 %p1.i95 = call float @llvm.amdgcn.interp.p1(float %i.f.i93, i32 0, i32 4, i32 %arg4) #1
1004 %p2.i96 = call float @llvm.amdgcn.interp.p2(float %p1.i95, float %j.f.i94, i32 0, i32 4, i32 %arg4) #1
1005 %i.i85 = extractelement <2 x i32> %arg6, i32 0
1006 %j.i86 = extractelement <2 x i32> %arg6, i32 1
1007 %i.f.i87 = bitcast i32 %i.i85 to float
1008 %j.f.i88 = bitcast i32 %j.i86 to float
1009 %p1.i89 = call float @llvm.amdgcn.interp.p1(float %i.f.i87, i32 1, i32 4, i32 %arg4) #1
1010 %p2.i90 = call float @llvm.amdgcn.interp.p2(float %p1.i89, float %j.f.i88, i32 1, i32 4, i32 %arg4) #1
1011 %i.i79 = extractelement <2 x i32> %arg6, i32 0
1012 %j.i80 = extractelement <2 x i32> %arg6, i32 1
1013 %i.f.i81 = bitcast i32 %i.i79 to float
1014 %j.f.i82 = bitcast i32 %j.i80 to float
1015 %p1.i83 = call float @llvm.amdgcn.interp.p1(float %i.f.i81, i32 2, i32 4, i32 %arg4) #1
1016 %p2.i84 = call float @llvm.amdgcn.interp.p2(float %p1.i83, float %j.f.i82, i32 2, i32 4, i32 %arg4) #1
1017 %i.i73 = extractelement <2 x i32> %arg6, i32 0
1018 %j.i74 = extractelement <2 x i32> %arg6, i32 1
1019 %i.f.i75 = bitcast i32 %i.i73 to float
1020 %j.f.i76 = bitcast i32 %j.i74 to float
1021 %p1.i77 = call float @llvm.amdgcn.interp.p1(float %i.f.i75, i32 3, i32 4, i32 %arg4) #1
1022 %p2.i78 = call float @llvm.amdgcn.interp.p2(float %p1.i77, float %j.f.i76, i32 3, i32 4, i32 %arg4) #1
1023 %i.i67 = extractelement <2 x i32> %arg6, i32 0
1024 %j.i68 = extractelement <2 x i32> %arg6, i32 1
1025 %i.f.i69 = bitcast i32 %i.i67 to float
1026 %j.f.i70 = bitcast i32 %j.i68 to float
1027 %p1.i71 = call float @llvm.amdgcn.interp.p1(float %i.f.i69, i32 0, i32 5, i32 %arg4) #1
1028 %p2.i72 = call float @llvm.amdgcn.interp.p2(float %p1.i71, float %j.f.i70, i32 0, i32 5, i32 %arg4) #1
1029 %i.i61 = extractelement <2 x i32> %arg6, i32 0
1030 %j.i62 = extractelement <2 x i32> %arg6, i32 1
1031 %i.f.i63 = bitcast i32 %i.i61 to float
1032 %j.f.i64 = bitcast i32 %j.i62 to float
1033 %p1.i65 = call float @llvm.amdgcn.interp.p1(float %i.f.i63, i32 1, i32 5, i32 %arg4) #1
1034 %p2.i66 = call float @llvm.amdgcn.interp.p2(float %p1.i65, float %j.f.i64, i32 1, i32 5, i32 %arg4) #1
1035 %i.i55 = extractelement <2 x i32> %arg6, i32 0
1036 %j.i56 = extractelement <2 x i32> %arg6, i32 1
1037 %i.f.i57 = bitcast i32 %i.i55 to float
1038 %j.f.i58 = bitcast i32 %j.i56 to float
1039 %p1.i59 = call float @llvm.amdgcn.interp.p1(float %i.f.i57, i32 2, i32 5, i32 %arg4) #1
1040 %p2.i60 = call float @llvm.amdgcn.interp.p2(float %p1.i59, float %j.f.i58, i32 2, i32 5, i32 %arg4) #1
1041 %i.i49 = extractelement <2 x i32> %arg6, i32 0
1042 %j.i50 = extractelement <2 x i32> %arg6, i32 1
1043 %i.f.i51 = bitcast i32 %i.i49 to float
1044 %j.f.i52 = bitcast i32 %j.i50 to float
1045 %p1.i53 = call float @llvm.amdgcn.interp.p1(float %i.f.i51, i32 3, i32 5, i32 %arg4) #1
1046 %p2.i54 = call float @llvm.amdgcn.interp.p2(float %p1.i53, float %j.f.i52, i32 3, i32 5, i32 %arg4) #1
1047 %i.i43 = extractelement <2 x i32> %arg6, i32 0
1048 %j.i44 = extractelement <2 x i32> %arg6, i32 1
1049 %i.f.i45 = bitcast i32 %i.i43 to float
1050 %j.f.i46 = bitcast i32 %j.i44 to float
1051 %p1.i47 = call float @llvm.amdgcn.interp.p1(float %i.f.i45, i32 0, i32 6, i32 %arg4) #1
1052 %p2.i48 = call float @llvm.amdgcn.interp.p2(float %p1.i47, float %j.f.i46, i32 0, i32 6, i32 %arg4) #1
1053 %i.i37 = extractelement <2 x i32> %arg6, i32 0
1054 %j.i38 = extractelement <2 x i32> %arg6, i32 1
1055 %i.f.i39 = bitcast i32 %i.i37 to float
1056 %j.f.i40 = bitcast i32 %j.i38 to float
1057 %p1.i41 = call float @llvm.amdgcn.interp.p1(float %i.f.i39, i32 1, i32 6, i32 %arg4) #1
1058 %p2.i42 = call float @llvm.amdgcn.interp.p2(float %p1.i41, float %j.f.i40, i32 1, i32 6, i32 %arg4) #1
1059 %i.i31 = extractelement <2 x i32> %arg6, i32 0
1060 %j.i32 = extractelement <2 x i32> %arg6, i32 1
1061 %i.f.i33 = bitcast i32 %i.i31 to float
1062 %j.f.i34 = bitcast i32 %j.i32 to float
1063 %p1.i35 = call float @llvm.amdgcn.interp.p1(float %i.f.i33, i32 2, i32 6, i32 %arg4) #1
1064 %p2.i36 = call float @llvm.amdgcn.interp.p2(float %p1.i35, float %j.f.i34, i32 2, i32 6, i32 %arg4) #1
1065 %i.i25 = extractelement <2 x i32> %arg6, i32 0
1066 %j.i26 = extractelement <2 x i32> %arg6, i32 1
1067 %i.f.i27 = bitcast i32 %i.i25 to float
1068 %j.f.i28 = bitcast i32 %j.i26 to float
1069 %p1.i29 = call float @llvm.amdgcn.interp.p1(float %i.f.i27, i32 3, i32 6, i32 %arg4) #1
1070 %p2.i30 = call float @llvm.amdgcn.interp.p2(float %p1.i29, float %j.f.i28, i32 3, i32 6, i32 %arg4) #1
1071 %i.i19 = extractelement <2 x i32> %arg6, i32 0
1072 %j.i20 = extractelement <2 x i32> %arg6, i32 1
1073 %i.f.i21 = bitcast i32 %i.i19 to float
1074 %j.f.i22 = bitcast i32 %j.i20 to float
1075 %p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 0, i32 7, i32 %arg4) #1
1076 %p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 0, i32 7, i32 %arg4) #1
1077 %i.i13 = extractelement <2 x i32> %arg6, i32 0
1078 %j.i14 = extractelement <2 x i32> %arg6, i32 1
1079 %i.f.i15 = bitcast i32 %i.i13 to float
1080 %j.f.i16 = bitcast i32 %j.i14 to float
1081 %p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 1, i32 7, i32 %arg4) #1
1082 %p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 1, i32 7, i32 %arg4) #1
1083 %i.i7 = extractelement <2 x i32> %arg6, i32 0
1084 %j.i8 = extractelement <2 x i32> %arg6, i32 1
1085 %i.f.i9 = bitcast i32 %i.i7 to float
1086 %j.f.i10 = bitcast i32 %j.i8 to float
1087 %p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 2, i32 7, i32 %arg4) #1
1088 %p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 2, i32 7, i32 %arg4) #1
1089 %i.i1 = extractelement <2 x i32> %arg6, i32 0
1090 %j.i2 = extractelement <2 x i32> %arg6, i32 1
1091 %i.f.i3 = bitcast i32 %i.i1 to float
1092 %j.f.i4 = bitcast i32 %j.i2 to float
1093 %p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 3, i32 7, i32 %arg4) #1
1094 %p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 3, i32 7, i32 %arg4) #1
8511095 %tmp195 = fmul float %arg14, %tmp123
8521096 %tmp196 = fadd float %tmp195, %tmp124
8531097 %tmp197 = call float @llvm.AMDGPU.clamp.f32(float %tmp162, float 0.000000e+00, float 1.000000e+00)
8571101 %tmp201 = bitcast float %tmp197 to i32
8581102 %tmp202 = icmp ne i32 %tmp201, 0
8591103 %. = select i1 %tmp202, float -1.000000e+00, float 1.000000e+00
860 %tmp203 = fsub float -0.000000e+00, %tmp163
1104 %tmp203 = fsub float -0.000000e+00, %p2.i
8611105 %tmp204 = fadd float %tmp43, %tmp203
862 %tmp205 = fsub float -0.000000e+00, %tmp164
1106 %tmp205 = fsub float -0.000000e+00, %p2.i186
8631107 %tmp206 = fadd float %tmp44, %tmp205
864 %tmp207 = fsub float -0.000000e+00, %tmp165
1108 %tmp207 = fsub float -0.000000e+00, %p2.i180
8651109 %tmp208 = fadd float %tmp45, %tmp207
8661110 %tmp209 = fmul float %tmp204, %tmp204
8671111 %tmp210 = fmul float %tmp206, %tmp206
8751119 %tmp218 = fmul float %., %tmp53
8761120 %tmp219 = fmul float %arg13, %tmp46
8771121 %tmp220 = fmul float %tmp196, %tmp47
878 %tmp221 = bitcast float %tmp173 to i32
879 %tmp222 = bitcast float %tmp174 to i32
1122 %tmp221 = bitcast float %p2.i132 to i32
1123 %tmp222 = bitcast float %p2.i126 to i32
8801124 %tmp223 = insertelement <2 x i32> undef, i32 %tmp221, i32 0
8811125 %tmp224 = insertelement <2 x i32> %tmp223, i32 %tmp222, i32 1
8821126 %tmp132.bc = bitcast <16 x i8> %tmp132 to <4 x i32>
8941138 %result.i44 = fadd float %tmp231, %one.sub.a.i43
8951139 %one.sub.a.i41 = fsub float 1.000000e+00, %tmp26
8961140 %result.i42 = fadd float %tmp232, %one.sub.a.i41
897 %tmp233 = fmul float %tmp215, %tmp183
898 %tmp234 = fmul float %tmp216, %tmp184
1141 %tmp233 = fmul float %tmp215, %p2.i72
1142 %tmp234 = fmul float %tmp216, %p2.i66
8991143 %tmp235 = fadd float %tmp234, %tmp233
900 %tmp236 = fmul float %tmp217, %tmp185
1144 %tmp236 = fmul float %tmp217, %p2.i60
9011145 %tmp237 = fadd float %tmp235, %tmp236
902 %tmp238 = fmul float %tmp215, %tmp186
903 %tmp239 = fmul float %tmp216, %tmp187
1146 %tmp238 = fmul float %tmp215, %p2.i54
1147 %tmp239 = fmul float %tmp216, %p2.i48
9041148 %tmp240 = fadd float %tmp239, %tmp238
905 %tmp241 = fmul float %tmp217, %tmp188
1149 %tmp241 = fmul float %tmp217, %p2.i42
9061150 %tmp242 = fadd float %tmp240, %tmp241
907 %tmp243 = fmul float %tmp215, %tmp189
908 %tmp244 = fmul float %tmp216, %tmp190
1151 %tmp243 = fmul float %tmp215, %p2.i36
1152 %tmp244 = fmul float %tmp216, %p2.i30
9091153 %tmp245 = fadd float %tmp244, %tmp243
910 %tmp246 = fmul float %tmp217, %tmp191
1154 %tmp246 = fmul float %tmp217, %p2.i24
9111155 %tmp247 = fadd float %tmp245, %tmp246
9121156 %tmp248 = call float @llvm.AMDGPU.clamp.f32(float %tmp247, float 0.000000e+00, float 1.000000e+00)
9131157 %tmp249 = fmul float %tmp213, 0x3F5A36E2E0000000
9411185
9421186 LOOP: ; preds = %LOOP, %main_body
9431187 %temp144.0 = phi float [ 1.000000e+00, %main_body ], [ %tmp288, %LOOP ]
944 %temp168.0 = phi float [ %tmp175, %main_body ], [ %tmp284, %LOOP ]
945 %temp169.0 = phi float [ %tmp176, %main_body ], [ %tmp285, %LOOP ]
1188 %temp168.0 = phi float [ %p2.i120, %main_body ], [ %tmp284, %LOOP ]
1189 %temp169.0 = phi float [ %p2.i114, %main_body ], [ %tmp285, %LOOP ]
9461190 %temp170.0 = phi float [ %tmp252, %main_body ], [ %tmp286, %LOOP ]
9471191 %tmp276 = bitcast float %temp168.0 to i32
9481192 %tmp277 = bitcast float %temp169.0 to i32
9781222 %tmp303 = fadd float %tmp302, %tmp284
9791223 %tmp304 = fmul float %tmp301, %tmp274
9801224 %tmp305 = fadd float %tmp304, %tmp285
981 %tmp306 = fsub float -0.000000e+00, %tmp175
1225 %tmp306 = fsub float -0.000000e+00, %p2.i120
9821226 %tmp307 = fadd float %tmp303, %tmp306
983 %tmp308 = fsub float -0.000000e+00, %tmp176
1227 %tmp308 = fsub float -0.000000e+00, %p2.i114
9841228 %tmp309 = fadd float %tmp305, %tmp308
985 %tmp310 = fadd float %tmp175, %tmp307
986 %tmp311 = fadd float %tmp176, %tmp309
1229 %tmp310 = fadd float %p2.i120, %tmp307
1230 %tmp311 = fadd float %p2.i114, %tmp309
9871231 %tmp312 = fmul float %tmp307, %tmp66
9881232 %tmp313 = fmul float %tmp309, %tmp67
9891233 %tmp314 = fmul float %tmp312, %tmp54
9921236 %tmp317 = fadd float %tmp316, %tmp314
9931237 %tmp318 = fmul float %tmp313, %tmp57
9941238 %tmp319 = fadd float %tmp318, %tmp315
995 %tmp320 = fadd float %tmp177, %tmp317
996 %tmp321 = fadd float %tmp178, %tmp319
1239 %tmp320 = fadd float %p2.i108, %tmp317
1240 %tmp321 = fadd float %p2.i102, %tmp319
9971241 %tmp322 = fmul float %tmp312, %tmp58
9981242 %tmp323 = fmul float %tmp312, %tmp59
9991243 %tmp324 = fmul float %tmp312, %tmp60
10061250 %tmp331 = fadd float %tmp330, %tmp324
10071251 %tmp332 = fmul float %tmp313, %tmp65
10081252 %tmp333 = fadd float %tmp332, %tmp325
1009 %tmp334 = fadd float %tmp167, %tmp327
1010 %tmp335 = fadd float %tmp168, %tmp329
1011 %tmp336 = fadd float %tmp169, %tmp331
1012 %tmp337 = fadd float %tmp170, %tmp333
1253 %tmp334 = fadd float %p2.i168, %tmp327
1254 %tmp335 = fadd float %p2.i162, %tmp329
1255 %tmp336 = fadd float %p2.i156, %tmp331
1256 %tmp337 = fadd float %p2.i150, %tmp333
10131257 %tmp338 = bitcast float %tmp334 to i32
10141258 %tmp339 = bitcast float %tmp335 to i32
10151259 %tmp340 = insertelement <2 x i32> undef, i32 %tmp338, i32 0
10241268 %tmp348 = fmul float %tmp344, %tmp23
10251269 %tmp349 = fmul float %tmp345, %tmp24
10261270 %tmp350 = fmul float %tmp346, %tmp25
1027 %tmp351 = fmul float %tmp347, %tmp179
1028 %tmp352 = fmul float %tmp348, %tmp180
1029 %tmp353 = fmul float %tmp349, %tmp181
1030 %tmp354 = fmul float %tmp350, %tmp182
1271 %tmp351 = fmul float %tmp347, %p2.i96
1272 %tmp352 = fmul float %tmp348, %p2.i90
1273 %tmp353 = fmul float %tmp349, %p2.i84
1274 %tmp354 = fmul float %tmp350, %p2.i78
10311275 %tmp355 = fsub float -0.000000e+00, %tmp346
10321276 %tmp356 = fadd float 1.000000e+00, %tmp355
10331277 %tmp357 = fmul float %tmp356, %tmp48
11061350 %tmp411 = fmul float %tmp410, %tmp35
11071351 %tmp412 = fmul float %tmp409, %tmp363
11081352 %tmp413 = fmul float %tmp411, %tmp363
1109 %tmp414 = call float @fabs(float %tmp405)
1110 %tmp415 = call float @fabs(float %tmp407)
1353 %tmp414 = call float @llvm.fabs.f32(float %tmp405)
1354 %tmp415 = call float @llvm.fabs.f32(float %tmp407)
11111355 %tmp416 = fsub float -0.000000e+00, %tmp414
11121356 %tmp417 = fadd float 1.000000e+00, %tmp416
11131357 %tmp418 = fsub float -0.000000e+00, %tmp415
11271371 %tmp432 = fsub float -0.000000e+00, %tmp429
11281372 %cmp = fcmp ogt float 0.000000e+00, %tmp432
11291373 %tmp433 = select i1 %cmp, float %tmp431, float 0.000000e+00
1130 %tmp434 = fmul float %tmp183, %tmp421
1131 %tmp435 = fmul float %tmp184, %tmp421
1132 %tmp436 = fmul float %tmp185, %tmp421
1133 %tmp437 = fmul float %tmp186, %tmp423
1374 %tmp434 = fmul float %p2.i72, %tmp421
1375 %tmp435 = fmul float %p2.i66, %tmp421
1376 %tmp436 = fmul float %p2.i60, %tmp421
1377 %tmp437 = fmul float %p2.i54, %tmp423
11341378 %tmp438 = fadd float %tmp437, %tmp434
1135 %tmp439 = fmul float %tmp187, %tmp423
1379 %tmp439 = fmul float %p2.i48, %tmp423
11361380 %tmp440 = fadd float %tmp439, %tmp435
1137 %tmp441 = fmul float %tmp188, %tmp423
1381 %tmp441 = fmul float %p2.i42, %tmp423
11381382 %tmp442 = fadd float %tmp441, %tmp436
1139 %tmp443 = fmul float %tmp189, %tmp433
1383 %tmp443 = fmul float %p2.i36, %tmp433
11401384 %tmp444 = fadd float %tmp443, %tmp438
1141 %tmp445 = fmul float %tmp190, %tmp433
1385 %tmp445 = fmul float %p2.i30, %tmp433
11421386 %tmp446 = fadd float %tmp445, %tmp440
1143 %tmp447 = fmul float %tmp191, %tmp433
1387 %tmp447 = fmul float %p2.i24, %tmp433
11441388 %tmp448 = fadd float %tmp447, %tmp442
11451389 %tmp449 = fmul float %tmp444, %tmp444
11461390 %tmp450 = fmul float %tmp446, %tmp446
11861430 %tmp480 = fadd float %tmp479, %tmp40
11871431 %tmp481 = fmul float %tmp474, %tmp41
11881432 %tmp482 = fadd float %tmp481, %tmp42
1189 %tmp483 = bitcast float %tmp171 to i32
1190 %tmp484 = bitcast float %tmp172 to i32
1433 %tmp483 = bitcast float %p2.i144 to i32
1434 %tmp484 = bitcast float %p2.i138 to i32
11911435 %tmp485 = insertelement <2 x i32> undef, i32 %tmp483, i32 0
11921436 %tmp486 = insertelement <2 x i32> %tmp485, i32 %tmp484, i32 1
11931437 %tmp156.bc = bitcast <16 x i8> %tmp156 to <4 x i32>
12031447 %tmp496 = fmul float %tmp489, %tmp494
12041448 %tmp497 = fmul float %tmp490, %tmp494
12051449 %tmp498 = fmul float %tmp27, %tmp495
1206 %tmp499 = fadd float %tmp498, %tmp192
1450 %tmp499 = fadd float %tmp498, %p2.i18
12071451 %tmp500 = fmul float %tmp28, %tmp496
1208 %tmp501 = fadd float %tmp500, %tmp193
1452 %tmp501 = fadd float %tmp500, %p2.i12
12091453 %tmp502 = fmul float %tmp29, %tmp497
1210 %tmp503 = fadd float %tmp502, %tmp194
1454 %tmp503 = fadd float %tmp502, %p2.i6
12111455 %tmp504 = fmul float %tmp499, %tmp482
12121456 %tmp505 = fmul float %tmp501, %tmp482
12131457 %tmp506 = fmul float %tmp503, %tmp482
12481492 %tmp541 = fmul float %tmp538, %tmp68
12491493 %tmp542 = fmul float %tmp539, %tmp69
12501494 %tmp543 = fmul float %tmp540, %tmp70
1251 %tmp544 = fsub float -0.000000e+00, %tmp163
1495 %tmp544 = fsub float -0.000000e+00, %p2.i
12521496 %tmp545 = fadd float %tmp96, %tmp544
1253 %tmp546 = fsub float -0.000000e+00, %tmp164
1497 %tmp546 = fsub float -0.000000e+00, %p2.i186
12541498 %tmp547 = fadd float %tmp97, %tmp546
1255 %tmp548 = fsub float -0.000000e+00, %tmp165
1499 %tmp548 = fsub float -0.000000e+00, %p2.i180
12561500 %tmp549 = fadd float %tmp98, %tmp548
12571501 %tmp550 = fmul float %tmp545, %tmp545
12581502 %tmp551 = fmul float %tmp547, %tmp547
13381582 %temp69.0 = phi float [ %tmp112, %ENDIF200 ], [ %.231, %ELSE214 ], [ %tmp108, %ELSE211 ]
13391583 %temp70.0 = phi float [ %tmp113, %ENDIF200 ], [ %.232, %ELSE214 ], [ %tmp109, %ELSE211 ]
13401584 %temp71.0 = phi float [ %tmp114, %ENDIF200 ], [ %.233, %ELSE214 ], [ %tmp110, %ELSE211 ]
1341 %tmp602 = fmul float %tmp163, %tmp84
1342 %tmp603 = fmul float %tmp164, %tmp85
1585 %tmp602 = fmul float %p2.i, %tmp84
1586 %tmp603 = fmul float %p2.i186, %tmp85
13431587 %tmp604 = fadd float %tmp602, %tmp603
1344 %tmp605 = fmul float %tmp165, %tmp86
1588 %tmp605 = fmul float %p2.i180, %tmp86
13451589 %tmp606 = fadd float %tmp604, %tmp605
1346 %tmp607 = fmul float %tmp166, %tmp87
1590 %tmp607 = fmul float %p2.i174, %tmp87
13471591 %tmp608 = fadd float %tmp606, %tmp607
1348 %tmp609 = fmul float %tmp163, %tmp88
1349 %tmp610 = fmul float %tmp164, %tmp89
1592 %tmp609 = fmul float %p2.i, %tmp88
1593 %tmp610 = fmul float %p2.i186, %tmp89
13501594 %tmp611 = fadd float %tmp609, %tmp610
1351 %tmp612 = fmul float %tmp165, %tmp90
1595 %tmp612 = fmul float %p2.i180, %tmp90
13521596 %tmp613 = fadd float %tmp611, %tmp612
1353 %tmp614 = fmul float %tmp166, %tmp91
1597 %tmp614 = fmul float %p2.i174, %tmp91
13541598 %tmp615 = fadd float %tmp613, %tmp614
1355 %tmp616 = fmul float %tmp163, %tmp92
1356 %tmp617 = fmul float %tmp164, %tmp93
1599 %tmp616 = fmul float %p2.i, %tmp92
1600 %tmp617 = fmul float %p2.i186, %tmp93
13571601 %tmp618 = fadd float %tmp616, %tmp617
1358 %tmp619 = fmul float %tmp165, %tmp94
1602 %tmp619 = fmul float %p2.i180, %tmp94
13591603 %tmp620 = fadd float %tmp618, %tmp619
1360 %tmp621 = fmul float %tmp166, %tmp95
1604 %tmp621 = fmul float %p2.i174, %tmp95
13611605 %tmp622 = fadd float %tmp620, %tmp621
13621606 %tmp623 = fsub float -0.000000e+00, %tmp77
13631607 %tmp624 = fadd float 1.000000e+00, %tmp623
1364 %tmp625 = call float @fabs(float %tmp608)
1365 %tmp626 = call float @fabs(float %tmp615)
1608 %tmp625 = call float @llvm.fabs.f32(float %tmp608)
1609 %tmp626 = call float @llvm.fabs.f32(float %tmp615)
13661610 %tmp627 = fcmp oge float %tmp624, %tmp625
13671611 %tmp628 = sext i1 %tmp627 to i32
13681612 %tmp629 = bitcast i32 %tmp628 to float
15031747 %tmp747 = fadd float %tmp746, %tmp745
15041748 %tmp748 = fmul float %temp14.0, %tmp217
15051749 %tmp749 = fadd float %tmp747, %tmp748
1506 %tmp750 = call float @fabs(float %tmp749)
1750 %tmp750 = call float @llvm.fabs.f32(float %tmp749)
15071751 %tmp751 = fmul float %tmp750, %tmp750
15081752 %tmp752 = fmul float %tmp751, %tmp49
15091753 %tmp753 = fadd float %tmp752, %tmp50
15651809 br label %ENDIF209
15661810 }
15671811
1568 ; Function Attrs: readnone
1569 declare float @llvm.AMDGPU.clamp.f32(float, float, float) #1
1570
15711812 ; Function Attrs: nounwind readnone
1572 declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #2
1813 declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0
15731814
15741815 ; Function Attrs: nounwind readnone
1575 declare <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #2
1576
1577
1578 declare float @llvm.exp2.f32(float) #2
1816 declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
15791817
15801818 ; Function Attrs: nounwind readnone
1581 declare float @llvm.SI.load.const(<16 x i8>, i32) #2
1819 declare <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
15821820
15831821 ; Function Attrs: nounwind readnone
1584 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #2
1585
1586 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
1587 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
1588
1589 ; Function Attrs: nounwind readonly
1590 declare float @ceil(float) #3
1822 declare float @llvm.exp2.f32(float) #0
15911823
15921824 ; Function Attrs: nounwind readnone
1593 declare float @llvm.amdgcn.rsq.f32(float) #2
1825 declare float @llvm.SI.load.const(<16 x i8>, i32) #0
15941826
15951827 ; Function Attrs: nounwind readnone
1596 declare <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #2
1597
1598 ; Function Attrs: readnone
1599 declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #1
1600
1601 ; Function Attrs: readnone
1602 declare float @fabs(float) #1
1828 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
16031829
16041830 ; Function Attrs: nounwind readnone
1605 declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #2
1606
1831 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
16071832
16081833 ; Function Attrs: nounwind readnone
1609 declare float @llvm.pow.f32(float, float) #2
1834 declare float @llvm.ceil.f32(float) #0
16101835
16111836 ; Function Attrs: nounwind readnone
1612 declare i32 @llvm.SI.packf16(float, float) #2
1837 declare float @llvm.amdgcn.rsq.f32(float) #0
1838
1839 ; Function Attrs: nounwind readnone
1840 declare <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
1841
1842 ; Function Attrs: nounwind readnone
1843 declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0
1844
1845 ; Function Attrs: nounwind readnone
1846 declare float @llvm.fabs.f32(float) #0
1847
1848 ; Function Attrs: nounwind readnone
1849 declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
1850
1851 ; Function Attrs: nounwind readnone
1852 declare float @llvm.pow.f32(float, float) #0
1853
1854 ; Function Attrs: nounwind readnone
1855 declare i32 @llvm.SI.packf16(float, float) #0
16131856
16141857 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
16151858
1616 attributes #1 = { readnone }
1617 attributes #2 = { nounwind readnone }
1618 attributes #3 = { nounwind readonly }
1859 ; Function Attrs: nounwind readnone
1860 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #0
1861
1862 ; Function Attrs: nounwind readnone
1863 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #0
1864
1865 attributes #0 = { nounwind readnone }
1866 attributes #1 = { nounwind }
16191867
16201868 !0 = !{!1, !1, i64 0, i32 1}
16211869 !1 = !{!"const", !2}
8787 ; GCN-NOT: v_readlane_b32 m0
8888 ; GCN-NOT: s_buffer_store_dword m0
8989 ; GCN-NOT: s_buffer_load_dword m0
90 define amdgpu_ps void @spill_kill_m0_lds(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3) #0 {
90 define amdgpu_ps void @spill_kill_m0_lds(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %m0) #0 {
9191 main_body:
92 %tmp = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %arg3)
92 %tmp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %m0)
9393 %cmp = fcmp ueq float 0.000000e+00, %tmp
9494 br i1 %cmp, label %if, label %else
9595
9999 br label %endif
100100
101101 else: ; preds = %main_body
102 %interp = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %arg3)
102 %interp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %m0)
103103 br label %endif
104104
105105 endif: ; preds = %else, %if
136136 ; GCN-NOT: v_readlane_b32 m0
137137 ; GCN-NOT: s_buffer_store_dword m0
138138 ; GCN-NOT: s_buffer_load_dword m0
139 define void @m0_unavailable_spill(i32 %arg3) #0 {
139 define void @m0_unavailable_spill(i32 %m0.arg) #0 {
140140 main_body:
141141 %m0 = call i32 asm sideeffect "; def $0, 1", "={M0}"() #0
142 %tmp = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %arg3)
142 %tmp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %m0.arg)
143143 call void asm sideeffect "; clobber $0", "~{M0}"() #0
144144 %cmp = fcmp ueq float 0.000000e+00, %tmp
145145 br i1 %cmp, label %if, label %else
204204 ret void
205205 }
206206
207 declare float @llvm.SI.fs.constant(i32, i32, i32) readnone
207 declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #0
208208
209209 declare i32 @llvm.SI.packf16(float, float) readnone
210210
211211 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
212212
213213 attributes #0 = { nounwind }
214 attributes #1 = { nounwind readnone }
None ; RUN: llc -march=amdgcn < %s | FileCheck %s
1 ; REQUIRES: asserts
0 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
21 ;
32 ; This test used to crash with the following assertion:
43 ; llc: include/llvm/ADT/IntervalMap.h:632: unsigned int llvm::IntervalMapImpl::LeafNode >::insertFrom(unsigned int &, unsigned int, KeyT, KeyT, ValT) [KeyT = llvm::SlotIndex, ValT = llvm::LiveInterval *, N = 8, Traits = llvm::IntervalMapInfo]: Assertion `(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"' failed.
98 ;
109 ; Check for a valid output.
1110 ; CHECK: image_sample_c
12
13 target triple = "amdgcn--"
14
15 @ddxy_lds = external addrspace(3) global [64 x i32]
16
1711 define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([17 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg, [16 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg1, [32 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg2, [16 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg3, [16 x <4 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615) %arg4, float inreg %arg5, i32 inreg %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <3 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, <2 x i32> %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, i32 %arg20, float %arg21, i32 %arg22) #0 {
1812 main_body:
19 %tmp = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %arg6, <2 x i32> %arg8)
13 %i.i = extractelement <2 x i32> %arg8, i32 0
14 %j.i = extractelement <2 x i32> %arg8, i32 1
15 %i.f.i = bitcast i32 %i.i to float
16 %j.f.i = bitcast i32 %j.i to float
17 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 3, i32 4, i32 %arg6) #2
18 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 3, i32 4, i32 %arg6) #2
2019 %tmp23 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
2120 %tmp24 = extractelement <4 x float> %tmp23, i32 3
2221 %tmp25 = fmul float %tmp24, undef
23 %tmp26 = fmul float undef, %tmp
22 %tmp26 = fmul float undef, %p2.i
2423 %tmp27 = fadd float %tmp26, undef
2524 %tmp28 = bitcast float %tmp27 to i32
2625 %tmp29 = insertelement <4 x i32> undef, i32 %tmp28, i32 0
104103 br label %LOOP
105104 }
106105
106 ; Function Attrs: nounwind readnone
107107 declare float @llvm.AMDGPU.clamp.(float, float, float) #1
108 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
108
109 ; Function Attrs: nounwind readnone
109110 declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
111
112 ; Function Attrs: nounwind readnone
110113 declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
114
115 ; Function Attrs: nounwind readnone
111116 declare <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
117
118 ; Function Attrs: nounwind readnone
119 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
120
121 ; Function Attrs: nounwind readnone
122 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
112123
113124 attributes #0 = { "InitialPSInputAddr"="36983" "target-cpu"="tonga" }
114125 attributes #1 = { nounwind readnone }
126 attributes #2 = { nounwind }