llvm.org GIT mirror llvm / a002a91
Make InstrInfo depend only upon the Subtarget getting passed in rather than the TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213425 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 5 years ago
7 changed file(s) with 47 addition(s) and 50 deletion(s). Raw diff Collapse all Expand all
3030
3131 #define DEBUG_TYPE "mips16-instrinfo"
3232
33 Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
34 : MipsInstrInfo(tm, Mips::Bimm16),
35 RI(*tm.getSubtargetImpl()) {}
33 Mips16InstrInfo::Mips16InstrInfo(const MipsSubtarget &STI)
34 : MipsInstrInfo(STI, Mips::Bimm16), RI(STI) {}
3635
3736 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
3837 return RI;
449448 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
450449 }
451450
452 const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) {
453 return new Mips16InstrInfo(TM);
451 const MipsInstrInfo *llvm::createMips16InstrInfo(const MipsSubtarget &STI) {
452 return new Mips16InstrInfo(STI);
454453 }
455454
456455 bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg,
2222 const Mips16RegisterInfo RI;
2323
2424 public:
25 explicit Mips16InstrInfo(MipsTargetMachine &TM);
25 explicit Mips16InstrInfo(const MipsSubtarget &STI);
2626
2727 const MipsRegisterInfo &getRegisterInfo() const override;
2828
2929 // Pin the vtable to this file.
3030 void MipsInstrInfo::anchor() {}
3131
32 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr)
33 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
34 TM(tm), UncondBrOpc(UncondBr) {}
35
36 const MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) {
37 if (TM.getSubtargetImpl()->inMips16Mode())
38 return llvm::createMips16InstrInfo(TM);
39
40 return llvm::createMipsSEInstrInfo(TM);
32 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
33 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
34 Subtarget(STI), UncondBrOpc(UncondBr) {}
35
36 const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
37 if (STI.inMips16Mode())
38 return llvm::createMips16InstrInfo(STI);
39
40 return llvm::createMipsSEInstrInfo(STI);
4141 }
4242
4343 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
155155
156156 // Up to 2 branches are removed.
157157 // Note that indirect branches are not removed.
158 for(removed = 0; I != REnd && removed < 2; ++I, ++removed)
158 for (removed = 0; I != REnd && removed < 2; ++I, ++removed)
159159 if (!getAnalyzableBrOpc(I->getOpcode()))
160160 break;
161161
3232 class MipsInstrInfo : public MipsGenInstrInfo {
3333 virtual void anchor();
3434 protected:
35 MipsTargetMachine &TM;
35 const MipsSubtarget &Subtarget;
3636 unsigned UncondBrOpc;
3737
3838 public:
4545 BT_Indirect // One indirct branch.
4646 };
4747
48 explicit MipsInstrInfo(MipsTargetMachine &TM, unsigned UncondBrOpc);
48 explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
4949
50 static const MipsInstrInfo *create(MipsTargetMachine &TM);
50 static const MipsInstrInfo *create(MipsSubtarget &STI);
5151
5252 /// Branch Analysis
5353 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
139139 };
140140
141141 /// Create MipsInstrInfo objects.
142 const MipsInstrInfo *createMips16InstrInfo(MipsTargetMachine &TM);
143 const MipsInstrInfo *createMipsSEInstrInfo(MipsTargetMachine &TM);
142 const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
143 const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);
144144
145145 }
146146
2323
2424 using namespace llvm;
2525
26 MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
27 : MipsInstrInfo(tm,
28 tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
29 RI(*tm.getSubtargetImpl()),
30 IsN64(tm.getSubtarget().isABI_N64()) {}
26 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
27 : MipsInstrInfo(STI, STI.getRelocationModel() == Reloc::PIC_ ? Mips::B
28 : Mips::J),
29 RI(STI), IsN64(STI.isABI_N64()) {}
3130
3231 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
3332 return RI;
8382 unsigned DestReg, unsigned SrcReg,
8483 bool KillSrc) const {
8584 unsigned Opc = 0, ZeroReg = 0;
86 bool isMicroMips = TM.getSubtarget().inMicroMipsMode();
85 bool isMicroMips = Subtarget.inMicroMipsMode();
8786
8887 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
8988 if (Mips::GPR32RegClass.contains(SrcReg)) {
264263
265264 bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
266265 MachineBasicBlock &MBB = *MI->getParent();
267 bool isMicroMips = TM.getSubtarget().inMicroMipsMode();
266 bool isMicroMips = Subtarget.inMicroMipsMode();
268267 unsigned Opc;
269268
270269 switch(MI->getDesc().getOpcode()) {
359358 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
360359 MachineBasicBlock &MBB,
361360 MachineBasicBlock::iterator I) const {
362 const MipsSubtarget &STI = TM.getSubtarget();
361 const MipsSubtarget &STI = Subtarget;
363362 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
364363 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
365364 unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
379378 MachineBasicBlock::iterator II, DebugLoc DL,
380379 unsigned *NewImm) const {
381380 MipsAnalyzeImmediate AnalyzeImm;
382 const MipsSubtarget &STI = TM.getSubtarget();
381 const MipsSubtarget &STI = Subtarget;
383382 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
384383 unsigned Size = STI.isABI_N64() ? 64 : 32;
385384 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
428427
429428 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
430429 MachineBasicBlock::iterator I) const {
431 const auto &Subtarget = TM.getSubtarget();
432
433430 if (Subtarget.isGP64bit())
434431 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
435432 .addReg(Mips::RA_64);
511508 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
512509 MachineBasicBlock::iterator I,
513510 bool FP64) const {
514 const MipsSubtarget &Subtarget = TM.getSubtarget();
515511 unsigned DstReg = I->getOperand(0).getReg();
516512 unsigned SrcReg = I->getOperand(1).getReg();
517513 unsigned N = I->getOperand(2).getImm();
551547 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
552548 MachineBasicBlock::iterator I,
553549 bool FP64) const {
554 const MipsSubtarget &Subtarget = TM.getSubtarget();
555550 unsigned DstReg = I->getOperand(0).getReg();
556551 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
557552 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
611606 // This pseudo instruction is generated as part of the lowering of
612607 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
613608 // indirect jump to TargetReg
614 const MipsSubtarget &STI = TM.getSubtarget();
615 unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
616 unsigned SP = STI.isGP64bit() ? Mips::SP_64 : Mips::SP;
617 unsigned RA = STI.isGP64bit() ? Mips::RA_64 : Mips::RA;
618 unsigned T9 = STI.isGP64bit() ? Mips::T9_64 : Mips::T9;
619 unsigned ZERO = STI.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
609 unsigned ADDU = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
610 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
611 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
612 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
613 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
620614 unsigned OffsetReg = I->getOperand(0).getReg();
621615 unsigned TargetReg = I->getOperand(1).getReg();
622616
623617 // addu $ra, $v0, $zero
624618 // addu $sp, $sp, $v1
625619 // jr $ra (via RetRA)
620 const TargetMachine &TM = MBB.getParent()->getTarget();
626621 if (TM.getRelocationModel() == Reloc::PIC_)
627622 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
628 .addReg(TargetReg).addReg(ZERO);
623 .addReg(TargetReg)
624 .addReg(ZERO);
629625 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
630 .addReg(TargetReg).addReg(ZERO);
626 .addReg(TargetReg)
627 .addReg(ZERO);
631628 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
632 .addReg(SP).addReg(OffsetReg);
629 .addReg(SP)
630 .addReg(OffsetReg);
633631 expandRetRA(MBB, I);
634632 }
635633
636 const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
637 return new MipsSEInstrInfo(TM);
638 }
634 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
635 return new MipsSEInstrInfo(STI);
636 }
2323 bool IsN64;
2424
2525 public:
26 explicit MipsSEInstrInfo(MipsTargetMachine &TM);
26 explicit MipsSEInstrInfo(const MipsSubtarget &STI);
2727
2828 const MipsRegisterInfo &getRegisterInfo() const override;
2929
114114 HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
115115 HasMSA(false), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT),
116116 DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
117 TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*TM)),
117 TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*this)),
118118 FrameLowering(MipsFrameLowering::create(*TM, *this)),
119119 TLInfo(MipsTargetLowering::create(*TM)) {
120120
253253 FrameLoweringSE.swap(FrameLowering);
254254 TLInfoSE.swap(TLInfo);
255255 if (!InstrInfo16) {
256 InstrInfo.reset(MipsInstrInfo::create(*TM));
256 InstrInfo.reset(MipsInstrInfo::create(*this));
257257 FrameLowering.reset(MipsFrameLowering::create(*TM, *this));
258258 TLInfo.reset(MipsTargetLowering::create(*TM));
259259 } else {
271271 FrameLowering16.swap(FrameLowering);
272272 TLInfo16.swap(TLInfo);
273273 if (!InstrInfoSE) {
274 InstrInfo.reset(MipsInstrInfo::create(*TM));
274 InstrInfo.reset(MipsInstrInfo::create(*this));
275275 FrameLowering.reset(MipsFrameLowering::create(*TM, *this));
276276 TLInfo.reset(MipsTargetLowering::create(*TM));
277277 } else {