llvm.org GIT mirror llvm / 9ff542f
1. Change use of "Cache" to "Default". 2. Added argument to instruction scheduler creators so the creators can do special things. 3. Repaired target hazard code. 4. Misc. More to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29450 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Laskey 14 years ago
10 changed file(s) with 88 addition(s) and 52 deletion(s). Raw diff Collapse all Expand all
3131 (void) llvm::createLocalRegisterAllocator();
3232 (void) llvm::createLinearScanRegisterAllocator();
3333
34 (void) llvm::createBFS_DAGScheduler(NULL, NULL);
35 (void) llvm::createSimpleDAGScheduler(NULL, NULL);
36 (void) llvm::createNoItinsDAGScheduler(NULL, NULL);
37 (void) llvm::createBURRListDAGScheduler(NULL, NULL);
38 (void) llvm::createTDRRListDAGScheduler(NULL, NULL);
39 (void) llvm::createTDListDAGScheduler(NULL, NULL);
34 (void) llvm::createBFS_DAGScheduler(NULL, NULL, NULL);
35 (void) llvm::createSimpleDAGScheduler(NULL, NULL, NULL);
36 (void) llvm::createNoItinsDAGScheduler(NULL, NULL, NULL);
37 (void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL);
38 (void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL);
39 (void) llvm::createTDListDAGScheduler(NULL, NULL, NULL);
4040
4141 }
4242 } ForceCodegenLinking; // Force link by creating a global definition.
4343 }
4444
45 #endif
45 #endif
11 //
22 // The LLVM Compiler Infrastructure
33 //
4 // This file was developed by the LLVM research group and is distributed under
4 // This file was developed by the James M. Laskey and is distributed under
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the mechanics for machine function pass registries. A
10 // function pass registry (MachinePassRegistry) is auto filled by the static
11 // constructors of MachinePassRegistryNode. Further there is a command line
12 // parser (RegisterPassParser) which listens to each registry for additions
13 // and deletions, so that the appropriate command option is updated.
614 //
715 //===----------------------------------------------------------------------===//
816
1220 #include "llvm/CodeGen/Passes.h"
1321 #include "llvm/CodeGen/ScheduleDAG.h"
1422 #include "llvm/Support/CommandLine.h"
15
16 #include
1723
1824 namespace llvm {
1925
8288
8389 MachinePassRegistryNode *List;
8490 // List of registry nodes.
85 FunctionPassCtor Cache; // Cached function pass creator.
91 FunctionPassCtor Default; // Default function pass creator.
8692 MachinePassRegistryListener* Listener;// Listener for list adds are removes.
8793
8894 public:
9399 // Accessors.
94100 //
95101 MachinePassRegistryNode *getList() { return List; }
96 FunctionPassCtor getCache() { return Cache; }
97 void setCache(FunctionPassCtor C) { Cache = C; }
102 FunctionPassCtor getDefault() { return Default; }
103 void setDefault(FunctionPassCtor C) { Default = C; }
98104 void setListener(MachinePassRegistryListener *L) { Listener = L; }
99105
100106 /// Add - Adds a function pass to the registration list.
112118 for (MachinePassRegistryNode **I = &List;
113119 *I; I = (*I)->getNextAddress()) {
114120 if (*I == Node) {
115 #if 0 // FIXME: Command opt needs to call a termination routine.
116121 if (Listener) Listener->NotifyRemove(Node->getName(),
117122 Node->getDescription());
118 #endif
119123 *I = (*I)->getNext();
120124 break;
121125 }
165169 static RegisterRegAlloc *getList() {
166170 return (RegisterRegAlloc *)Registry.getList();
167171 }
168 static FunctionPassCtor getCache() {
169 return Registry.getCache();
170 }
171 static void setCache(FunctionPassCtor C) {
172 Registry.setCache(C);
172 static FunctionPassCtor getDefault() {
173 return Registry.getDefault();
174 }
175 static void setDefault(FunctionPassCtor C) {
176 Registry.setDefault(C);
173177 }
174178 static void setListener(MachinePassRegistryListener *L) {
175179 Registry.setListener(L);
199203 ///
200204 //===----------------------------------------------------------------------===//
201205
206 class SelectionDAGISel;
202207 class ScheduleDAG;
203208 class SelectionDAG;
204209 class MachineBasicBlock;
205210
206211 class RegisterScheduler : public
207 MachinePassRegistryNode {
208
209 public:
210
211 typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAG*, MachineBasicBlock*);
212 MachinePassRegistryNode<
213 ScheduleDAG *(*)(SelectionDAGISel*, SelectionDAG*, MachineBasicBlock*)> {
214
215 public:
216
217 typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, SelectionDAG*,
218 MachineBasicBlock*);
212219
213220 static MachinePassRegistry Registry;
214221
227234 static RegisterScheduler *getList() {
228235 return (RegisterScheduler *)Registry.getList();
229236 }
230 static FunctionPassCtor getCache() {
231 return Registry.getCache();
232 }
233 static void setCache(FunctionPassCtor C) {
234 Registry.setCache(C);
237 static FunctionPassCtor getDefault() {
238 return Registry.getDefault();
239 }
240 static void setDefault(FunctionPassCtor C) {
241 Registry.setDefault(C);
235242 }
236243 static void setListener(MachinePassRegistryListener *L) {
237244 Registry.setListener(L);
266273 public cl::parser {
267274 public:
268275 RegisterPassParser() {}
276 ~RegisterPassParser() { RegistryClass::setListener(NULL); }
269277
270278 void initialize(cl::Option &O) {
271279 cl::parser::initialize(O);
2525 class MachineInstr;
2626 class MRegisterInfo;
2727 class SelectionDAG;
28 class SelectionDAGISel;
2829 class SSARegMap;
2930 class TargetInstrInfo;
3031 class TargetInstrDescriptor;
222223
223224 /// createBFS_DAGScheduler - This creates a simple breadth first instruction
224225 /// scheduler.
225 ScheduleDAG *createBFS_DAGScheduler(SelectionDAG *DAG, MachineBasicBlock *BB);
226 ScheduleDAG *createBFS_DAGScheduler(SelectionDAGISel *IS,
227 SelectionDAG *DAG,
228 MachineBasicBlock *BB);
226229
227230 /// createSimpleDAGScheduler - This creates a simple two pass instruction
228231 /// scheduler using instruction itinerary.
229 ScheduleDAG* createSimpleDAGScheduler(SelectionDAG *DAG,
232 ScheduleDAG* createSimpleDAGScheduler(SelectionDAGISel *IS,
233 SelectionDAG *DAG,
230234 MachineBasicBlock *BB);
231235
232236 /// createNoItinsDAGScheduler - This creates a simple two pass instruction
233237 /// scheduler without using instruction itinerary.
234 ScheduleDAG* createNoItinsDAGScheduler(SelectionDAG *DAG,
238 ScheduleDAG* createNoItinsDAGScheduler(SelectionDAGISel *IS,
239 SelectionDAG *DAG,
235240 MachineBasicBlock *BB);
236241
237242 /// createBURRListDAGScheduler - This creates a bottom up register usage
238243 /// reduction list scheduler.
239 ScheduleDAG* createBURRListDAGScheduler(SelectionDAG *DAG,
244 ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
245 SelectionDAG *DAG,
240246 MachineBasicBlock *BB);
241247
242248 /// createTDRRListDAGScheduler - This creates a top down register usage
243249 /// reduction list scheduler.
244 ScheduleDAG* createTDRRListDAGScheduler(SelectionDAG *DAG,
250 ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
251 SelectionDAG *DAG,
245252 MachineBasicBlock *BB);
246253
247254 /// createTDListDAGScheduler - This creates a top-down list scheduler with
248255 /// a hazard recognizer.
249 ScheduleDAG* createTDListDAGScheduler(SelectionDAG *DAG,
256 ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
257 SelectionDAG *DAG,
250258 MachineBasicBlock *BB);
251259
252260 }
6565 /// CanBeFoldedBy - Returns true if the specific operand node N of U can be
6666 /// folded during instruction selection?
6767 virtual bool CanBeFoldedBy(SDNode *N, SDNode *U) { return true; }
68
69 /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
70 /// to use for this target when scheduling the DAG.
71 virtual HazardRecognizer *CreateTargetHazardRecognizer();
6872
6973 /// CaseBlock - This structure is used to communicate between SDLowering and
7074 /// SDISel for the code generation of additional basic blocks needed by multi-
None //===-- MachineInstr.cpp --------------------------------------------------===//
0 //===-- CodeGen/MachineInstr.cpp ------------------------------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
55 // the University of Illinois Open Source License. See LICENSE.TXT for details.
66 //
77 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the machine function pass registry for register allocators
10 // and instruction schedulers.
11 //
12 //===----------------------------------------------------------------------===//
813
914 #include "llvm/CodeGen/MachinePassRegistry.h"
10 #include
1115
1216 using namespace llvm;
1317
2626 }
2727
2828 FunctionPass *llvm::createRegisterAllocator() {
29 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getCache();
29 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
3030
3131 if (!Ctor) {
3232 Ctor = RegisterRegAlloc::FindCtor(RegAlloc);
3333 assert(Ctor && "No register allocator found");
3434 if (!Ctor) Ctor = RegisterRegAlloc::FirstCtor();
35 RegisterRegAlloc::setCache(Ctor);
35 RegisterRegAlloc::setDefault(Ctor);
3636 }
3737
3838 assert(Ctor && "No register allocator found");
2020 #define DEBUG_TYPE "sched"
2121 #include "llvm/CodeGen/MachinePassRegistry.h"
2222 #include "llvm/CodeGen/ScheduleDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
2324 #include "llvm/CodeGen/SSARegMap.h"
2425 #include "llvm/Target/MRegisterInfo.h"
2526 #include "llvm/Target/TargetData.h"
518519 /// createTDListDAGScheduler - This creates a top-down list scheduler with a
519520 /// new hazard recognizer. This scheduler takes ownership of the hazard
520521 /// recognizer and deletes it when done.
521 ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAG *DAG,
522 ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS,
523 SelectionDAG *DAG,
522524 MachineBasicBlock *BB) {
523525 return new ScheduleDAGList(*DAG, BB, DAG->getTarget(),
524526 new LatencyPriorityQueue(),
525 new HazardRecognizer());
526 }
527 IS->CreateTargetHazardRecognizer());
528 }
885885 // Public Constructor Functions
886886 //===----------------------------------------------------------------------===//
887887
888 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG *DAG,
888 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
889 SelectionDAG *DAG,
889890 MachineBasicBlock *BB) {
890891 return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true,
891892 new BURegReductionPriorityQueue());
892893 }
893894
894 llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAG *DAG,
895 llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
896 SelectionDAG *DAG,
895897 MachineBasicBlock *BB) {
896898 return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false,
897899 new TDRegReductionPriorityQueue());
11191119
11201120 /// createSimpleDAGScheduler - This creates a simple two pass instruction
11211121 /// scheduler using instruction itinerary.
1122 llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SelectionDAG *DAG,
1122 llvm::ScheduleDAG* llvm::createSimpleDAGScheduler(SelectionDAGISel *IS,
1123 SelectionDAG *DAG,
11231124 MachineBasicBlock *BB) {
11241125 return new ScheduleDAGSimple(false, false, *DAG, BB, DAG->getTarget());
11251126 }
11261127
11271128 /// createNoItinsDAGScheduler - This creates a simple two pass instruction
11281129 /// scheduler without using instruction itinerary.
1129 llvm::ScheduleDAG* llvm::createNoItinsDAGScheduler(SelectionDAG *DAG,
1130 llvm::ScheduleDAG* llvm::createNoItinsDAGScheduler(SelectionDAGISel *IS,
1131 SelectionDAG *DAG,
11301132 MachineBasicBlock *BB) {
11311133 return new ScheduleDAGSimple(false, true, *DAG, BB, DAG->getTarget());
11321134 }
11331135
11341136 /// createBFS_DAGScheduler - This creates a simple breadth first instruction
11351137 /// scheduler.
1136 llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAG *DAG,
1138 llvm::ScheduleDAG* llvm::createBFS_DAGScheduler(SelectionDAGISel *IS,
1139 SelectionDAG *DAG,
11371140 MachineBasicBlock *BB) {
11381141 return new ScheduleDAGSimple(true, false, *DAG, BB, DAG->getTarget());
11391142 }
6666 cl::init("default"),
6767 cl::desc("Instruction schedulers available:"));
6868
69 RegisterScheduler
69 static RegisterScheduler
7070 defaultListDAGScheduler("default", " Best scheduler for the target", NULL);
7171 } // namespace
7272
36103610 if (ViewSchedDAGs) DAG.viewGraph();
36113611
36123612 static RegisterScheduler::FunctionPassCtor Ctor =
3613 RegisterScheduler::getCache();
3613 RegisterScheduler::getDefault();
36143614
36153615 if (!Ctor) {
36163616 if (std::string("default") == std::string(ISHeuristic)) {
36283628 Ctor = RegisterScheduler::FindCtor(ISHeuristic);
36293629 }
36303630
3631 RegisterScheduler::setCache(Ctor);
3631 RegisterScheduler::setDefault(Ctor);
36323632 }
36333633
36343634 assert(Ctor && "No instruction scheduler found");
3635 ScheduleDAG *SL = Ctor(&DAG, BB);
3635 ScheduleDAG *SL = Ctor(this, &DAG, BB);
36363636 BB = SL->Run();
36373637 delete SL;
3638 }
3639
3640
3641 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
3642 return new HazardRecognizer();
36383643 }
36393644
36403645