llvm.org GIT mirror llvm / 9fdcfdd
CodeGen/LiveVariables: hoist out code in nested loops This makes runOnMachineFunction vastly more readable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216368 91177308-0d34-0410-b5e6-96231b3b80d8 Dylan Noblesmith 6 years ago
2 changed file(s) with 125 addition(s) and 110 deletion(s). Raw diff Collapse all Expand all
174174 /// register which is used in a PHI node. We map that to the BB the vreg
175175 /// is coming from.
176176 void analyzePHINodes(const MachineFunction& Fn);
177
178 void runOnInstr(MachineInstr *MI, SmallVectorImpl &Defs);
179
180 void runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs);
177181 public:
178182
179183 bool runOnMachineFunction(MachineFunction &MF) override;
496496 }
497497 }
498498
499 void LiveVariables::runOnInstr(MachineInstr *MI,
500 SmallVectorImpl &Defs) {
501 assert(!MI->isDebugValue());
502 // Process all of the operands of the instruction...
503 unsigned NumOperandsToProcess = MI->getNumOperands();
504
505 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
506 // of the uses. They will be handled in other basic blocks.
507 if (MI->isPHI())
508 NumOperandsToProcess = 1;
509
510 // Clear kill and dead markers. LV will recompute them.
511 SmallVector UseRegs;
512 SmallVector DefRegs;
513 SmallVector RegMasks;
514 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
515 MachineOperand &MO = MI->getOperand(i);
516 if (MO.isRegMask()) {
517 RegMasks.push_back(i);
518 continue;
519 }
520 if (!MO.isReg() || MO.getReg() == 0)
521 continue;
522 unsigned MOReg = MO.getReg();
523 if (MO.isUse()) {
524 MO.setIsKill(false);
525 if (MO.readsReg())
526 UseRegs.push_back(MOReg);
527 } else /*MO.isDef()*/ {
528 MO.setIsDead(false);
529 DefRegs.push_back(MOReg);
530 }
531 }
532
533 MachineBasicBlock *MBB = MI->getParent();
534 // Process all uses.
535 for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
536 unsigned MOReg = UseRegs[i];
537 if (TargetRegisterInfo::isVirtualRegister(MOReg))
538 HandleVirtRegUse(MOReg, MBB, MI);
539 else if (!MRI->isReserved(MOReg))
540 HandlePhysRegUse(MOReg, MI);
541 }
542
543 // Process all masked registers. (Call clobbers).
544 for (unsigned i = 0, e = RegMasks.size(); i != e; ++i)
545 HandleRegMask(MI->getOperand(RegMasks[i]));
546
547 // Process all defs.
548 for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
549 unsigned MOReg = DefRegs[i];
550 if (TargetRegisterInfo::isVirtualRegister(MOReg))
551 HandleVirtRegDef(MOReg, MI);
552 else if (!MRI->isReserved(MOReg))
553 HandlePhysRegDef(MOReg, MI, Defs);
554 }
555 UpdatePhysRegDefs(MI, Defs);
556 }
557
558 void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
559 // Mark live-in registers as live-in.
560 SmallVector Defs;
561 for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
562 EE = MBB->livein_end(); II != EE; ++II) {
563 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
564 "Cannot have a live-in virtual register!");
565 HandlePhysRegDef(*II, nullptr, Defs);
566 }
567
568 // Loop over all of the instructions, processing them.
569 DistanceMap.clear();
570 unsigned Dist = 0;
571 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
572 I != E; ++I) {
573 MachineInstr *MI = I;
574 if (MI->isDebugValue())
575 continue;
576 DistanceMap.insert(std::make_pair(MI, Dist++));
577
578 runOnInstr(MI, Defs);
579 }
580
581 // Handle any virtual assignments from PHI nodes which might be at the
582 // bottom of this basic block. We check all of our successor blocks to see
583 // if they have PHI nodes, and if so, we simulate an assignment at the end
584 // of the current block.
585 if (!PHIVarInfo[MBB->getNumber()].empty()) {
586 SmallVectorImpl &VarInfoVec = PHIVarInfo[MBB->getNumber()];
587
588 for (SmallVectorImpl::iterator I = VarInfoVec.begin(),
589 E = VarInfoVec.end(); I != E; ++I)
590 // Mark it alive only in the block we are representing.
591 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
592 MBB);
593 }
594
595 // MachineCSE may CSE instructions which write to non-allocatable physical
596 // registers across MBBs. Remember if any reserved register is liveout.
597 SmallSet LiveOuts;
598 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
599 SE = MBB->succ_end(); SI != SE; ++SI) {
600 MachineBasicBlock *SuccMBB = *SI;
601 if (SuccMBB->isLandingPad())
602 continue;
603 for (MachineBasicBlock::livein_iterator LI = SuccMBB->livein_begin(),
604 LE = SuccMBB->livein_end(); LI != LE; ++LI) {
605 unsigned LReg = *LI;
606 if (!TRI->isInAllocatableClass(LReg))
607 // Ignore other live-ins, e.g. those that are live into landing pads.
608 LiveOuts.insert(LReg);
609 }
610 }
611
612 // Loop over PhysRegDef / PhysRegUse, killing any registers that are
613 // available at the end of the basic block.
614 for (unsigned i = 0; i != NumRegs; ++i)
615 if ((PhysRegDef[i] || PhysRegUse[i]) && !LiveOuts.count(i))
616 HandlePhysRegDef(i, nullptr, Defs);
617 }
618
499619 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
500620 MF = &mf;
501621 MRI = &mf.getRegInfo();
525645 SmallPtrSet Visited;
526646
527647 for (MachineBasicBlock *MBB : depth_first_ext(Entry, Visited)) {
528 // Mark live-in registers as live-in.
529 SmallVector Defs;
530 for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
531 EE = MBB->livein_end(); II != EE; ++II) {
532 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
533 "Cannot have a live-in virtual register!");
534 HandlePhysRegDef(*II, nullptr, Defs);
535 }
536
537 // Loop over all of the instructions, processing them.
538 DistanceMap.clear();
539 unsigned Dist = 0;
540 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
541 I != E; ++I) {
542 MachineInstr *MI = I;
543 if (MI->isDebugValue())
544 continue;
545 DistanceMap.insert(std::make_pair(MI, Dist++));
546
547 // Process all of the operands of the instruction...
548 unsigned NumOperandsToProcess = MI->getNumOperands();
549
550 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
551 // of the uses. They will be handled in other basic blocks.
552 if (MI->isPHI())
553 NumOperandsToProcess = 1;
554
555 // Clear kill and dead markers. LV will recompute them.
556 SmallVector UseRegs;
557 SmallVector DefRegs;
558 SmallVector RegMasks;
559 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
560 MachineOperand &MO = MI->getOperand(i);
561 if (MO.isRegMask()) {
562 RegMasks.push_back(i);
563 continue;
564 }
565 if (!MO.isReg() || MO.getReg() == 0)
566 continue;
567 unsigned MOReg = MO.getReg();
568 if (MO.isUse()) {
569 MO.setIsKill(false);
570 if (MO.readsReg())
571 UseRegs.push_back(MOReg);
572 } else /*MO.isDef()*/ {
573 MO.setIsDead(false);
574 DefRegs.push_back(MOReg);
575 }
576 }
577
578 // Process all uses.
579 for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
580 unsigned MOReg = UseRegs[i];
581 if (TargetRegisterInfo::isVirtualRegister(MOReg))
582 HandleVirtRegUse(MOReg, MBB, MI);
583 else if (!MRI->isReserved(MOReg))
584 HandlePhysRegUse(MOReg, MI);
585 }
586
587 // Process all masked registers. (Call clobbers).
588 for (unsigned i = 0, e = RegMasks.size(); i != e; ++i)
589 HandleRegMask(MI->getOperand(RegMasks[i]));
590
591 // Process all defs.
592 for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
593 unsigned MOReg = DefRegs[i];
594 if (TargetRegisterInfo::isVirtualRegister(MOReg))
595 HandleVirtRegDef(MOReg, MI);
596 else if (!MRI->isReserved(MOReg))
597 HandlePhysRegDef(MOReg, MI, Defs);
598 }
599 UpdatePhysRegDefs(MI, Defs);
600 }
601
602 // Handle any virtual assignments from PHI nodes which might be at the
603 // bottom of this basic block. We check all of our successor blocks to see
604 // if they have PHI nodes, and if so, we simulate an assignment at the end
605 // of the current block.
606 if (!PHIVarInfo[MBB->getNumber()].empty()) {
607 SmallVectorImpl &VarInfoVec = PHIVarInfo[MBB->getNumber()];
608
609 for (SmallVectorImpl::iterator I = VarInfoVec.begin(),
610 E = VarInfoVec.end(); I != E; ++I)
611 // Mark it alive only in the block we are representing.
612 MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
613 MBB);
614 }
615
616 // MachineCSE may CSE instructions which write to non-allocatable physical
617 // registers across MBBs. Remember if any reserved register is liveout.
618 SmallSet LiveOuts;
619 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
620 SE = MBB->succ_end(); SI != SE; ++SI) {
621 MachineBasicBlock *SuccMBB = *SI;
622 if (SuccMBB->isLandingPad())
623 continue;
624 for (MachineBasicBlock::livein_iterator LI = SuccMBB->livein_begin(),
625 LE = SuccMBB->livein_end(); LI != LE; ++LI) {
626 unsigned LReg = *LI;
627 if (!TRI->isInAllocatableClass(LReg))
628 // Ignore other live-ins, e.g. those that are live into landing pads.
629 LiveOuts.insert(LReg);
630 }
631 }
632
633 // Loop over PhysRegDef / PhysRegUse, killing any registers that are
634 // available at the end of the basic block.
635 for (unsigned i = 0; i != NumRegs; ++i)
636 if ((PhysRegDef[i] || PhysRegUse[i]) && !LiveOuts.count(i))
637 HandlePhysRegDef(i, nullptr, Defs);
648 runOnBlock(MBB, NumRegs);
638649
639650 PhysRegDef.clear();
640651 PhysRegUse.clear();