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AMDGPU/GlobalISel: Define instruction mapping for G_OR Patch by Tom Stellard git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326489 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
3 changed file(s) with 125 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
168168 return AMDGPUInstrInfo::isUniformMMO(MMO);
169169 }
170170
171 bool AMDGPURegisterBankInfo::isSALUMapping(const MachineInstr &MI) const {
172 const MachineFunction &MF = *MI.getParent()->getParent();
173 const MachineRegisterInfo &MRI = MF.getRegInfo();
174 for (unsigned i = 0, e = MI.getNumOperands();i != e; ++i) {
175 unsigned Reg = MI.getOperand(i).getReg();
176 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
177 if (Bank && Bank->getID() != AMDGPU::SGPRRegBankID)
178 return false;
179 }
180 return true;
181 }
182
183 const RegisterBankInfo::InstructionMapping &
184 AMDGPURegisterBankInfo::getDefaultMappingSOP(const MachineInstr &MI) const {
185 const MachineFunction &MF = *MI.getParent()->getParent();
186 const MachineRegisterInfo &MRI = MF.getRegInfo();
187 SmallVector OpdsMapping(MI.getNumOperands());
188
189 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
190 unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
191 OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
192 }
193 return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
194 MI.getNumOperands());
195 }
196
197 const RegisterBankInfo::InstructionMapping &
198 AMDGPURegisterBankInfo::getDefaultMappingVOP(const MachineInstr &MI) const {
199 const MachineFunction &MF = *MI.getParent()->getParent();
200 const MachineRegisterInfo &MRI = MF.getRegInfo();
201 SmallVector OpdsMapping(MI.getNumOperands());
202 unsigned OpdIdx = 0;
203
204 unsigned Size0 = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
205 OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size0);
206
207 unsigned Reg1 = MI.getOperand(1).getReg();
208 unsigned Size1 = getSizeInBits(Reg1, MRI, *TRI);
209 unsigned Bank1 = getRegBankID(Reg1, MRI, *TRI);
210 OpdsMapping[OpdIdx++] = AMDGPU::getValueMapping(Bank1, Size1);
211
212 for (unsigned e = MI.getNumOperands(); OpdIdx != e; ++OpdIdx) {
213 unsigned Size = getSizeInBits(MI.getOperand(OpdIdx).getReg(), MRI, *TRI);
214 OpdsMapping[OpdIdx] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
215 }
216
217 return getInstructionMapping(1, 1, getOperandsMapping(OpdsMapping),
218 MI.getNumOperands());
219 }
220
171221 const RegisterBankInfo::InstructionMapping &
172222 AMDGPURegisterBankInfo::getInstrMappingForLoad(const MachineInstr &MI) const {
173223
230280 switch (MI.getOpcode()) {
231281 default:
232282 return getInvalidInstructionMapping();
283 case AMDGPU::G_OR:
284 if (isSALUMapping(MI))
285 return getDefaultMappingSOP(MI);
286 return getDefaultMappingVOP(MI);
233287 break;
234288 case AMDGPU::G_IMPLICIT_DEF: {
235289 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
4545 const TargetRegisterInfo &TRI,
4646 unsigned Default = AMDGPU::VGPRRegBankID) const;
4747
48 bool isSALUMapping(const MachineInstr &MI) const;
49 const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
50 const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
4851 public:
4952 AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI);
5053
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
3
4 ---
5 name: or_ss
6 legalized: true
7
8 body: |
9 bb.0:
10 liveins: $sgpr0, $sgpr1
11 ; CHECK-LABEL: name: or_ss
12 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
13 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
14 ; CHECK: [[OR:%[0-9]+]]:sgpr(s32) = G_OR [[COPY]], [[COPY1]]
15 %0:_(s32) = COPY $sgpr0
16 %1:_(s32) = COPY $sgpr1
17 %2:_(s32) = G_OR %0, %1
18 ...
19
20 ---
21 name: or_sv
22 legalized: true
23
24 body: |
25 bb.0:
26 liveins: $sgpr0, $vgpr0
27 ; CHECK-LABEL: name: or_sv
28 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
29 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
30 ; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[COPY]], [[COPY1]]
31 %0:_(s32) = COPY $sgpr0
32 %1:_(s32) = COPY $vgpr0
33 %2:_(s32) = G_OR %0, %1
34 ...
35
36 ---
37 name: or_vs
38 legalized: true
39
40 body: |
41 bb.0:
42 liveins: $sgpr0, $vgpr0
43 ; CHECK-LABEL: name: or_vs
44 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
45 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
46 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
47 ; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[COPY]], [[COPY2]]
48 %0:_(s32) = COPY $vgpr0
49 %1:_(s32) = COPY $sgpr0
50 %2:_(s32) = G_OR %0, %1
51 ...
52
53 ---
54 name: or_vv
55 legalized: true
56
57 body: |
58 bb.0:
59 liveins: $vgpr0, $vgpr1
60 ; CHECK-LABEL: name: or_vv
61 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
62 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
63 ; CHECK: [[OR:%[0-9]+]]:vgpr(s32) = G_OR [[COPY]], [[COPY1]]
64 %0:_(s32) = COPY $vgpr0
65 %1:_(s32) = COPY $vgpr1
66 %2:_(s32) = G_OR %0, %1
67 ...