llvm.org GIT mirror llvm / 9f6636f
Fix naming inconsistencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35163 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
6 changed file(s) with 30 addition(s) and 30 deletion(s). Raw diff Collapse all Expand all
383383 // We must materialize a zero in a reg! Returning an constant here won't
384384 // work since its node is -1 so it won't get added to the selection queue.
385385 // Explicitly issue a tMOVri8 node!
386 Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVri8, MVT::i32,
386 Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
387387 CurDAG->getTargetConstant(0, MVT::i32)), 0);
388388 return true;
389389 }
671671 // one of the above mentioned nodes. It has to be wrapped because otherwise
672672 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
673673 // be used to form addressing mode. These wrapped nodes will be selected
674 // into MOVri.
674 // into MOVi.
675675 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
676676 MVT::ValueType PtrVT = Op.getValueType();
677677 ConstantPoolSDNode *CP = cast(Op);
4949 SrcReg = MI.getOperand(1).getReg();
5050 DstReg = MI.getOperand(0).getReg();
5151 return true;
52 case ARM::MOVrr:
53 case ARM::tMOVrr:
52 case ARM::MOVr:
53 case ARM::tMOVr:
5454 assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() &&
5555 MI.getOperand(1).isRegister() &&
5656 "Invalid ARM MOV instruction");
709709 // Move Instructions.
710710 //
711711
712 def MOVrr : AI1<(ops GPR:$dst, GPR:$src),
712 def MOVr : AI1<(ops GPR:$dst, GPR:$src),
713713 "mov $dst, $src", []>;
714 def MOVrs : AI1<(ops GPR:$dst, so_reg:$src),
714 def MOVs : AI1<(ops GPR:$dst, so_reg:$src),
715715 "mov $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
716716
717717 let isReMaterializable = 1 in
718 def MOVri : AI1<(ops GPR:$dst, so_imm:$src),
718 def MOVi : AI1<(ops GPR:$dst, so_imm:$src),
719719 "mov $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
720720
721721 // These aren't really mov instructions, but we have to define them this way
727727 def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src),
728728 "movs $dst, $src, asr #1",
729729 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
730 def MOVrrx : AI1<(ops GPR:$dst, GPR:$src),
730 def MOVrx : AI1<(ops GPR:$dst, GPR:$src),
731731 "mov $dst, $src, rrx",
732732 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
733733
10691069
10701070 // Two piece so_imms.
10711071 def : ARMPat<(i32 so_imm2part:$src),
1072 (ORRri (MOVri (so_imm2part_1 imm:$src)),
1072 (ORRri (MOVi (so_imm2part_1 imm:$src)),
10731073 (so_imm2part_2 imm:$src))>;
10741074
10751075 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
379379 [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
380380
381381 let isReMaterializable = 1 in
382 def tMOVri8 : TI<(ops GPR:$dst, i32imm:$src),
382 def tMOVi8 : TI<(ops GPR:$dst, i32imm:$src),
383383 "mov $dst, $src",
384384 [(set GPR:$dst, imm0_255:$src)]>;
385385
388388
389389 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
390390 // which is MOV(3). This also supports high registers.
391 def tMOVrr : TI<(ops GPR:$dst, GPR:$src),
391 def tMOVr : TI<(ops GPR:$dst, GPR:$src),
392392 "cpy $dst, $src", []>;
393393
394394 def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
543543
544544 // Two piece imms.
545545 def : ThumbPat<(i32 thumb_immshifted:$src),
546 (tLSLri (tMOVri8 (thumb_immshifted_val imm:$src)),
546 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
547547 (thumb_immshifted_shamt imm:$src))>;
548548
549549 def : ThumbPat<(i32 imm0_255_comp:$src),
550 (tMVN (tMOVri8 (imm_comp_XFORM imm:$src)))>;
550 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
184184 if (RC == ARM::GPRRegisterClass) {
185185 MachineFunction &MF = *MBB.getParent();
186186 ARMFunctionInfo *AFI = MF.getInfo();
187 BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVrr : ARM::MOVrr),
187 BuildMI(MBB, I, TII.get(AFI->isThumbFunction() ? ARM::tMOVr : ARM::MOVr),
188188 DestReg).addReg(SrcReg);
189189 } else if (RC == ARM::SPRRegisterClass)
190190 BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
213213 MachineInstr *NewMI = NULL;
214214 switch (Opc) {
215215 default: break;
216 case ARM::MOVrr: {
216 case ARM::MOVr: {
217217 if (OpNum == 0) { // move -> store
218218 unsigned SrcReg = MI->getOperand(1).getReg();
219219 NewMI = BuildMI(TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
225225 }
226226 break;
227227 }
228 case ARM::tMOVrr: {
228 case ARM::tMOVr: {
229229 if (OpNum == 0) { // move -> store
230230 unsigned SrcReg = MI->getOperand(1).getReg();
231231 if (isPhysicalRegister(SrcReg) && !isLowRegister(SrcReg))
447447 if (DestReg == ARM::SP) {
448448 assert(BaseReg == ARM::SP && "Unexpected!");
449449 LdReg = ARM::R3;
450 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R12)
450 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R12)
451451 .addReg(ARM::R3, false, false, true);
452452 }
453453
454454 if (NumBytes <= 255 && NumBytes >= 0)
455 BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes);
455 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
456456 else if (NumBytes < 0 && NumBytes >= -255) {
457 BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), LdReg).addImm(NumBytes);
457 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), LdReg).addImm(NumBytes);
458458 BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg)
459459 .addReg(LdReg, false, false, true);
460460 } else
468468 else
469469 MIB.addReg(LdReg).addReg(BaseReg, false, false, true);
470470 if (DestReg == ARM::SP)
471 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::R3)
471 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::R3)
472472 .addReg(ARM::R12, false, false, true);
473473 }
474474
537537 BuildMI(MBB, MBBI, TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3), DestReg)
538538 .addReg(BaseReg, false, false, true).addImm(ThisVal);
539539 } else {
540 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), DestReg)
540 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), DestReg)
541541 .addReg(BaseReg, false, false, true);
542542 }
543543 BaseReg = DestReg;
626626 int Chunk = (1 << 8) - 1;
627627 int ThisVal = (Imm > Chunk) ? Chunk : Imm;
628628 Imm -= ThisVal;
629 BuildMI(MBB, MBBI, TII.get(ARM::tMOVri8), DestReg).addImm(ThisVal);
629 BuildMI(MBB, MBBI, TII.get(ARM::tMOVi8), DestReg).addImm(ThisVal);
630630 if (Imm > 0)
631631 emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII);
632632 if (isSub)
689689 Offset += MI.getOperand(i+1).getImm();
690690 if (Offset == 0) {
691691 // Turn it into a move.
692 MI.setInstrDescriptor(TII.get(ARM::MOVrr));
692 MI.setInstrDescriptor(TII.get(ARM::MOVr));
693693 MI.getOperand(i).ChangeToRegister(FrameReg, false);
694694 MI.RemoveOperand(i+1);
695695 return;
740740
741741 if (Offset == 0) {
742742 // Turn it into a move.
743 MI.setInstrDescriptor(TII.get(ARM::tMOVrr));
743 MI.setInstrDescriptor(TII.get(ARM::tMOVr));
744744 MI.getOperand(i).ChangeToRegister(FrameReg, false);
745745 MI.RemoveOperand(i+1);
746746 return;
908908 unsigned TmpReg = ARM::R3;
909909 bool UseRR = false;
910910 if (ValReg == ARM::R3) {
911 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12)
911 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
912912 .addReg(ARM::R2, false, false, true);
913913 TmpReg = ARM::R2;
914914 }
915915 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
916 BuildMI(MBB, II, TII.get(ARM::tMOVrr), ARM::R12)
916 BuildMI(MBB, II, TII.get(ARM::tMOVr), ARM::R12)
917917 .addReg(ARM::R3, false, false, true);
918918 if (Opcode == ARM::tSpill) {
919919 if (FrameReg == ARM::SP)
933933
934934 MachineBasicBlock::iterator NII = next(II);
935935 if (ValReg == ARM::R3)
936 BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R2)
936 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R2)
937937 .addReg(ARM::R12, false, false, true);
938938 if (TmpReg == ARM::R3 && AFI->isR3LiveIn())
939 BuildMI(MBB, NII, TII.get(ARM::tMOVrr), ARM::R3)
939 BuildMI(MBB, NII, TII.get(ARM::tMOVr), ARM::R3)
940940 .addReg(ARM::R12, false, false, true);
941941 } else
942942 assert(false && "Unexpected opcode!");
13901390 if (NumBytes)
13911391 emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, FramePtr, -NumBytes, TII);
13921392 else
1393 BuildMI(MBB, MBBI, TII.get(ARM::tMOVrr), ARM::SP).addReg(FramePtr);
1393 BuildMI(MBB, MBBI, TII.get(ARM::tMOVr), ARM::SP).addReg(FramePtr);
13941394 } else {
13951395 if (MBBI->getOpcode() == ARM::tBX_RET &&
13961396 &MBB.front() != MBBI &&
14151415 BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
14161416 .addImm(NumBytes);
14171417 else
1418 BuildMI(MBB, MBBI, TII.get(ARM::MOVrr), ARM::SP).addReg(FramePtr);
1418 BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr);
14191419 } else if (NumBytes) {
14201420 emitSPUpdate(MBB, MBBI, NumBytes, false, TII);
14211421 }