llvm.org GIT mirror llvm / 9f4e5a0
AMDGPU: Remove tfe bit from flat instruction definitions We don't use it and it was removed in gfx9, and the encoding bit repurposed. Additionally actually using it requires changing the output register class, which wasn't done anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302814 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
11 changed file(s) with 82 addition(s) and 173 deletion(s). Raw diff Collapse all Expand all
135135 bool SelectMUBUFIntrinsicVOffset(SDValue Offset, SDValue &SOffset,
136136 SDValue &ImmOffset, SDValue &VOffset) const;
137137
138 bool SelectFlat(SDValue Addr, SDValue &VAddr,
139 SDValue &SLC, SDValue &TFE) const;
138 bool SelectFlat(SDValue Addr, SDValue &VAddr, SDValue &SLC) const;
140139
141140 bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
142141 bool &Imm) const;
12771276
12781277 bool AMDGPUDAGToDAGISel::SelectFlat(SDValue Addr,
12791278 SDValue &VAddr,
1280 SDValue &SLC,
1281 SDValue &TFE) const {
1279 SDValue &SLC) const {
12821280 VAddr = Addr;
1283 TFE = SLC = CurDAG->getTargetConstant(0, SDLoc(), MVT::i1);
1281 SLC = CurDAG->getTargetConstant(0, SDLoc(), MVT::i1);
12841282 return true;
12851283 }
12861284
126126 .add(I.getOperand(1))
127127 .add(I.getOperand(0))
128128 .addImm(0)
129 .addImm(0)
130129 .addImm(0);
130
131131
132132 // Now that we selected an opcode, we need to constrain the register
133133 // operands to use appropriate classes.
392392 .add(I.getOperand(0))
393393 .addReg(PtrReg)
394394 .addImm(0)
395 .addImm(0)
396395 .addImm(0);
397396
398397 bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
66 //
77 //===----------------------------------------------------------------------===//
88
9 def FLATAtomic : ComplexPattern3, "SelectFlat">;
9 def FLATAtomic : ComplexPattern2, "SelectFlat">;
1010
1111 //===----------------------------------------------------------------------===//
1212 // FLAT classes
6161 bits<8> vdst;
6262 bits<1> slc;
6363 bits<1> glc;
64 bits<1> tfe;
64
65 // We don't use tfe right now, and it was removed in gfx9.
66 bits<1> tfe = 0;
6567
6668 // 15-0 is reserved.
6769 let Inst{16} = !if(ps.has_glc, glc, ps.glcValue);
7880 class FLAT_Load_Pseudo : FLAT_Pseudo<
7981 opName,
8082 (outs regClass:$vdst),
81 (ins VReg_64:$vaddr, GLC:$glc, slc:$slc, tfe:$tfe),
82 " $vdst, $vaddr$glc$slc$tfe"> {
83 (ins VReg_64:$vaddr, GLC:$glc, slc:$slc),
84 " $vdst, $vaddr$glc$slc"> {
8385 let has_data = 0;
8486 let mayLoad = 1;
8587 }
8789 class FLAT_Store_Pseudo : FLAT_Pseudo<
8890 opName,
8991 (outs),
90 (ins VReg_64:$vaddr, vdataClass:$vdata, GLC:$glc, slc:$slc, tfe:$tfe),
91 " $vaddr, $vdata$glc$slc$tfe"> {
92 (ins VReg_64:$vaddr, vdataClass:$vdata, GLC:$glc, slc:$slc),
93 " $vaddr, $vdata$glc$slc"> {
9294 let mayLoad = 0;
9395 let mayStore = 1;
9496 let has_vdst = 0;
104106
105107 def "" : FLAT_Pseudo
106108 (outs),
107 (ins VReg_64:$vaddr, data_rc:$vdata, slc:$slc, tfe:$tfe),
108 " $vaddr, $vdata$slc$tfe",
109 (ins VReg_64:$vaddr, data_rc:$vdata, slc:$slc),
110 " $vaddr, $vdata$slc",
109111 []>,
110112 AtomicNoRet {
111113 let mayLoad = 1;
118120
119121 def _RTN : FLAT_Pseudo
120122 (outs vdst_rc:$vdst),
121 (ins VReg_64:$vaddr, data_rc:$vdata, slc:$slc, tfe:$tfe),
122 " $vdst, $vaddr, $vdata glc$slc$tfe",
123 (ins VReg_64:$vaddr, data_rc:$vdata, slc:$slc),
124 " $vdst, $vaddr, $vdata glc$slc",
123125 [(set vt:$vdst,
124 (atomic (FLATAtomic i64:$vaddr, i1:$slc, i1:$tfe), data_vt:$vdata))]>,
126 (atomic (FLATAtomic i64:$vaddr, i1:$slc), data_vt:$vdata))]>,
125127 AtomicNoRet {
126128 let mayLoad = 1;
127129 let mayStore = 1;
310312 // Patterns for global loads with no offset.
311313 class FlatLoadPat : Pat <
312314 (vt (node i64:$addr)),
313 (inst $addr, 0, 0, 0)
315 (inst $addr, 0, 0)
314316 >;
315317
316318 class FlatLoadAtomicPat : Pat <
317319 (vt (node i64:$addr)),
318 (inst $addr, 1, 0, 0)
320 (inst $addr, 1, 0)
319321 >;
320322
321323 class FlatStorePat : Pat <
322324 (node vt:$data, i64:$addr),
323 (inst $addr, $data, 0, 0, 0)
325 (inst $addr, $data, 0, 0)
324326 >;
325327
326328 class FlatStoreAtomicPat : Pat <
327329 // atomic store follows atomic binop convention so the address comes
328330 // first.
329331 (node i64:$addr, vt:$data),
330 (inst $addr, $data, 1, 0, 0)
332 (inst $addr, $data, 1, 0)
331333 >;
332334
333335 class FlatAtomicPat
334336 ValueType data_vt = vt> : Pat <
335337 (vt (node i64:$addr, data_vt:$data)),
336 (inst $addr, $data, 0, 0)
338 (inst $addr, $data, 0)
337339 >;
338340
339341 let Predicates = [isCIVI] in {
1313
1414 # GCN: global_addrspace
1515 # GCN: [[PTR:%[0-9]+]] = COPY %vgpr0_vgpr1
16 # GCN: FLAT_LOAD_DWORD [[PTR]], 0, 0, 0
16 # GCN: FLAT_LOAD_DWORD [[PTR]], 0, 0
1717
1818 body: |
1919 bb.0:
1414 # GCN: global_addrspace
1515 # GCN: [[PTR:%[0-9]+]] = COPY %vgpr0_vgpr1
1616 # GCN: [[VAL:%[0-9]+]] = COPY %vgpr2
17 # GCN: FLAT_STORE_DWORD [[PTR]], [[VAL]], 0, 0, 0
17 # GCN: FLAT_STORE_DWORD [[PTR]], [[VAL]], 0, 0
1818
1919 body: |
2020 bb.0:
218218 %34 = V_MOV_B32_e32 63, implicit %exec
219219
220220 %27 = V_AND_B32_e64 %26, %24, implicit %exec
221 FLAT_STORE_DWORD %37, %27, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
221 FLAT_STORE_DWORD %37, %27, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
222222
223223 %28 = V_AND_B32_e64 %24, %26, implicit %exec
224 FLAT_STORE_DWORD %37, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
224 FLAT_STORE_DWORD %37, %28, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
225225
226226 %29 = V_AND_B32_e32 %26, %24, implicit %exec
227 FLAT_STORE_DWORD %37, %29, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
227 FLAT_STORE_DWORD %37, %29, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
228228
229229 %30 = V_AND_B32_e64 %26, %26, implicit %exec
230 FLAT_STORE_DWORD %37, %30, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
230 FLAT_STORE_DWORD %37, %30, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
231231
232232 %31 = V_AND_B32_e64 %34, %34, implicit %exec
233 FLAT_STORE_DWORD %37, %31, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
233 FLAT_STORE_DWORD %37, %31, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
234234
235235 S_ENDPGM
236236
406406 %27 = S_MOV_B32 -4
407407
408408 %11 = V_LSHLREV_B32_e64 12, %10, implicit %exec
409 FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
409 FLAT_STORE_DWORD %20, %11, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
410410
411411 %12 = V_LSHLREV_B32_e64 %7, 12, implicit %exec
412 FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
412 FLAT_STORE_DWORD %20, %12, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
413413
414414 %13 = V_LSHL_B32_e64 %7, 12, implicit %exec
415 FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
415 FLAT_STORE_DWORD %20, %13, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
416416
417417 %14 = V_LSHL_B32_e64 12, %7, implicit %exec
418 FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
418 FLAT_STORE_DWORD %20, %14, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
419419
420420 %15 = V_LSHL_B32_e64 12, %24, implicit %exec
421 FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
421 FLAT_STORE_DWORD %20, %15, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
422422
423423 %22 = V_LSHL_B32_e64 %6, 12, implicit %exec
424 FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
424 FLAT_STORE_DWORD %20, %22, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
425425
426426 %23 = V_LSHL_B32_e64 %6, 32, implicit %exec
427 FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
427 FLAT_STORE_DWORD %20, %23, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
428428
429429 %25 = V_LSHL_B32_e32 %6, %6, implicit %exec
430 FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
430 FLAT_STORE_DWORD %20, %25, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
431431
432432 %26 = V_LSHLREV_B32_e32 11, %24, implicit %exec
433 FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
433 FLAT_STORE_DWORD %20, %26, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
434434
435435 %28 = V_LSHL_B32_e32 %27, %6, implicit %exec
436 FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
436 FLAT_STORE_DWORD %20, %28, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
437437
438438 S_ENDPGM
439439
614614 %35 = V_MOV_B32_e32 2, implicit %exec
615615
616616 %11 = V_ASHRREV_I32_e64 8, %10, implicit %exec
617 FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
617 FLAT_STORE_DWORD %20, %11, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
618618
619619 %12 = V_ASHRREV_I32_e64 %8, %10, implicit %exec
620 FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
620 FLAT_STORE_DWORD %20, %12, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
621621
622622 %13 = V_ASHR_I32_e64 %7, 3, implicit %exec
623 FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
623 FLAT_STORE_DWORD %20, %13, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
624624
625625 %14 = V_ASHR_I32_e64 7, %32, implicit %exec
626 FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
626 FLAT_STORE_DWORD %20, %14, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
627627
628628 %15 = V_ASHR_I32_e64 %27, %24, implicit %exec
629 FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
629 FLAT_STORE_DWORD %20, %15, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
630630
631631 %22 = V_ASHR_I32_e64 %6, 4, implicit %exec
632 FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
632 FLAT_STORE_DWORD %20, %22, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
633633
634634 %23 = V_ASHR_I32_e64 %6, %33, implicit %exec
635 FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
635 FLAT_STORE_DWORD %20, %23, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
636636
637637 %25 = V_ASHR_I32_e32 %34, %34, implicit %exec
638 FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
638 FLAT_STORE_DWORD %20, %25, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
639639
640640 %26 = V_ASHRREV_I32_e32 11, %10, implicit %exec
641 FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
641 FLAT_STORE_DWORD %20, %26, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
642642
643643 %28 = V_ASHR_I32_e32 %27, %35, implicit %exec
644 FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
644 FLAT_STORE_DWORD %20, %28, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
645645
646646 S_ENDPGM
647647
823823 %35 = V_MOV_B32_e32 2, implicit %exec
824824
825825 %11 = V_LSHRREV_B32_e64 8, %10, implicit %exec
826 FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
826 FLAT_STORE_DWORD %20, %11, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
827827
828828 %12 = V_LSHRREV_B32_e64 %8, %10, implicit %exec
829 FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
829 FLAT_STORE_DWORD %20, %12, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
830830
831831 %13 = V_LSHR_B32_e64 %7, 3, implicit %exec
832 FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
832 FLAT_STORE_DWORD %20, %13, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
833833
834834 %14 = V_LSHR_B32_e64 7, %32, implicit %exec
835 FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
835 FLAT_STORE_DWORD %20, %14, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
836836
837837 %15 = V_LSHR_B32_e64 %27, %24, implicit %exec
838 FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
838 FLAT_STORE_DWORD %20, %15, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
839839
840840 %22 = V_LSHR_B32_e64 %6, 4, implicit %exec
841 FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
841 FLAT_STORE_DWORD %20, %22, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
842842
843843 %23 = V_LSHR_B32_e64 %6, %33, implicit %exec
844 FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
844 FLAT_STORE_DWORD %20, %23, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
845845
846846 %25 = V_LSHR_B32_e32 %34, %34, implicit %exec
847 FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
847 FLAT_STORE_DWORD %20, %25, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
848848
849849 %26 = V_LSHRREV_B32_e32 11, %10, implicit %exec
850 FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
850 FLAT_STORE_DWORD %20, %26, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
851851
852852 %28 = V_LSHR_B32_e32 %27, %35, implicit %exec
853 FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
853 FLAT_STORE_DWORD %20, %28, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out)
854854
855855 S_ENDPGM
856856
245245 S_BRANCH %bb.1
246246
247247 bb.1:
248 FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr
249 %vgpr3 = V_MOV_B32_e32 0, implicit %exec
250 FLAT_STORE_DWORDX3 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4, 0, 0, 0, implicit %exec, implicit %flat_scr
251 %vgpr3 = V_MOV_B32_e32 0, implicit %exec
252 FLAT_STORE_DWORDX4 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr
253 %vgpr3 = V_MOV_B32_e32 0, implicit %exec
254 FLAT_ATOMIC_CMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr
255 %vgpr3 = V_MOV_B32_e32 0, implicit %exec
256 FLAT_ATOMIC_FCMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr
248 FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %vgpr2_vgpr3, 0, 0, implicit %exec, implicit %flat_scr
249 %vgpr3 = V_MOV_B32_e32 0, implicit %exec
250 FLAT_STORE_DWORDX3 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4, 0, 0, implicit %exec, implicit %flat_scr
251 %vgpr3 = V_MOV_B32_e32 0, implicit %exec
252 FLAT_STORE_DWORDX4 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr
253 %vgpr3 = V_MOV_B32_e32 0, implicit %exec
254 FLAT_ATOMIC_CMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, implicit %exec, implicit %flat_scr
255 %vgpr3 = V_MOV_B32_e32 0, implicit %exec
256 FLAT_ATOMIC_FCMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, implicit %exec, implicit %flat_scr
257257 %vgpr3 = V_MOV_B32_e32 0, implicit %exec
258258 S_ENDPGM
259259
5656 %4.sub1 = COPY %3.sub0
5757 undef %5.sub0 = COPY %4.sub1
5858 %5.sub1 = COPY %4.sub0
59 FLAT_STORE_DWORDX2 %vgpr0_vgpr1, killed %5, 0, 0, 0, implicit %exec, implicit %flat_scr
59 FLAT_STORE_DWORDX2 %vgpr0_vgpr1, killed %5, 0, 0, implicit %exec, implicit %flat_scr
6060
6161 %6 = IMPLICIT_DEF
6262 undef %7.sub0_sub1 = COPY %6
6363 %7.sub2 = COPY %3.sub0
64 FLAT_STORE_DWORDX3 %vgpr0_vgpr1, killed %7, 0, 0, 0, implicit %exec, implicit %flat_scr
64 FLAT_STORE_DWORDX3 %vgpr0_vgpr1, killed %7, 0, 0, implicit %exec, implicit %flat_scr
6565
6666 %8 = IMPLICIT_DEF
6767 undef %9.sub0_sub1_sub2 = COPY %8
6868 %9.sub3 = COPY %3.sub0
69 FLAT_STORE_DWORDX4 %vgpr0_vgpr1, killed %9, 0, 0, 0, implicit %exec, implicit %flat_scr
69 FLAT_STORE_DWORDX4 %vgpr0_vgpr1, killed %9, 0, 0, implicit %exec, implicit %flat_scr
7070 ...
5050 body: |
5151 bb.0:
5252 successors: %bb.1
53 %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.global4)
54 %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16)
53 %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.global4)
54 %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16)
5555 %vgpr0 = V_MOV_B32_e32 %vgpr1, implicit %exec
5656 S_BRANCH %bb.1
5757
5858 bb.1:
5959 successors: %bb.2
60 %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr
61 %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16)
60 %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr
61 %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16)
6262 %vgpr0 = V_MOV_B32_e32 %vgpr1, implicit %exec
6363 S_BRANCH %bb.2
6464
6565 bb.2:
66 %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.flat4)
67 %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.flat16)
66 %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.flat4)
67 %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.flat16)
6868 %vgpr0 = V_MOV_B32_e32 %vgpr1, implicit %exec
6969 S_ENDPGM
7070 ...
8585 body: |
8686 bb.0:
8787 successors: %bb.1
88 %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr
88 %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr
8989
9090 bb.1:
9191 %vgpr3_vgpr4 = V_LSHLREV_B64 4, %vgpr7_vgpr8, implicit %exec
92 FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr
92 FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, implicit %exec, implicit %flat_scr
9393 S_ENDPGM
9494 ...
9595 ---
113113 body: |
114114 bb.0:
115115 successors: %bb.2
116 %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr
116 %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr
117117 S_BRANCH %bb.2
118118
119119 bb.1:
120 FLAT_STORE_DWORD %vgpr8_vgpr9, %vgpr10, 0, 0, 0, implicit %exec, implicit %flat_scr
120 FLAT_STORE_DWORD %vgpr8_vgpr9, %vgpr10, 0, 0, implicit %exec, implicit %flat_scr
121121 S_ENDPGM
122122
123123 bb.2:
124124 %vgpr3_vgpr4 = V_LSHLREV_B64 4, %vgpr7_vgpr8, implicit %exec
125 FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr
125 FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, implicit %exec, implicit %flat_scr
126126 S_ENDPGM
127127 ...
2929 // CI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
3030 // VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
3131
32 flat_load_dword v1, v[3:4] glc tfe
33 // NOSI: error:
34 // CI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01]
35 // VI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x80,0x01]
36
37 flat_load_dword v1, v[3:4] glc slc tfe
38 // NOSI: error:
39 // CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
40 // VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
41
42 flat_load_dword v1, v[3:4] slc
43 // NOSI: error:
44 // CI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x00,0x01]
45 // VI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x00,0x01]
46
47 flat_load_dword v1, v[3:4] slc tfe
48 // NOSI: error:
49 // CI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01]
50 // VI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x80,0x01]
51
52 flat_load_dword v1, v[3:4] tfe
53 // NOSI: error:
54 // CI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x80,0x01]
55 // VI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x80,0x01]
56
5732 flat_store_dword v[3:4], v1
5833 // NOSI: error:
5934 // CIVI: flat_store_dword v[3:4], v1 ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x00,0x00]
6641 // NOSI: error:
6742 // CIVI: flat_store_dword v[3:4], v1 glc slc ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x00,0x00]
6843
69 flat_store_dword v[3:4], v1 glc tfe
70 // NOSI: error:
71 // CIVI: flat_store_dword v[3:4], v1 glc tfe ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x80,0x00]
72
73 flat_store_dword v[3:4], v1 glc slc tfe
74 // NOSI: error:
75 // CIVI: flat_store_dword v[3:4], v1 glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
7644
7745 flat_store_dword v[3:4], v1 slc
7846 // NOSI: error:
7947 // CIVI: flat_store_dword v[3:4], v1 slc ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x00,0x00]
80
81 flat_store_dword v[3:4], v1 slc tfe
82 // NOSI: error:
83 // CIVI: flat_store_dword v[3:4], v1 slc tfe ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x80,0x00]
84
85 flat_store_dword v[3:4], v1 tfe
86 // NOSI: error:
87 // CIVI: flat_store_dword v[3:4], v1 tfe ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x80,0x00]
8848
8949 // FIXME: For atomic instructions, glc must be placed immediately following
9050 // the data regiser. These forms aren't currently supported:
9151 // flat_atomic_add v1, v[3:4], v5 slc glc
92 // flat_atomic_add v1, v[3:4], v5 slc glc tfe
93 // flat_atomic_add v1, v[3:4], v5 slc tfe glc
94 // flat_atomic_add v1, v[3:4], v5 tfe glc
95 // flat_atomic_add v[3:4], v5 tfe glc
96 // flat_atomic_add v1, v[3:4], v5 tfe glc slc
97 // flat_atomic_add v1, v[3:4], v5 tfe slc glc
9852
9953 flat_atomic_add v1 v[3:4], v5 glc slc
10054 // NOSI: error:
10155 // CI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x00,0x01]
10256 // VI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x00,0x01]
10357
104 flat_atomic_add v1 v[3:4], v5 glc tfe
105 // NOSI: error:
106 // CI: flat_atomic_add v1, v[3:4], v5 glc tfe ; encoding: [0x00,0x00,0xc9,0xdc,0x03,0x05,0x80,0x01]
107 // VI: flat_atomic_add v1, v[3:4], v5 glc tfe ; encoding: [0x00,0x00,0x09,0xdd,0x03,0x05,0x80,0x01]
108
109 flat_atomic_add v1 v[3:4], v5 glc slc tfe
110 // NOSI: error:
111 // CI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01]
112 // VI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x80,0x01]
113
11458 flat_atomic_add v[3:4], v5 slc
11559 // NOSI: error:
11660 // CI: flat_atomic_add v[3:4], v5 slc ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x00,0x00]
11761 // VI: flat_atomic_add v[3:4], v5 slc ; encoding: [0x00,0x00,0x0a,0xdd,0x03,0x05,0x00,0x00]
118
119 flat_atomic_add v[3:4], v5 slc tfe
120 // NOSI: error:
121 // CI: flat_atomic_add v[3:4], v5 slc tfe ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x80,0x00]
122 // VI: flat_atomic_add v[3:4], v5 slc tfe ; encoding: [0x00,0x00,0x0a,0xdd,0x03,0x05,0x80,0x00]
123
124 flat_atomic_add v[3:4], v5 tfe
125 // NOSI: error:
126 // CI: flat_atomic_add v[3:4], v5 tfe ; encoding: [0x00,0x00,0xc8,0xdc,0x03,0x05,0x80,0x00]
127 // VI: flat_atomic_add v[3:4], v5 tfe ; encoding: [0x00,0x00,0x08,0xdd,0x03,0x05,0x80,0x00]
12862
12963 //===----------------------------------------------------------------------===//
13064 // Instructions
88 # VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
99 0x00 0x00 0x53 0xdc 0x03 0x00 0x00 0x01
1010
11 # VI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x80,0x01]
12 0x00 0x00 0x51 0xdc 0x03 0x00 0x80 0x01
13
14 # VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
15 0x00 0x00 0x53 0xdc 0x03 0x00 0x80 0x01
16
1711 # VI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x00,0x01]
1812 0x00 0x00 0x52 0xdc 0x03 0x00 0x00 0x01
1913
20 # VI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x80,0x01]
21 0x00 0x00 0x52 0xdc 0x03 0x00 0x80 0x01
22
23 # VI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x80,0x01]
24 0x00 0x00 0x50 0xdc 0x03 0x00 0x80 0x01
25
2614 # VI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x00,0x01]
2715 0x00 0x00 0x0b 0xdd 0x03 0x05 0x00 0x01
2816
29 # VI: flat_atomic_add v1, v[3:4], v5 glc tfe ; encoding: [0x00,0x00,0x09,0xdd,0x03,0x05,0x80,0x01]
30 0x00 0x00 0x09 0xdd 0x03 0x05 0x80 0x01
31
32 # VI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x80,0x01]
33 0x00 0x00 0x0b 0xdd 0x03 0x05 0x80 0x01
34
3517 # VI: flat_atomic_add v[3:4], v5 slc ; encoding: [0x00,0x00,0x0a,0xdd,0x03,0x05,0x00,0x00]
3618 0x00 0x00 0x0a 0xdd 0x03 0x05 0x00 0x00
3719
38 # VI: flat_atomic_add v[3:4], v5 slc tfe ; encoding: [0x00,0x00,0x0a,0xdd,0x03,0x05,0x80,0x00]
39 0x00 0x00 0x0a 0xdd 0x03 0x05 0x80 0x00
40
41 # VI: flat_atomic_add v[3:4], v5 tfe ; encoding: [0x00,0x00,0x08,0xdd,0x03,0x05,0x80,0x00]
42 0x00 0x00 0x08 0xdd 0x03 0x05 0x80 0x00
43
4420 # VI: flat_load_ubyte v1, v[3:4] ; encoding: [0x00,0x00,0x40,0xdc,0x03,0x00,0x00,0x01]
4521 0x00 0x00 0x40 0xdc 0x03 0x00 0x00 0x01
4622