llvm.org GIT mirror llvm / 9f29d01
[X86] Fix some cppcheck "Local variable name shadows outer variable" warnings. NFCI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359976 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 1 year, 5 months ago
1 changed file(s) with 42 addition(s) and 44 deletion(s). Raw diff Collapse all Expand all
34303430 }
34313431
34323432 // Copy all forwards from physical to virtual registers.
3433 for (ForwardedRegister &F : Forwards) {
3433 for (ForwardedRegister &FR : Forwards) {
34343434 // FIXME: Can we use a less constrained schedule?
3435 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3436 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
3437 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
3435 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, FR.VReg, FR.VT);
3436 FR.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(FR.VT));
3437 Chain = DAG.getCopyToReg(Chain, dl, FR.VReg, RegVal);
34383438 }
34393439 }
34403440
1787317873 else
1787417874 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
1787517875
17876 unsigned ByteSize = SrcVT.getSizeInBits()/8;
17876 unsigned ByteSize = SrcVT.getSizeInBits() / 8;
1787717877
1787817878 FrameIndexSDNode *FI = dyn_cast(StackSlot);
17879 MachineMemOperand *MMO;
17879 MachineMemOperand *LoadMMO;
1788017880 if (FI) {
1788117881 int SSFI = FI->getIndex();
17882 MMO = DAG.getMachineFunction().getMachineMemOperand(
17882 LoadMMO = DAG.getMachineFunction().getMachineMemOperand(
1788317883 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
1788417884 MachineMemOperand::MOLoad, ByteSize, ByteSize);
1788517885 } else {
17886 MMO = cast(StackSlot)->getMemOperand();
17886 LoadMMO = cast(StackSlot)->getMemOperand();
1788717887 StackSlot = StackSlot.getOperand(1);
1788817888 }
17889 SDValue Ops[] = { Chain, StackSlot };
17890 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
17891 X86ISD::FILD, DL,
17892 Tys, Ops, SrcVT, MMO);
17889 SDValue FILDOps[] = {Chain, StackSlot};
17890 SDValue Result =
17891 DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, DL,
17892 Tys, FILDOps, SrcVT, LoadMMO);
1789317893
1789417894 if (useSSE) {
1789517895 Chain = Result.getValue(1);
1789917899 // shouldn't be necessary except that RFP cannot be live across
1790017900 // multiple blocks. When stackifier is fixed, they can be uncoupled.
1790117901 MachineFunction &MF = DAG.getMachineFunction();
17902 unsigned SSFISize = Op.getValueSizeInBits()/8;
17902 unsigned SSFISize = Op.getValueSizeInBits() / 8;
1790317903 int SSFI = MF.getFrameInfo().CreateStackObject(SSFISize, SSFISize, false);
1790417904 auto PtrVT = getPointerTy(MF.getDataLayout());
1790517905 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
1790617906 Tys = DAG.getVTList(MVT::Other);
17907 SDValue Ops[] = { Chain, Result, StackSlot, InFlag };
17908 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
17907 SDValue FSTOps[] = {Chain, Result, StackSlot, InFlag};
17908 MachineMemOperand *StoreMMO = DAG.getMachineFunction().getMachineMemOperand(
1790917909 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
1791017910 MachineMemOperand::MOStore, SSFISize, SSFISize);
1791117911
17912 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
17913 Ops, Op.getValueType(), MMO);
17912 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, FSTOps,
17913 Op.getValueType(), StoreMMO);
1791417914 Result = DAG.getLoad(
1791517915 Op.getValueType(), DL, Chain, StackSlot,
1791617916 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI));
3009730097 MachineBasicBlock *BB) const {
3009830098 DebugLoc DL = MI.getDebugLoc();
3009930099 MachineFunction *MF = BB->getParent();
30100 MachineFrameInfo &MFI = MF->getFrameInfo();
3010130100 MachineRegisterInfo *MRI = &MF->getRegInfo();
3010230101 const X86InstrInfo *TII = Subtarget.getInstrInfo();
30103 int FI = MFI.getFunctionContextIndex();
30102 int FI = MF->getFrameInfo().getFunctionContextIndex();
3010430103
3010530104 // Get a mapping of the call site numbers to all of the landing pads they're
3010630105 // associated with.
3654536544 // Use SplitOpsAndApply to handle AVX splitting.
3654636545 auto PMADDWDBuilder = [](SelectionDAG &DAG, const SDLoc &DL,
3654736546 ArrayRef Ops) {
36548 MVT VT = MVT::getVectorVT(MVT::i32, Ops[0].getValueSizeInBits() / 32);
36549 return DAG.getNode(X86ISD::VPMADDWD, DL, VT, Ops);
36547 MVT OpVT = MVT::getVectorVT(MVT::i32, Ops[0].getValueSizeInBits() / 32);
36548 return DAG.getNode(X86ISD::VPMADDWD, DL, OpVT, Ops);
3655036549 };
3655136550 return SplitOpsAndApply(DAG, Subtarget, SDLoc(N), VT,
3655236551 { DAG.getBitcast(WVT, N0), DAG.getBitcast(WVT, N1) },
3797937978 // Swap rhs with lhs to match or(setcc(eq, cmp, 0), or).
3798037979 if (RHS->getOpcode() == ISD::OR)
3798137980 std::swap(LHS, RHS);
37982 EVT VT = OR->getValueType(0);
37983 SDValue NewRHS = lowerX86CmpEqZeroToCtlzSrl(RHS, VT, DAG);
37981 NewRHS = lowerX86CmpEqZeroToCtlzSrl(RHS, VT, DAG);
3798437982 if (!NewRHS)
3798537983 return SDValue();
3798637984 Ret = DAG.getNode(ISD::OR, SDLoc(OR), VT, Ret, NewRHS);
3948939487 const SDLoc &DL) {
3949039488 assert(N->getOpcode() == ISD::TRUNCATE && "Wrong opcode");
3949139489 SDValue Src = N->getOperand(0);
39492 unsigned Opcode = Src.getOpcode();
39490 unsigned SrcOpcode = Src.getOpcode();
3949339491 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3949439492
3949539493 EVT VT = N->getValueType(0);
3951739515 auto TruncateArithmetic = [&](SDValue N0, SDValue N1) {
3951839516 SDValue Trunc0 = DAG.getNode(ISD::TRUNCATE, DL, VT, N0);
3951939517 SDValue Trunc1 = DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
39520 return DAG.getNode(Opcode, DL, VT, Trunc0, Trunc1);
39518 return DAG.getNode(SrcOpcode, DL, VT, Trunc0, Trunc1);
3952139519 };
3952239520
3952339521 // Don't combine if the operation has other uses.
3953239530 // In most cases its only worth pre-truncating if we're only facing the cost
3953339531 // of one truncation.
3953439532 // i.e. if one of the inputs will constant fold or the input is repeated.
39535 switch (Opcode) {
39533 switch (SrcOpcode) {
3953639534 case ISD::AND:
3953739535 case ISD::XOR:
3953839536 case ISD::OR: {
3953939537 SDValue Op0 = Src.getOperand(0);
3954039538 SDValue Op1 = Src.getOperand(1);
39541 if (TLI.isOperationLegalOrPromote(Opcode, VT) &&
39539 if (TLI.isOperationLegalOrPromote(SrcOpcode, VT) &&
3954239540 (Op0 == Op1 || IsFreeTruncation(Op0) || IsFreeTruncation(Op1)))
3954339541 return TruncateArithmetic(Op0, Op1);
3954439542 break;
3954739545 case ISD::MUL:
3954839546 // X86 is rubbish at scalar and vector i64 multiplies (until AVX512DQ) - its
3954939547 // better to truncate if we have the chance.
39550 if (SrcVT.getScalarType() == MVT::i64 && TLI.isOperationLegal(Opcode, VT) &&
39551 !TLI.isOperationLegal(Opcode, SrcVT))
39548 if (SrcVT.getScalarType() == MVT::i64 &&
39549 TLI.isOperationLegal(SrcOpcode, VT) &&
39550 !TLI.isOperationLegal(SrcOpcode, SrcVT))
3955239551 return TruncateArithmetic(Src.getOperand(0), Src.getOperand(1));
3955339552 LLVM_FALLTHROUGH;
3955439553 case ISD::ADD: {
3955539554 SDValue Op0 = Src.getOperand(0);
3955639555 SDValue Op1 = Src.getOperand(1);
39557 if (TLI.isOperationLegal(Opcode, VT) &&
39556 if (TLI.isOperationLegal(SrcOpcode, VT) &&
3955839557 (Op0 == Op1 || IsFreeTruncation(Op0) || IsFreeTruncation(Op1)))
3955939558 return TruncateArithmetic(Op0, Op1);
3956039559 break;
3956439563 // truncatable to avoid interfering with combineSubToSubus.
3956539564 SDValue Op0 = Src.getOperand(0);
3956639565 SDValue Op1 = Src.getOperand(1);
39567 if (TLI.isOperationLegal(Opcode, VT) &&
39566 if (TLI.isOperationLegal(SrcOpcode, VT) &&
3956839567 (Op0 == Op1 || (IsFreeTruncation(Op0) && IsFreeTruncation(Op1))))
3956939568 return TruncateArithmetic(Op0, Op1);
3957039569 break;
4077440773 SDLoc DL(N);
4077540774
4077640775 auto ExtendVecSize = [&DAG](const SDLoc &DL, SDValue N, unsigned Size) {
40777 EVT InVT = N.getValueType();
40778 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
40779 Size / InVT.getScalarSizeInBits());
40780 SmallVector Opnds(Size / InVT.getSizeInBits(),
40781 DAG.getUNDEF(InVT));
40776 EVT SrcVT = N.getValueType();
40777 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getScalarType(),
40778 Size / SrcVT.getScalarSizeInBits());
40779 SmallVector Opnds(Size / SrcVT.getSizeInBits(),
40780 DAG.getUNDEF(SrcVT));
4078240781 Opnds[0] = N;
40783 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
40782 return DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Opnds);
4078440783 };
4078540784
4078640785 // If target-size is less than 128-bits, extend to a type that would extend
4163741636 if ((Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) &&
4163841637 Op.hasOneUse() && isa(Op.getOperand(1)) &&
4163941638 onlyZeroFlagUsed(SDValue(N, 0))) {
41640 EVT VT = Op.getValueType();
4164141639 unsigned BitWidth = VT.getSizeInBits();
4164241640 const APInt &ShAmt = Op.getConstantOperandAPInt(1);
4164341641 if (ShAmt.ult(BitWidth)) { // Avoid undefined shifts.
4198841986 // Madd vector size is half of the original vector size
4198941987 auto PMADDWDBuilder = [](SelectionDAG &DAG, const SDLoc &DL,
4199041988 ArrayRef Ops) {
41991 MVT VT = MVT::getVectorVT(MVT::i32, Ops[0].getValueSizeInBits() / 32);
41992 return DAG.getNode(X86ISD::VPMADDWD, DL, VT, Ops);
41989 MVT OpVT = MVT::getVectorVT(MVT::i32, Ops[0].getValueSizeInBits() / 32);
41990 return DAG.getNode(X86ISD::VPMADDWD, DL, OpVT, Ops);
4199341991 };
4199441992
4199541993 auto BuildPMADDWD = [&](SDValue Mul) {
4233742335 ArrayRef Ops) {
4233842336 // Shrink by adding truncate nodes and let DAGCombine fold with the
4233942337 // sources.
42340 EVT InVT = Ops[0].getValueType();
42341 assert(InVT.getScalarType() == MVT::i16 &&
42338 EVT OpVT = Ops[0].getValueType();
42339 assert(OpVT.getScalarType() == MVT::i16 &&
4234242340 "Unexpected scalar element type");
42343 assert(InVT == Ops[1].getValueType() && "Operands' types mismatch");
42341 assert(OpVT == Ops[1].getValueType() && "Operands' types mismatch");
4234442342 EVT ResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
42345 InVT.getVectorNumElements() / 2);
42343 OpVT.getVectorNumElements() / 2);
4234642344 return DAG.getNode(X86ISD::VPMADDWD, DL, ResVT, Ops[0], Ops[1]);
4234742345 };
4234842346 return SplitOpsAndApply(DAG, Subtarget, DL, VT, { In0, In1 },