llvm.org GIT mirror llvm / 9f1c831
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53097 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
16 changed file(s) with 239 addition(s) and 274 deletion(s). Raw diff Collapse all Expand all
5151 /// non-phi instructions that are the last users of the value.
5252 ///
5353 /// In the common case where a value is defined and killed in the same block,
54 /// DefInst is the defining inst, there is one killing instruction, and
55 /// AliveBlocks is empty.
54 /// There is one killing instruction, and AliveBlocks is empty.
5655 ///
5756 /// Otherwise, the value is live out of the block. If the value is live
5857 /// across any blocks, these blocks are listed in AliveBlocks. Blocks where
6766 /// but does include the predecessor block in the AliveBlocks set (unless that
6867 /// block also defines the value). This leads to the (perfectly sensical)
6968 /// situation where a value is defined in a block, and the last use is a phi
70 /// node in the successor. In this case, DefInst will be the defining
71 /// instruction, AliveBlocks is empty (the value is not live across any
72 /// blocks) and Kills is empty (phi nodes are not included). This is sensical
73 /// because the value must be live to the end of the block, but is not live in
74 /// any successor blocks.
69 /// node in the successor. In this case, AliveBlocks is empty (the value is
70 /// not live across any blocks) and Kills is empty (phi nodes are not
71 /// included). This is sensical because the value must be live to the end of
72 /// the block, but is not live in any successor blocks.
7573 struct VarInfo {
76 /// DefInst - The machine instruction that defines this register.
77 ///
78 MachineInstr *DefInst;
79
8074 /// AliveBlocks - Set of blocks of which this value is alive completely
8175 /// through. This is a bit set which uses the basic block number as an
8276 /// index.
9690 ///
9791 std::vector Kills;
9892
99 VarInfo() : DefInst(0), NumUses(0) {}
93 VarInfo() : NumUses(0) {}
10094
10195 /// removeKill - Delete a kill corresponding to the specified
10296 /// machine instruction. Returns true if there was a kill
182176 //===--------------------------------------------------------------------===//
183177 // API to update live variable information
184178
185 /// instructionChanged - When the address of an instruction changes, this
186 /// method should be called so that live variables can update its internal
187 /// data structures. This removes the records for OldMI, transfering them to
188 /// the records for NewMI.
189 void instructionChanged(MachineInstr *OldMI, MachineInstr *NewMI);
190
191179 /// replaceKillInstruction - Update register kill info by replacing a kill
192180 /// instruction with a new one.
193181 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
203191 getVarInfo(IncomingReg).Kills.push_back(MI);
204192 }
205193
206 /// removeVirtualRegisterKilled - Remove the specified virtual
194 /// removeVirtualRegisterKilled - Remove the specified kill of the virtual
207195 /// register from the live variable information. Returns true if the
208196 /// variable was marked as killed by the specified instruction,
209197 /// false otherwise.
210 bool removeVirtualRegisterKilled(unsigned reg,
211 MachineBasicBlock *MBB,
212 MachineInstr *MI) {
198 bool removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) {
213199 if (!getVarInfo(reg).removeKill(MI))
214200 return false;
215201
237223 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
238224 bool AddIfNotFound = false) {
239225 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
240 getVarInfo(IncomingReg).Kills.push_back(MI);
241 }
242
243 /// removeVirtualRegisterDead - Remove the specified virtual
226 getVarInfo(IncomingReg).Kills.push_back(MI);
227 }
228
229 /// removeVirtualRegisterDead - Remove the specified kill of the virtual
244230 /// register from the live variable information. Returns true if the
245231 /// variable was marked dead at the specified instruction, false
246232 /// otherwise.
247 bool removeVirtualRegisterDead(unsigned reg,
248 MachineBasicBlock *MBB,
249 MachineInstr *MI) {
233 bool removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) {
250234 if (!getVarInfo(reg).removeKill(MI))
251235 return false;
252236
263247 return true;
264248 }
265249
266 /// removeVirtualRegistersDead - Remove all of the dead registers for the
267 /// specified instruction from the live variable information.
268 void removeVirtualRegistersDead(MachineInstr *MI);
269
270250 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
271251 AU.setPreservesAll();
272252 }
233233 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
234234 bool AddIfNotFound = false);
235235
236 /// copyKillDeadInfo - Copies killed/dead information from one instr to another
237 void copyKillDeadInfo(MachineInstr *OldMI,
238 const TargetRegisterInfo *RegInfo);
239
240 /// isSafeToMove - Return true if it is safe to this instruction. If SawStore
241 /// true, it means there is a store (or call) between the instruction the
242 /// localtion and its intended destination.
236 /// isSafeToMove - Return true if it is safe to move this instruction. If
237 /// SawStore is set to true, it means that there is a store (or call) between
238 /// the instruction's location and its intended destination.
243239 bool isSafeToMove(const TargetInstrInfo *TII, bool &SawStore);
244240
245241 //
883883
884884 // Attempt to fold the memory reference into the instruction. If
885885 // we can do this, we don't need to insert spill code.
886 if (lv_)
887 lv_->instructionChanged(MI, fmi);
888 else
889 fmi->copyKillDeadInfo(MI, tri_);
890886 MachineBasicBlock &MBB = *MI->getParent();
891887 if (isSS && !mf_->getFrameInfo()->isImmutableObjectIndex(Slot))
892888 vrm.virtFolded(Reg, MI, fmi, (VirtRegMap::ModRef)MRInfo);
14631459 addIntervalsForSpills(const LiveInterval &li,
14641460 const MachineLoopInfo *loopInfo, VirtRegMap &vrm,
14651461 float &SSWeight) {
1466 // Since this is called after the analysis is done we don't know if
1467 // LiveVariables is available
1468 lv_ = getAnalysisToUpdate();
1469
14701462 assert(li.weight != HUGE_VALF &&
14711463 "attempt to spill already spilled interval!");
14721464
652652 return false;
653653 }
654654
655 /// instructionChanged - When the address of an instruction changes, this method
656 /// should be called so that live variables can update its internal data
657 /// structures. This removes the records for OldMI, transfering them to the
658 /// records for NewMI.
659 void LiveVariables::instructionChanged(MachineInstr *OldMI,
660 MachineInstr *NewMI) {
661 // If the instruction defines any virtual registers, update the VarInfo,
662 // kill and dead information for the instruction.
663 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
664 MachineOperand &MO = OldMI->getOperand(i);
665 if (MO.isRegister() && MO.getReg() &&
666 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
667 unsigned Reg = MO.getReg();
668 VarInfo &VI = getVarInfo(Reg);
669 if (MO.isDef()) {
670 if (MO.isDead()) {
671 MO.setIsDead(false);
672 addVirtualRegisterDead(Reg, NewMI);
673 }
674 }
675 if (MO.isKill()) {
676 MO.setIsKill(false);
677 addVirtualRegisterKilled(Reg, NewMI);
678 }
679 // If this is a kill of the value, update the VI kills list.
680 if (VI.removeKill(OldMI))
681 VI.Kills.push_back(NewMI); // Yes, there was a kill of it
682 }
683 }
684 }
685
686655 /// replaceKillInstruction - Update register kill info by replacing a kill
687656 /// instruction with a new one.
688657 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
698667 MachineOperand &MO = MI->getOperand(i);
699668 if (MO.isRegister() && MO.isKill()) {
700669 MO.setIsKill(false);
701 unsigned Reg = MO.getReg();
702 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
703 bool removed = getVarInfo(Reg).removeKill(MI);
704 assert(removed && "kill not in register's VarInfo?");
705 }
706 }
707 }
708 }
709
710 /// removeVirtualRegistersDead - Remove all of the dead registers for the
711 /// specified instruction from the live variable information.
712 void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
713 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
714 MachineOperand &MO = MI->getOperand(i);
715 if (MO.isRegister() && MO.isDead()) {
716 MO.setIsDead(false);
717670 unsigned Reg = MO.getReg();
718671 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
719672 bool removed = getVarInfo(Reg).removeKill(MI);
646646 }
647647 }
648648
649 /// isSafeToMove - Return true if it is safe to this instruction. If SawStore is
650 /// set to true, it means that there is a store (or call) between the
651 /// instruction's location and its intended destination.
649 /// isSafeToMove - Return true if it is safe to move this instruction. If
650 /// SawStore is set to true, it means that there is a store (or call) between
651 /// the instruction's location and its intended destination.
652652 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
653653 // Ignore stuff that we obviously can't move.
654654 if (TID->mayStore() || TID->isCall()) {
828828 }
829829 return false;
830830 }
831
832 /// copyKillDeadInfo - copies killed/dead information from one instr to another
833 void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
834 const TargetRegisterInfo *RegInfo) {
835 // If the instruction defines any virtual registers, update the VarInfo,
836 // kill and dead information for the instruction.
837 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
838 MachineOperand &MO = OldMI->getOperand(i);
839 if (MO.isRegister() && MO.getReg() &&
840 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
841 unsigned Reg = MO.getReg();
842 if (MO.isDef()) {
843 if (MO.isDead()) {
844 MO.setIsDead(false);
845 addRegisterDead(Reg, RegInfo);
846 }
847 }
848 if (MO.isKill()) {
849 MO.setIsKill(false);
850 addRegisterKilled(Reg, RegInfo);
851 }
852 }
853 }
854 }
151151
152152 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2;
153153 unsigned DestReg = MPhi->getOperand(0).getReg();
154 bool isDead = MPhi->getOperand(0).isDead();
154155
155156 // Create a new register for the incoming PHI arguments.
156157 MachineFunction &MF = *MBB.getParent();
157158 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
158 unsigned IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
159 unsigned IncomingReg = 0;
159160
160161 // Insert a register to register copy at the top of the current block (but
161162 // after any remaining phi nodes) which copies the new incoming register
162163 // into the phi node destination.
163164 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
164165 if (isSourceDefinedByImplicitDef(MPhi, MRI))
165 // If all sources of a PHI node are implicit_def, just emit an implicit_def
166 // instead of a copy.
167 BuildMI(MBB, AfterPHIsIt, TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg);
168 else
166 // If all sources of a PHI node are implicit_def, just emit an
167 // implicit_def instead of a copy.
168 BuildMI(MBB, AfterPHIsIt,
169 TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg);
170 else {
171 IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
169172 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
173 }
170174
171175 // Update live variable information if there is any.
172176 LiveVariables *LV = getAnalysisToUpdate();
173177 if (LV) {
174178 MachineInstr *PHICopy = prior(AfterPHIsIt);
175179
176 // Increment use count of the newly created virtual register.
177 LV->getVarInfo(IncomingReg).NumUses++;
178
179 // Add information to LiveVariables to know that the incoming value is
180 // killed. Note that because the value is defined in several places (once
181 // each for each incoming block), the "def" block and instruction fields for
182 // the VarInfo is not filled in.
183 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
180 if (IncomingReg) {
181 // Increment use count of the newly created virtual register.
182 LV->getVarInfo(IncomingReg).NumUses++;
183
184 // Add information to LiveVariables to know that the incoming value is
185 // killed. Note that because the value is defined in several places (once
186 // each for each incoming block), the "def" block and instruction fields
187 // for the VarInfo is not filled in.
188 LV->addVirtualRegisterKilled(IncomingReg, PHICopy);
189
190 LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true;
191 }
184192
185193 // Since we are going to be deleting the PHI node, if it is the last use of
186194 // any registers, or if the value itself is dead, we need to move this
188196 LV->removeVirtualRegistersKilled(MPhi);
189197
190198 // If the result is dead, update LV.
191 if (MPhi->registerDefIsDead(DestReg)) {
199 if (isDead) {
192200 LV->addVirtualRegisterDead(DestReg, PHICopy);
193 LV->removeVirtualRegistersDead(MPhi);
194 }
195
196 LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true;
201 LV->removeVirtualRegisterDead(DestReg, MPhi);
202 }
197203 }
198204
199205 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node.
210216 "Machine PHI Operands must all be virtual registers!");
211217
212218 // If source is defined by an implicit def, there is no need to insert a
213 // copy unless it's the only source.
219 // copy.
214220 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
215221 if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
216222 ImpDefs.insert(DefMI);
183183 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
184184 KillMO->setIsKill(true);
185185
186 if (LV) {
187 LiveVariables::VarInfo& VarInfo = LV->getVarInfo(SavedReg);
188 VarInfo.removeKill(KillMI);
189 VarInfo.Kills.push_back(MI);
190 }
186 if (LV)
187 LV->replaceKillInstruction(SavedReg, KillMI, MI);
191188
192189 // Move instruction to its destination.
193190 MBB->remove(MI);
453450 // regB is used in this BB.
454451 varInfoB.UsedBlocks[mbbi->getNumber()] = true;
455452
456 if (LV->removeVirtualRegisterKilled(regB, mbbi, mi))
453 if (LV->removeVirtualRegisterKilled(regB, mi))
457454 LV->addVirtualRegisterKilled(regB, prevMi);
458455
459 if (LV->removeVirtualRegisterDead(regB, mbbi, mi))
456 if (LV->removeVirtualRegisterDead(regB, mi))
460457 LV->addVirtualRegisterDead(regB, prevMi);
461458 }
462459
676676 unsigned PredReg = MI->getOperand(3).getReg();
677677 if (OpNum == 0) { // move -> store
678678 unsigned SrcReg = MI->getOperand(1).getReg();
679 NewMI = BuildMI(get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
680 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
679 bool isKill = MI->getOperand(1).isKill();
680 NewMI = BuildMI(get(ARM::STR)).addReg(SrcReg, false, false, isKill)
681 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
681682 } else { // move -> load
682683 unsigned DstReg = MI->getOperand(0).getReg();
683 NewMI = BuildMI(get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
684 .addImm(0).addImm(Pred).addReg(PredReg);
684 bool isDead = MI->getOperand(0).isDead();
685 NewMI = BuildMI(get(ARM::LDR)).addReg(DstReg, true, false, false, isDead)
686 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
685687 }
686688 break;
687689 }
688690 case ARM::tMOVr: {
689691 if (OpNum == 0) { // move -> store
690692 unsigned SrcReg = MI->getOperand(1).getReg();
693 bool isKill = MI->getOperand(1).isKill();
691694 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
692695 // tSpill cannot take a high register operand.
693696 break;
694 NewMI = BuildMI(get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
695 .addImm(0);
697 NewMI = BuildMI(get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
698 .addFrameIndex(FI).addImm(0);
696699 } else { // move -> load
697700 unsigned DstReg = MI->getOperand(0).getReg();
698701 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
699702 // tRestore cannot target a high register operand.
700703 break;
701 NewMI = BuildMI(get(ARM::tRestore), DstReg).addFrameIndex(FI)
702 .addImm(0);
704 bool isDead = MI->getOperand(0).isDead();
705 NewMI = BuildMI(get(ARM::tRestore))
706 .addReg(DstReg, true, false, false, isDead)
707 .addFrameIndex(FI).addImm(0);
703708 }
704709 break;
705710 }
722727 unsigned PredReg = MI->getOperand(3).getReg();
723728 if (OpNum == 0) { // move -> store
724729 unsigned SrcReg = MI->getOperand(1).getReg();
725 NewMI = BuildMI(get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
726 .addImm(0).addImm(Pred).addReg(PredReg);
730 bool isKill = MI->getOperand(1).isKill();
731 NewMI = BuildMI(get(ARM::FSTD)).addReg(SrcReg, false, false, isKill)
732 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
727733 } else { // move -> load
728734 unsigned DstReg = MI->getOperand(0).getReg();
729 NewMI = BuildMI(get(ARM::FLDD), DstReg).addFrameIndex(FI)
730 .addImm(0).addImm(Pred).addReg(PredReg);
731 }
732 break;
733 }
734 }
735
736 if (NewMI)
737 NewMI->copyKillDeadInfo(MI);
735 bool isDead = MI->getOperand(0).isDead();
736 NewMI = BuildMI(get(ARM::FLDD)).addReg(DstReg, true, false, false, isDead)
737 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
738 }
739 break;
740 }
741 }
742
738743 return NewMI;
739744 }
740745
268268 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
269269 if (Ops[0] == 0) { // move -> store
270270 unsigned InReg = MI->getOperand(1).getReg();
271 bool isKill = MI->getOperand(1).isKill();
271272 Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
272273 ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
273 NewMI = BuildMI(get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
274 NewMI = BuildMI(get(Opc)).addReg(InReg, false, false, isKill)
275 .addFrameIndex(FrameIndex)
274276 .addReg(Alpha::F31);
275277 } else { // load -> move
276278 unsigned OutReg = MI->getOperand(0).getReg();
279 bool isDead = MI->getOperand(0).isDead();
277280 Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
278281 ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
279 NewMI = BuildMI(get(Opc), OutReg).addFrameIndex(FrameIndex)
282 NewMI = BuildMI(get(Opc)).addReg(OutReg, true, false, false, isDead)
283 .addFrameIndex(FrameIndex)
280284 .addReg(Alpha::F31);
281285 }
282286 }
283287 break;
284288 }
285 if (NewMI)
286 NewMI->copyKillDeadInfo(MI);
287 return 0;
289 return NewMI;
288290 }
289291
290292 static unsigned AlphaRevCondCode(unsigned Opcode) {
411411 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
412412 if (OpNum == 0) { // move -> store
413413 unsigned InReg = MI->getOperand(1).getReg();
414 bool isKill = MI->getOperand(1).isKill();
414415 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
415 NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32)).addReg(InReg),
416 NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32))
417 .addReg(InReg, false, false, isKill),
416418 FrameIndex);
417419 }
418420 } else { // move -> load
419421 unsigned OutReg = MI->getOperand(0).getReg();
420 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32;
421 NewMI = addFrameReference(BuildMI(TII.get(Opc), OutReg), FrameIndex);
422 }
423 }
424
425 if (NewMI)
426 NewMI->copyKillDeadInfo(MI);
422 bool isDead = MI->getOperand(0).isDead();
423 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
424 ? SPU::STQDr32 : SPU::STQXr32;
425 NewMI = addFrameReference(BuildMI(TII.get(Opc))
426 .addReg(OutReg, true, false, false, isDead), FrameIndex);
427 }
428 }
427429
428430 return NewMI;
429431 #else
385385 (MI->getOperand(1).getReg() == Mips::ZERO) &&
386386 (MI->getOperand(2).isRegister()))
387387 {
388 if (Ops[0] == 0) // COPY -> STORE
388 if (Ops[0] == 0) { // COPY -> STORE
389 unsigned SrcReg = MI->getOperand(2).getReg();
390 bool isKill = MI->getOperand(2).isKill();
389391 NewMI = BuildMI(get(Mips::SW)).addFrameIndex(FI)
390 .addImm(0).addReg(MI->getOperand(2).getReg());
391 else // COPY -> LOAD
392 NewMI = BuildMI(get(Mips::LW), MI->getOperand(0)
393 .getReg()).addImm(0).addFrameIndex(FI);
392 .addImm(0).addReg(SrcReg, false, false, isKill);
393 } else { // COPY -> LOAD
394 unsigned DstReg = MI->getOperand(0).getReg();
395 bool isDead = MI->getOperand(0).isDead();
396 NewMI = BuildMI(get(Mips::LW))
397 .addReg(DstReg, true, false, false, isDead)
398 .addImm(0).addFrameIndex(FI);
399 }
394400 }
395401 break;
396402 }
397403
398 if (NewMI)
399 NewMI->copyKillDeadInfo(MI);
400404 return NewMI;
401405 }
402406
660660 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
661661 if (OpNum == 0) { // move -> store
662662 unsigned InReg = MI->getOperand(1).getReg();
663 NewMI = addFrameReference(BuildMI(get(PPC::STW)).addReg(InReg),
663 bool isKill = MI->getOperand(1).isKill();
664 NewMI = addFrameReference(BuildMI(get(PPC::STW))
665 .addReg(InReg, false, false, isKill),
664666 FrameIndex);
665667 } else { // move -> load
666668 unsigned OutReg = MI->getOperand(0).getReg();
667 NewMI = addFrameReference(BuildMI(get(PPC::LWZ), OutReg),
669 bool isDead = MI->getOperand(0).isDead();
670 NewMI = addFrameReference(BuildMI(get(PPC::LWZ))
671 .addReg(OutReg, true, false, false, isDead),
668672 FrameIndex);
669673 }
670674 } else if ((Opc == PPC::OR8 &&
671675 MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
672676 if (OpNum == 0) { // move -> store
673677 unsigned InReg = MI->getOperand(1).getReg();
674 NewMI = addFrameReference(BuildMI(get(PPC::STD)).addReg(InReg),
678 bool isKill = MI->getOperand(1).isKill();
679 NewMI = addFrameReference(BuildMI(get(PPC::STD))
680 .addReg(InReg, false, false, isKill),
675681 FrameIndex);
676682 } else { // move -> load
677683 unsigned OutReg = MI->getOperand(0).getReg();
678 NewMI = addFrameReference(BuildMI(get(PPC::LD), OutReg), FrameIndex);
684 bool isDead = MI->getOperand(0).isDead();
685 NewMI = addFrameReference(BuildMI(get(PPC::LD))
686 .addReg(OutReg, true, false, false, isDead),
687 FrameIndex);
679688 }
680689 } else if (Opc == PPC::FMRD) {
681690 if (OpNum == 0) { // move -> store
682691 unsigned InReg = MI->getOperand(1).getReg();
683 NewMI = addFrameReference(BuildMI(get(PPC::STFD)).addReg(InReg),
692 bool isKill = MI->getOperand(1).isKill();
693 NewMI = addFrameReference(BuildMI(get(PPC::STFD))
694 .addReg(InReg, false, false, isKill),
684695 FrameIndex);
685696 } else { // move -> load
686697 unsigned OutReg = MI->getOperand(0).getReg();
687 NewMI = addFrameReference(BuildMI(get(PPC::LFD), OutReg), FrameIndex);
698 bool isDead = MI->getOperand(0).isDead();
699 NewMI = addFrameReference(BuildMI(get(PPC::LFD))
700 .addReg(OutReg, true, false, false, isDead),
701 FrameIndex);
688702 }
689703 } else if (Opc == PPC::FMRS) {
690704 if (OpNum == 0) { // move -> store
691705 unsigned InReg = MI->getOperand(1).getReg();
692 NewMI = addFrameReference(BuildMI(get(PPC::STFS)).addReg(InReg),
706 bool isKill = MI->getOperand(1).isKill();
707 NewMI = addFrameReference(BuildMI(get(PPC::STFS))
708 .addReg(InReg, false, false, isKill),
693709 FrameIndex);
694710 } else { // move -> load
695711 unsigned OutReg = MI->getOperand(0).getReg();
696 NewMI = addFrameReference(BuildMI(get(PPC::LFS), OutReg), FrameIndex);
697 }
698 }
699
700 if (NewMI)
701 NewMI->copyKillDeadInfo(MI);
712 bool isDead = MI->getOperand(0).isDead();
713 NewMI = addFrameReference(BuildMI(get(PPC::LFS))
714 .addReg(OutReg, true, false, false, isDead),
715 FrameIndex);
716 }
717 }
718
702719 return NewMI;
703720 }
704721
246246 isFloat = true;
247247 // FALLTHROUGH
248248 case SP::FMOVD:
249 if (OpNum == 0) // COPY -> STORE
249 if (OpNum == 0) { // COPY -> STORE
250 unsigned SrcReg = MI->getOperand(1).getReg();
251 bool isKill = MI->getOperand(1).isKill();
250252 NewMI = BuildMI(get(isFloat ? SP::STFri : SP::STDFri))
251 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
252 else // COPY -> LOAD
253 NewMI = BuildMI(get(isFloat ? SP::LDFri : SP::LDDFri),
254 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
253 .addFrameIndex(FI).addImm(0).addReg(SrcReg, false, false, isKill);
254 } else { // COPY -> LOAD
255 unsigned DstReg = MI->getOperand(0).getReg();
256 bool isDead = MI->getOperand(0).isDead();
257 NewMI = BuildMI(get(isFloat ? SP::LDFri : SP::LDDFri))
258 .addReg(DstReg, true, false, false, isDead).addFrameIndex(FI).addImm(0);
259 }
255260 break;
256261 }
257262
258 if (NewMI)
259 NewMI->copyKillDeadInfo(MI);
260263 return NewMI;
261264 }
6969 /// displacement. An example is: DWORD PTR [EAX + 4].
7070 ///
7171 inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
72 unsigned Reg, int Offset) {
73 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(Offset);
72 unsigned Reg, bool isKill,
73 int Offset) {
74 return MIB.addReg(Reg, false, false, isKill)
75 .addImm(1).addReg(0).addImm(Offset);
7476 }
7577
7678 /// addRegReg - This function is used to add a memory reference of the form:
7779 /// [Reg + Reg].
7880 inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
79 unsigned Reg1, unsigned Reg2) {
80 return MIB.addReg(Reg1).addImm(1).addReg(Reg2).addImm(0);
81 unsigned Reg1, bool isKill1,
82 unsigned Reg2, bool isKill2) {
83 return MIB.addReg(Reg1, false, false, isKill1).addImm(1)
84 .addReg(Reg2, false, false, isKill2).addImm(0);
8185 }
8286
8387 inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
982982 // All instructions input are two-addr instructions. Get the known operands.
983983 unsigned Dest = MI->getOperand(0).getReg();
984984 unsigned Src = MI->getOperand(1).getReg();
985 bool isDead = MI->getOperand(0).isDead();
986 bool isKill = MI->getOperand(1).isKill();
985987
986988 MachineInstr *NewMI = NULL;
987989 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
994996 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
995997 if (!TM.getSubtarget().hasSSE2()) return 0;
996998
997 unsigned A = MI->getOperand(0).getReg();
998999 unsigned B = MI->getOperand(1).getReg();
9991000 unsigned C = MI->getOperand(2).getReg();
1001 if (B != C) return 0;
1002 unsigned A = MI->getOperand(0).getReg();
10001003 unsigned M = MI->getOperand(3).getImm();
1001 if (B != C) return 0;
1002 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
1004 NewMI = BuildMI(get(X86::PSHUFDri)).addReg(A, true, false, false, isDead)
1005 .addReg(B, false, false, isKill).addImm(M);
10031006 break;
10041007 }
10051008 case X86::SHL64ri: {
10061009 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
10071010 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
10081011 // the flags produced by a shift yet, so this is safe.
1009 unsigned Dest = MI->getOperand(0).getReg();
1010 unsigned Src = MI->getOperand(1).getReg();
10111012 unsigned ShAmt = MI->getOperand(2).getImm();
10121013 if (ShAmt == 0 || ShAmt >= 4) return 0;
1013
1014 NewMI = BuildMI(get(X86::LEA64r), Dest)
1015 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
1014
1015 NewMI = BuildMI(get(X86::LEA64r)).addReg(Dest, true, false, false, isDead)
1016 .addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0);
10161017 break;
10171018 }
10181019 case X86::SHL32ri: {
10191020 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
10201021 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
10211022 // the flags produced by a shift yet, so this is safe.
1022 unsigned Dest = MI->getOperand(0).getReg();
1023 unsigned Src = MI->getOperand(1).getReg();
10241023 unsigned ShAmt = MI->getOperand(2).getImm();
10251024 if (ShAmt == 0 || ShAmt >= 4) return 0;
1026
1025
10271026 unsigned Opc = TM.getSubtarget().is64Bit() ?
10281027 X86::LEA64_32r : X86::LEA32r;
1029 NewMI = BuildMI(get(Opc), Dest)
1030 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
1028 NewMI = BuildMI(get(Opc)).addReg(Dest, true, false, false, isDead)
1029 .addReg(0).addImm(1 << ShAmt)
1030 .addReg(Src, false, false, isKill).addImm(0);
10311031 break;
10321032 }
10331033 case X86::SHL16ri: {
10341034 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
10351035 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
10361036 // the flags produced by a shift yet, so this is safe.
1037 unsigned Dest = MI->getOperand(0).getReg();
1038 unsigned Src = MI->getOperand(1).getReg();
10391037 unsigned ShAmt = MI->getOperand(2).getImm();
10401038 if (ShAmt == 0 || ShAmt >= 4) return 0;
1041
1039
10421040 if (DisableLEA16) {
10431041 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
10441042 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
10491047
10501048 // Build and insert into an implicit UNDEF value. This is OK because
10511049 // well be shifting and then extracting the lower 16-bits.
1052 MachineInstr *Undef = BuildMI(get(X86::IMPLICIT_DEF), leaInReg);
1050 MachineInstr *Undef = BuildMI(get(X86::IMPLICIT_DEF), leaInReg);
1051 MachineInstr *InsMI = BuildMI(get(X86::INSERT_SUBREG),leaInReg)
1052 .addReg(leaInReg).addReg(Src, false, false, isKill)
1053 .addImm(X86::SUBREG_16BIT);
10531054
1054 MachineInstr *Ins =
1055 BuildMI(get(X86::INSERT_SUBREG),leaInReg)
1056 .addReg(leaInReg).addReg(Src).addImm(X86::SUBREG_16BIT);
1055 NewMI = BuildMI(get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt)
1056 .addReg(leaInReg, false, false, true).addImm(0);
10571057
1058 NewMI = BuildMI(get(Opc), leaOutReg)
1059 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
1060
1061 MachineInstr *Ext =
1062 BuildMI(get(X86::EXTRACT_SUBREG), Dest)
1063 .addReg(leaOutReg).addImm(X86::SUBREG_16BIT);
1064 Ext->copyKillDeadInfo(MI);
1058 MachineInstr *ExtMI = BuildMI(get(X86::EXTRACT_SUBREG))
1059 .addReg(Dest, true, false, false, isDead)
1060 .addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT);
10651061
10661062 MFI->insert(MBBI, Undef);
1067 MFI->insert(MBBI, Ins); // Insert the insert_subreg
1063 MFI->insert(MBBI, InsMI); // Insert the insert_subreg
1064 MFI->insert(MBBI, NewMI); // Insert the lea inst
1065 MFI->insert(MBBI, ExtMI); // Insert the extract_subreg
10681066 if (LV) {
1069 LV->instructionChanged(MI, NewMI); // Update live variables
1070 LV->addVirtualRegisterKilled(leaInReg, NewMI);
1067 // Update live variables
1068 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1069 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1070 if (isKill)
1071 LV->replaceKillInstruction(Src, MI, InsMI);
1072 if (isDead)
1073 LV->replaceKillInstruction(Dest, MI, ExtMI);
10711074 }
1072 MFI->insert(MBBI, NewMI); // Insert the new inst
1073 if (LV) LV->addVirtualRegisterKilled(leaOutReg, Ext);
1074 MFI->insert(MBBI, Ext); // Insert the extract_subreg
1075 return Ext;
1075 return ExtMI;
10761076 } else {
1077 NewMI = BuildMI(get(X86::LEA16r), Dest)
1078 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
1077 NewMI = BuildMI(get(X86::LEA16r)).addReg(Dest, true, false, false, isDead)
1078 .addReg(0).addImm(1 << ShAmt)
1079 .addReg(Src, false, false, isKill).addImm(0);
10791080 }
10801081 break;
10811082 }
10941095 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
10951096 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
10961097 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1097 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1);
1098 NewMI = addRegOffset(BuildMI(get(Opc))
1099 .addReg(Dest, true, false, false, isDead),
1100 Src, isKill, 1);
10981101 break;
10991102 }
11001103 case X86::INC16r:
11011104 case X86::INC64_16r:
11021105 if (DisableLEA16) return 0;
11031106 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1104 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
1107 NewMI = addRegOffset(BuildMI(get(X86::LEA16r))
1108 .addReg(Dest, true, false, false, isDead),
1109 Src, isKill, 1);
11051110 break;
11061111 case X86::DEC64r:
11071112 case X86::DEC32r: {
11081113 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
11091114 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
11101115 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1111 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1);
1116 NewMI = addRegOffset(BuildMI(get(Opc))
1117 .addReg(Dest, true, false, false, isDead),
1118 Src, isKill, -1);
11121119 break;
11131120 }
11141121 case X86::DEC16r:
11151122 case X86::DEC64_16r:
11161123 if (DisableLEA16) return 0;
11171124 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1118 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
1125 NewMI = addRegOffset(BuildMI(get(X86::LEA16r))
1126 .addReg(Dest, true, false, false, isDead),
1127 Src, isKill, -1);
11191128 break;
11201129 case X86::ADD64rr:
11211130 case X86::ADD32rr: {
11221131 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
11231132 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
11241133 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1125 NewMI = addRegReg(BuildMI(get(Opc), Dest), Src,
1126 MI->getOperand(2).getReg());
1134 unsigned Src2 = MI->getOperand(2).getReg();
1135 bool isKill2 = MI->getOperand(2).isKill();
1136 NewMI = addRegReg(BuildMI(get(Opc))
1137 .addReg(Dest, true, false, false, isDead),
1138 Src, isKill, Src2, isKill2);
1139 if (LV && isKill2)
1140 LV->replaceKillInstruction(Src2, MI, NewMI);
11271141 break;
11281142 }
1129 case X86::ADD16rr:
1143 case X86::ADD16rr: {
11301144 if (DisableLEA16) return 0;
11311145 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1132 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
1133 MI->getOperand(2).getReg());
1146 unsigned Src2 = MI->getOperand(2).getReg();
1147 bool isKill2 = MI->getOperand(2).isKill();
1148 NewMI = addRegReg(BuildMI(get(X86::LEA16r))
1149 .addReg(Dest, true, false, false, isDead),
1150 Src, isKill, Src2, isKill2);
1151 if (LV && isKill2)
1152 LV->replaceKillInstruction(Src2, MI, NewMI);
11341153 break;
1154 }
11351155 case X86::ADD64ri32:
11361156 case X86::ADD64ri8:
11371157 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
11381158 if (MI->getOperand(2).isImmediate())
1139 NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
1140 MI->getOperand(2).getImm());
1159 NewMI = addRegOffset(BuildMI(get(X86::LEA64r))
1160 .addReg(Dest, true, false, false, isDead),
1161 Src, isKill, MI->getOperand(2).getImm());
11411162 break;
11421163 case X86::ADD32ri:
11431164 case X86::ADD32ri8:
11441165 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
11451166 if (MI->getOperand(2).isImmediate()) {
11461167 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1147 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src,
1148 MI->getOperand(2).getImm());
1168 NewMI = addRegOffset(BuildMI(get(Opc))
1169 .addReg(Dest, true, false, false, isDead),
1170 Src, isKill, MI->getOperand(2).getImm());
11491171 }
11501172 break;
11511173 case X86::ADD16ri:
11531175 if (DisableLEA16) return 0;
11541176 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
11551177 if (MI->getOperand(2).isImmediate())
1156 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
1157 MI->getOperand(2).getImm());
1178 NewMI = addRegOffset(BuildMI(get(X86::LEA16r))
1179 .addReg(Dest, true, false, false, isDead),
1180 Src, isKill, MI->getOperand(2).getImm());
11581181 break;
11591182 case X86::SHL16ri:
11601183 if (DisableLEA16) return 0;
11701193 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
11711194 : (MIOpc == X86::SHL32ri
11721195 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1173 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
1196 NewMI = addFullAddress(BuildMI(get(Opc))
1197 .addReg(Dest, true, false, false, isDead), AM);
1198 if (isKill)
1199 NewMI->getOperand(3).setIsKill(true);
11741200 }
11751201 break;
11761202 }
11801206
11811207 if (!NewMI) return 0;
11821208
1183 NewMI->copyKillDeadInfo(MI);
1184 if (LV) LV->instructionChanged(MI, NewMI); // Update live variables
1209 if (LV) { // Update live variables
1210 if (isKill)
1211 LV->replaceKillInstruction(Src, MI, NewMI);
1212 if (isDead)
1213 LV->replaceKillInstruction(Dest, MI, NewMI);
1214 }
1215
11851216 MFI->insert(MBBI, NewMI); // Insert the new inst
11861217 return NewMI;
11871218 }
15061537 MachineOperand &MO) {
15071538 if (MO.isRegister())
15081539 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
1509 false, false, MO.getSubReg());
1540 MO.isKill(), MO.isDead(), MO.getSubReg());
15101541 else if (MO.isImmediate())
15111542 MIB = MIB.addImm(MO.getImm());
15121543 else if (MO.isFrameIndex())
17681799 }
17691800
17701801 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
1771 SmallVectorImpl &Addr,
1772 const TargetRegisterClass *RC,
1802 SmallVectorImpl &Addr,
1803 const TargetRegisterClass *RC,
17731804 SmallVectorImpl &NewMIs) const {
17741805 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
17751806 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
19051936 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
19061937 else if (MI->getOpcode() == X86::MOV8r0)
19071938 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
1908 if (NewMI) {
1909 NewMI->copyKillDeadInfo(MI);
1939 if (NewMI)
19101940 return NewMI;
1911 }
19121941
19131942 OpcodeTablePtr = &RegOp2MemOpTable0;
19141943 } else if (i == 1) {
19271956 NewMI = FuseTwoAddrInst(I->second, MOs, MI, *this);
19281957 else
19291958 NewMI = FuseInst(I->second, i, MOs, MI, *this);
1930 NewMI->copyKillDeadInfo(MI);
19311959 return NewMI;
19321960 }
19331961 }
749749 .addExternalSymbol("_alloca");
750750 // Restore EAX
751751 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
752 StackPtr, NumBytes-4);
752 StackPtr, false, NumBytes-4);
753753 MBB.insert(MBBI, MI);
754754 }
755755 } else {
845845 if (CSSize) {
846846 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
847847 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
848 FramePtr, -CSSize);
848 FramePtr, false, -CSSize);
849849 MBB.insert(MBBI, MI);
850850 } else
851851 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).