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ARM: fix VMOVvnf32 decoding when ambiguous with VCVT Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183612 91177308-0d34-0410-b5e6-96231b3b80d8 Amaury de la Vieuville 7 years ago
2 changed file(s) with 11 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
44694469 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
44704470 unsigned imm = fieldFromInstruction(Insn, 16, 6);
44714471 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4472 unsigned op = fieldFromInstruction(Insn, 5, 1);
44724473
44734474 DecodeStatus S = MCDisassembler::Success;
44744475
44754476 // VMOVv2f32 is ambiguous with these decodings.
44764477 if (!(imm & 0x38) && cmode == 0xF) {
4478 if (op == 1) return MCDisassembler::Fail;
44774479 Inst.setOpcode(ARM::VMOVv2f32);
44784480 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
44794481 }
44974499 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
44984500 unsigned imm = fieldFromInstruction(Insn, 16, 6);
44994501 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4502 unsigned op = fieldFromInstruction(Insn, 5, 1);
45004503
45014504 DecodeStatus S = MCDisassembler::Success;
45024505
45034506 // VMOVv4f32 is ambiguous with these decodings.
45044507 if (!(imm & 0x38) && cmode == 0xF) {
4508 if (op == 1) return MCDisassembler::Fail;
45054509 Inst.setOpcode(ARM::VMOVv4f32);
45064510 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
45074511 }
0 # VMOV cmode=0b1111 op=1
1 # RUN: echo "0x70 0xef 0xc7 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
2
3 # VMOV cmode=0b1111 op=1
4 # RUN: echo "0x30 0x0f 0x80 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
5
6 # CHECK: invalid instruction encoding