llvm.org GIT mirror llvm / 9ed06db
Add support for lowering 128-bit shifts on ppc64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48029 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 12 years ago
2 changed file(s) with 76 addition(s) and 46 deletion(s). Raw diff Collapse all Expand all
232232 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
233233 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
234234 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
235 // 64-bit PowerPC wants to expand i128 shifts itself.
236 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
237 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
238 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
235239 } else {
236240 // 32-bit PowerPC wants to expand i64 shifts itself.
237241 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
24152419 }
24162420
24172421 SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2418 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2419 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
2422 MVT::ValueType VT = Op.getValueType();
2423 unsigned BitWidth = MVT::getSizeInBits(VT);
2424 assert(Op.getNumOperands() == 3 &&
2425 VT == Op.getOperand(1).getValueType() &&
2426 "Unexpected SHL!");
24202427
24212428 // Expand into a bunch of logical ops. Note that these ops
24222429 // depend on the PPC behavior for oversized shift amounts.
24232430 SDOperand Lo = Op.getOperand(0);
24242431 SDOperand Hi = Op.getOperand(1);
24252432 SDOperand Amt = Op.getOperand(2);
2426
2427 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2428 DAG.getConstant(32, MVT::i32), Amt);
2429 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
2430 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
2431 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2432 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2433 DAG.getConstant(-32U, MVT::i32));
2434 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
2435 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2436 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
2433 MVT::ValueType AmtVT = Amt.getValueType();
2434
2435 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2436 DAG.getConstant(BitWidth, AmtVT), Amt);
2437 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
2438 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
2439 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2440 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
2441 DAG.getConstant(-BitWidth, AmtVT));
2442 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
2443 SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
2444 SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
24372445 SDOperand OutOps[] = { OutLo, OutHi };
2438 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2446 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
24392447 OutOps, 2);
24402448 }
24412449
24422450 SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2443 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2444 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
2445
2446 // Otherwise, expand into a bunch of logical ops. Note that these ops
2451 MVT::ValueType VT = Op.getValueType();
2452 unsigned BitWidth = MVT::getSizeInBits(VT);
2453 assert(Op.getNumOperands() == 3 &&
2454 VT == Op.getOperand(1).getValueType() &&
2455 "Unexpected SRL!");
2456
2457 // Expand into a bunch of logical ops. Note that these ops
24472458 // depend on the PPC behavior for oversized shift amounts.
24482459 SDOperand Lo = Op.getOperand(0);
24492460 SDOperand Hi = Op.getOperand(1);
24502461 SDOperand Amt = Op.getOperand(2);
2451
2452 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2453 DAG.getConstant(32, MVT::i32), Amt);
2454 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2455 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2456 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2457 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2458 DAG.getConstant(-32U, MVT::i32));
2459 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
2460 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2461 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
2462 MVT::ValueType AmtVT = Amt.getValueType();
2463
2464 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2465 DAG.getConstant(BitWidth, AmtVT), Amt);
2466 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
2467 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
2468 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2469 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
2470 DAG.getConstant(-BitWidth, AmtVT));
2471 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
2472 SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
2473 SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
24622474 SDOperand OutOps[] = { OutLo, OutHi };
2463 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2475 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
24642476 OutOps, 2);
24652477 }
24662478
24672479 SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
2468 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2469 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
2470
2471 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
2480 MVT::ValueType VT = Op.getValueType();
2481 unsigned BitWidth = MVT::getSizeInBits(VT);
2482 assert(Op.getNumOperands() == 3 &&
2483 VT == Op.getOperand(1).getValueType() &&
2484 "Unexpected SRA!");
2485
2486 // Expand into a bunch of logical ops, followed by a select_cc.
24722487 SDOperand Lo = Op.getOperand(0);
24732488 SDOperand Hi = Op.getOperand(1);
24742489 SDOperand Amt = Op.getOperand(2);
2475
2476 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2477 DAG.getConstant(32, MVT::i32), Amt);
2478 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2479 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2480 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2481 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2482 DAG.getConstant(-32U, MVT::i32));
2483 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
2484 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
2485 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
2490 MVT::ValueType AmtVT = Amt.getValueType();
2491
2492 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2493 DAG.getConstant(BitWidth, AmtVT), Amt);
2494 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
2495 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
2496 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2497 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
2498 DAG.getConstant(-BitWidth, AmtVT));
2499 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5);
2500 SDOperand OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt);
2501 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
24862502 Tmp4, Tmp6, ISD::SETLE);
24872503 SDOperand OutOps[] = { OutLo, OutHi };
2488 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2504 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
24892505 OutOps, 2);
24902506 }
24912507
0 ; RUN: llvm-as < %s | llc -march=ppc64 | grep sld | count 5
1
2 define i128 @foo_lshr(i128 %x, i128 %y) {
3 %r = lshr i128 %x, %y
4 ret i128 %r
5 }
6 define i128 @foo_ashr(i128 %x, i128 %y) {
7 %r = ashr i128 %x, %y
8 ret i128 %r
9 }
10 define i128 @foo_shl(i128 %x, i128 %y) {
11 %r = shl i128 %x, %y
12 ret i128 %r
13 }