llvm.org GIT mirror llvm / 9ecdca9
Silence more static analyzer warnings. Add in definedness checks for shift operators, null checks when pointers are assumed by the code to be non-null, and explicit unreachables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224255 91177308-0d34-0410-b5e6-96231b3b80d8 Michael Ilseman 5 years ago
13 changed file(s) with 45 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
238238 }
239239
240240 BitVector &set(unsigned Idx) {
241 assert(Bits && "Bits never allocated");
241242 Bits[Idx / BITWORD_SIZE] |= BitWord(1) << (Idx % BITWORD_SIZE);
242243 return *this;
243244 }
545546
546547 void grow(unsigned NewSize) {
547548 Capacity = std::max(NumBitWords(NewSize), Capacity * 2);
549 assert(Capacity > 0 && "realloc-ing zero space");
548550 Bits = (BitWord *)std::realloc(Bits, Capacity * sizeof(BitWord));
549551
550552 clear_unused_bits();
767767 assert(NumValues == VTs.NumVTs &&
768768 "NumValues wasn't wide enough for its operands!");
769769 for (unsigned i = 0; i != Ops.size(); ++i) {
770 assert(OperandList && "no operands available");
770771 OperandList[i].setUser(this);
771772 OperandList[i].setInitial(Ops[i]);
772773 }
275275 }
276276
277277 const StringTableOffset &getStringTableOffset() const {
278 assert(isSet() && "COFFSymbolRef points to nothing!");
278279 return CS16 ? CS16->Name.Offset : CS32->Name.Offset;
279280 }
280281
281282 uint32_t getValue() const { return CS16 ? CS16->Value : CS32->Value; }
282283
283284 int32_t getSectionNumber() const {
285 assert(isSet() && "COFFSymbolRef points to nothing!");
284286 if (CS16) {
285287 // Reserved sections are returned as negative numbers.
286288 if (CS16->SectionNumber <= COFF::MaxNumberOfSections16)
290292 return static_cast(CS32->SectionNumber);
291293 }
292294
293 uint16_t getType() const { return CS16 ? CS16->Type : CS32->Type; }
295 uint16_t getType() const {
296 assert(isSet() && "COFFSymbolRef points to nothing!");
297 return CS16 ? CS16->Type : CS32->Type;
298 }
294299
295300 uint8_t getStorageClass() const {
301 assert(isSet() && "COFFSymbolRef points to nothing!");
296302 return CS16 ? CS16->StorageClass : CS32->StorageClass;
297303 }
298304
299305 uint8_t getNumberOfAuxSymbols() const {
306 assert(isSet() && "COFFSymbolRef points to nothing!");
300307 return CS16 ? CS16->NumberOfAuxSymbols : CS32->NumberOfAuxSymbols;
301308 }
302309
359366 }
360367
361368 private:
369 bool isSet() const { return CS16 || CS32; }
370
362371 const coff_symbol16 *CS16;
363372 const coff_symbol32 *CS32;
364373 };
14911491
14921492 if (NumBits == 0) return; // 1-byte aligned: no need to emit alignment.
14931493
1494 assert(NumBits < std::numeric_limits::digits &&
1495 "undefined behavior");
14941496 if (getCurrentSection()->getKind().isText())
1495 OutStreamer.EmitCodeAlignment(1 << NumBits);
1497 OutStreamer.EmitCodeAlignment(1u << NumBits);
14961498 else
1497 OutStreamer.EmitValueToAlignment(1 << NumBits);
1499 OutStreamer.EmitValueToAlignment(1u << NumBits);
14981500 }
14991501
15001502 //===----------------------------------------------------------------------===//
7373
7474 // Is domain available?
7575 bool hasDomain(unsigned domain) const {
76 assert(domain < std::numeric_limits::digits &&
77 "undefined behavior");
7678 return AvailableDomains & (1u << domain);
7779 }
7880
337339 // All uses of B are referred to A.
338340 B->Next = retain(A);
339341
340 for (unsigned rx = 0; rx != NumRegs; ++rx)
342 for (unsigned rx = 0; rx != NumRegs; ++rx) {
343 assert(LiveRegs && "no space allocated for live registers");
341344 if (LiveRegs[rx].Value == B)
342345 setLiveReg(rx, A);
346 }
343347 return true;
344348 }
345349
644648 SmallVector Regs;
645649 for (SmallVectorImpl::iterator i=used.begin(), e=used.end(); i!=e; ++i) {
646650 int rx = *i;
651 assert(LiveRegs && "no space allocated for live registers");
647652 const LiveReg &LR = LiveRegs[rx];
648653 // This useless DomainValue could have been missed above.
649654 if (!LR.Value->getCommonDomains(available)) {
683688 continue;
684689
685690 // If latest didn't merge, it is useless now. Kill all registers using it.
686 for (SmallVectorImpl::iterator i=used.begin(), e=used.end(); i!=e; ++i)
687 if (LiveRegs[*i].Value == Latest)
688 kill(*i);
691 for (int i : used) {
692 assert(LiveRegs && "no space allocated for live registers");
693 if (LiveRegs[i].Value == Latest)
694 kill(i);
695 }
689696 }
690697
691698 // dv is the DomainValue we are going to use for this instruction.
128128 << " use list MachineOperand " << MO
129129 << " has no parent instruction.\n";
130130 Valid = false;
131 continue;
131132 }
132133 MachineOperand *MO0 = &MI->getOperand(0);
133134 unsigned NumOps = MI->getNumOperands();
4646 }
4747
4848 // Does this MF have different CSRs?
49 assert(TRI && "no register info set");
4950 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
5051 if (Update || CSR != CalleeSaved) {
5152 // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
7576 /// registers filtered out. Volatile registers come first followed by CSR
7677 /// aliases ordered according to the CSR order specified by the target.
7778 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
79 assert(RC && "no register class given");
7880 RCInfo &RCI = RegClass[RC->getID()];
7981
8082 // Raw register count, including all reserved regs.
565565 } else if (NumParts > 0) {
566566 // If the intermediate type was expanded, split each the value into
567567 // legal parts.
568 assert(NumIntermediates != 0 && "division by zero");
568569 assert(NumParts % NumIntermediates == 0 &&
569570 "Must expand into a divisible number of parts!");
570571 unsigned Factor = NumParts / NumIntermediates;
14071408 if (TM.Options.NoNaNsFPMath)
14081409 Condition = getFCmpCodeWithoutNaN(Condition);
14091410 } else {
1410 Condition = ISD::SETEQ; // silence warning.
1411 (void)Condition; // silence warning.
14111412 llvm_unreachable("Unknown compare instruction");
14121413 }
14131414
7575 static void dumpApplePropertyAttribute(raw_ostream &OS, uint64_t Val) {
7676 OS << " (";
7777 do {
78 uint64_t Bit = 1ULL << countTrailingZeros(Val);
78 uint64_t Shift = countTrailingZeros(Val);
79 assert(Shift < 64 && "undefined behavior");
80 uint64_t Bit = 1ULL << Shift;
7981 if (const char *PropName = ApplePropertyString(Bit))
8082 OS << PropName;
8183 else
180180 Res = (Index << 2) | 3;
181181 break;
182182 }
183 default:
184 llvm_unreachable("unreachable case");
183185 }
184186
185187 Symb.p = Res;
235235
236236 if (isShiftedMask_64(Imm)) {
237237 I = countTrailingZeros(Imm);
238 assert(I < 64 && "undefined behavior");
238239 CTO = CountTrailingOnes_64(Imm >> I);
239240 } else {
240241 Imm |= ~Mask;
176176 MCELF::SetType(SD, ELF::STT_NOTYPE);
177177 MCELF::SetBinding(SD, ELF::STB_LOCAL);
178178 SD.setExternal(false);
179 Symbol->setSection(*getCurrentSection().first);
179 auto Sec = getCurrentSection().first;
180 assert(Sec && "need a section");
181 Symbol->setSection(*Sec);
180182
181183 const MCExpr *Value = MCSymbolRefExpr::Create(Start, getContext());
182184 Symbol->setVariableValue(Value);
85768576 unsigned InvMask = cast(N->getOperand(2))->getZExtValue();
85778577 unsigned LSB = countTrailingZeros(~InvMask);
85788578 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
8579 unsigned Mask = (1 << Width)-1;
8579 assert(Width < std::numeric_limits::digits &&
8580 "undefined behavior");
8581 unsigned Mask = (1u << Width) - 1;
85808582 unsigned Mask2 = N11C->getZExtValue();
85818583 if ((Mask & (~Mask2)) == 0)
85828584 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),