llvm.org GIT mirror llvm / 9e7a312
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
4 changed file(s) with 53 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
614614 return false;
615615
616616 bool isDPR = NewOpc == ARM::FLDMD || NewOpc == ARM::FSTMD;
617 unsigned Offset = isAM5
618 ? ARM_AM::getAM5Opc((AddSub == ARM_AM::sub) ? ARM_AM::db : ARM_AM::ia,
619 true, isDPR ? 2 : 1)
620 : (isAM2
621 ? ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift)
622 : Bytes);
617 unsigned Offset = 0;
618 if (isAM5)
619 Offset = ARM_AM::getAM5Opc((AddSub == ARM_AM::sub)
620 ? ARM_AM::db
621 : ARM_AM::ia, true, (isDPR ? 2 : 1));
622 else if (isAM2)
623 Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
624 else
625 Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes;
623626 if (isLd) {
624627 if (isAM5)
625628 // FLDMS, FLDMD
100100
101101 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
102102 CodeGenOpt::Level OptLevel) {
103 // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
104 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
103 // FIXME: temporarily disabling load / store optimization pass for Thumb1 mode.
104 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti &&
105 !Subtarget.isThumb1Only())
105106 PM.add(createARMLoadStoreOptimizationPass());
106107
107108 if (OptLevel != CodeGenOpt::None &&
598598 // FIXME
599599 bool isLDM = (MI->getOpcode() == ARM::LDM ||
600600 MI->getOpcode() == ARM::LDM_RET ||
601 MI->getOpcode() == ARM::t2LDM ||
601602 MI->getOpcode() == ARM::t2LDM_RET);
602603 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
603604 } else
0 ; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
1
2 @X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
3
4 define i32 @t1() {
5 ; CHECK: t1:
6 ; CHECK: stmfd sp!, {r7, lr}
7 ; CHECK: ldmfd sp!, {r7, pc}
8 %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; [#uses=1]
9 %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; [#uses=1]
10 %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; [#uses=1]
11 ret i32 %tmp4
12 }
13
14 define i32 @t2() {
15 ; CHECK: t2:
16 ; CHECK: stmfd sp!, {r7, lr}
17 ; CHECK: ldmia
18 ; CHECK: ldmfd sp!, {r7, pc}
19 %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; [#uses=1]
20 %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; [#uses=1]
21 %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; [#uses=1]
22 %tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; [#uses=1]
23 ret i32 %tmp6
24 }
25
26 define i32 @t3() {
27 ; CHECK: t3:
28 ; CHECK: stmfd sp!, {r7, lr}
29 ; CHECK: ldmfd sp!, {r7, pc}
30 %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; [#uses=1]
31 %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; [#uses=1]
32 %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; [#uses=1]
33 %tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; [#uses=1]
34 ret i32 %tmp6
35 }
36
37 declare i32 @f1(i32, i32)
38
39 declare i32 @f2(i32, i32, i32)