llvm.org GIT mirror llvm / 9de4672
[AVR] Disallow the LDDWRdPtrQ instruction with Z as the destination This is an AVR-specific workaround for a limitation of the register allocator that only exposes itself on targets with high register contention like AVR, which only has three pointer registers. The three pointer registers are X, Y, and Z. In most nontrivial functions, Y is reserved for the frame pointer, as per the calling convention. This leaves X and Z. Some instructions, such as LPM ("load program memory"), are only defined for the Z register. Sometimes this just leaves X. When the backend generates a LDDWRdPtrQ instruction with Z as the destination pointer, it usually trips up the register allocator with this error message: LLVM ERROR: ran out of registers during register allocation This patch is a hacky workaround. We ban the LDDWRdPtrQ instruction from ever using the Z register as an operand. This gives the register allocator a bit more space to allocate, fixing the regalloc exhaustion error. Here is a description from the patch author Peter Nimmervoll As far as I understand the problem occurs when LDDWRdPtrQ uses the ptrdispregs register class as target register. This should work, but the allocator can't deal with this for some reason. So from my testing, it seams like (and I might be totally wrong on this) the allocator reserves the Z register for the ICALL instruction and then the register class ptrdispregs only has 1 register left and we can't use Y for source and destination. Removing the Z register from DREGS fixes the problem but removing Y register does not. More information about the bug can be found on the avr-rust issue tracker at https://github.com/avr-rust/rust/issues/37. A bug has raised to track the removal of this workaround and a proper fix; PR39553 at https://bugs.llvm.org/show_bug.cgi?id=39553. Patch by Peter Nimmervoll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346114 91177308-0d34-0410-b5e6-96231b3b80d8 Dylan McKay 2 years ago
6 changed file(s) with 91 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
12211221 // ldd Rd, P+q
12221222 // ldd Rd+1, P+q+1
12231223 let Constraints = "@earlyclobber $dst" in
1224 def LDDWRdPtrQ : Pseudo<(outs DREGS:$dst),
1224 def LDDWRdPtrQ : Pseudo<(outs DREGS_WITHOUT_Z_WORKAROUND:$dst),
12251225 (ins memri:$memri),
12261226 "lddw\t$dst, $memri",
12271227 [(set i16:$dst, (load addr:$memri))]>,
156156 R9R8, R7R6, R5R4, R3R2, R1R0
157157 )>;
158158
159 // The 16-bit DREGS register class, excluding the Z pointer register.
160 //
161 // This is used by instructions which cause high pointer register
162 // contention which leads to an assertion in the register allocator.
163 //
164 // There is no technical reason why instructions that use this class
165 // cannot use Z; it's simply a workaround a regalloc bug.
166 //
167 // More information can be found in PR39553.
168 def DREGS_WITHOUT_Z_WORKAROUND : RegisterClass<"AVR", [i16], 8,
169 (
170 // Return value and arguments.
171 add R25R24, R19R18, R21R20, R23R22,
172 // Scratch registers.
173 R27R26,
174 // Callee saved registers.
175 R29R28, R17R16, R15R14, R13R12, R11R10,
176 R9R8, R7R6, R5R4, R3R2, R1R0
177 )>;
178
159179 // 16-bit register class for immediate instructions.
160180 def DLDREGS : RegisterClass<"AVR", [i16], 8,
161181 (
2424
2525 ; CHECK-LABEL: test_lddwrdptrq
2626
27 ; CHECK: ldd [[SCRATCH:r[0-9]+]], Z+10
27 ; CHECK: ldd [[SCRATCH:r[0-9]+]], Y+10
2828 ; CHECK-NEXT: push [[SCRATCH]]
29 ; CHECK-NEXT: ldd [[SCRATCH]], Z+11
30 ; CHECK-NEXT: mov r31, [[SCRATCH]]
31 ; CHECK-NEXT: pop r30
29 ; CHECK-NEXT: ldd [[SCRATCH]], Y+11
30 ; CHECK-NEXT: mov r29, [[SCRATCH]]
31 ; CHECK-NEXT: pop r28
3232
33 early-clobber $r31r30 = LDDWRdPtrQ undef $r31r30, 10
33 early-clobber $r29r28 = LDDWRdPtrQ undef $r29r28, 10
3434 ...
1717
1818 ; CHECK-LABEL: test_lddwrdptrq
1919
20 ; CHECK: ldd r30, Y+10
21 ; CHECK-NEXT: ldd r31, Y+11
20 ; CHECK: ldd r28, Z+10
21 ; CHECK-NEXT: ldd r29, Z+11
2222
23 early-clobber $r31r30 = LDDWRdPtrQ undef $r29r28, 10
23 early-clobber $r29r28 = LDDWRdPtrQ undef $r31r30, 10
2424 ...
0 ; RUN: llc < %s -march=avr | FileCheck %s
1
2 %"fmt::Formatter" = type { i32, { i8*, void (i8*)** } }
3
4 @str.1b = external constant [0 x i8]
5
6 define void @"TryFromIntError::Debug"(%"fmt::Formatter"* dereferenceable(32)) unnamed_addr #0 personality i32 (...)* @rust_eh_personality {
7 ; CHECK-LABEL: "TryFromIntError::Debug"
8 start:
9 %builder = alloca i8, align 8
10 %1 = getelementptr inbounds %"fmt::Formatter", %"fmt::Formatter"* %0, i16 0, i32 1
11 %2 = bitcast { i8*, void (i8*)** }* %1 to {}**
12 %3 = load {}*, {}** %2, align 2
13 %4 = getelementptr inbounds %"fmt::Formatter", %"fmt::Formatter"* %0, i16 0, i32 1, i32 1
14 %5 = load void (i8*)**, void (i8*)*** %4, align 2
15 %6 = getelementptr inbounds void (i8*)*, void (i8*)** %5, i16 3
16 %7 = bitcast void (i8*)** %6 to i8 ({}*, i8*, i16)**
17 %8 = load i8 ({}*, i8*, i16)*, i8 ({}*, i8*, i16)** %7, align 2
18 %9 = tail call i8 %8({}* nonnull %3, i8* noalias nonnull readonly getelementptr inbounds ([0 x i8], [0 x i8]* @str.1b, i16 0, i16 0), i16 15)
19 unreachable
20 }
21
22 declare i32 @rust_eh_personality(...) unnamed_addr
23
24 attributes #0 = { uwtable }
0 ; RUN: llc < %s -march=avr | FileCheck %s
1
2 %"fmt::Formatter.1.77.153.229.305.381.1673" = type { [0 x i8], i32, [0 x i8], i32, [0 x i8], i8, [0 x i8], %"option::Option.0.76.152.228.304.380.1672", [0 x i8], %"option::Option.0.76.152.228.304.380.1672", [0 x i8], { {}*, {}* }, [0 x i8], { i8*, i8* }, [0 x i8], { [0 x { i8*, i8* }]*, i16 }, [0 x i8] }
3 %"option::Option.0.76.152.228.304.380.1672" = type { [0 x i8], i8, [2 x i8] }
4
5 @str.4S = external constant [5 x i8]
6
7 ; Function Attrs: uwtable
8 define void @"_ZN65_$LT$lib..str..Chars$LT$$u27$a$GT$$u20$as$u20$lib..fmt..Debug$GT$3fmt17h76a537e22649f739E"(%"fmt::Formatter.1.77.153.229.305.381.1673"* dereferenceable(27) %__arg_0) unnamed_addr #0 personality i32 (...)* @rust_eh_personality {
9 ; CHECK-LABEL: "_ZN65_$LT$lib..str..Chars$LT$$u27$a$GT$$u20$as$u20$lib..fmt..Debug$GT$3fmt17h76a537e22649f739E"
10 start:
11 %0 = getelementptr inbounds %"fmt::Formatter.1.77.153.229.305.381.1673", %"fmt::Formatter.1.77.153.229.305.381.1673"* %__arg_0, i16 0, i32 11, i32 0
12 %1 = load {}*, {}** %0, align 1, !noalias !0, !nonnull !9
13 %2 = getelementptr inbounds %"fmt::Formatter.1.77.153.229.305.381.1673", %"fmt::Formatter.1.77.153.229.305.381.1673"* %__arg_0, i16 0, i32 11, i32 1
14 %3 = bitcast {}** %2 to i1 ({}*, [0 x i8]*, i16)***
15 %4 = load i1 ({}*, [0 x i8]*, i16)**, i1 ({}*, [0 x i8]*, i16)*** %3, align 1, !noalias !0, !nonnull !9
16 %5 = getelementptr inbounds i1 ({}*, [0 x i8]*, i16)*, i1 ({}*, [0 x i8]*, i16)** %4, i16 3
17 %6 = load i1 ({}*, [0 x i8]*, i16)*, i1 ({}*, [0 x i8]*, i16)** %5, align 1, !invariant.load !9, !noalias !0, !nonnull !9
18 %7 = tail call zeroext i1 %6({}* nonnull %1, [0 x i8]* noalias nonnull readonly bitcast ([5 x i8]* @str.4S to [0 x i8]*), i16 5), !noalias !10
19 unreachable
20 }
21
22 declare i32 @rust_eh_personality(...) unnamed_addr
23
24 attributes #0 = { uwtable }
25
26 !0 = !{!1, !3, !5, !6, !8}
27 !1 = distinct !{!1, !2, !"_ZN3lib3fmt9Formatter9write_str17ha1a9656fc66ccbe5E: %data.0"}
28 !2 = distinct !{!2, !"_ZN3lib3fmt9Formatter9write_str17ha1a9656fc66ccbe5E"}
29 !3 = distinct !{!3, !4, !"_ZN3lib3fmt8builders16debug_struct_new17h352a1de8f89c2bc3E: argument 0"}
30 !4 = distinct !{!4, !"_ZN3lib3fmt8builders16debug_struct_new17h352a1de8f89c2bc3E"}
31 !5 = distinct !{!5, !4, !"_ZN3lib3fmt8builders16debug_struct_new17h352a1de8f89c2bc3E: %name.0"}
32 !6 = distinct !{!6, !7, !"_ZN3lib3fmt9Formatter12debug_struct17ha1ff79f633171b68E: argument 0"}
33 !7 = distinct !{!7, !"_ZN3lib3fmt9Formatter12debug_struct17ha1ff79f633171b68E"}
34 !8 = distinct !{!8, !7, !"_ZN3lib3fmt9Formatter12debug_struct17ha1ff79f633171b68E: %name.0"}
35 !9 = !{}
36 !10 = !{!3, !6}