llvm.org GIT mirror llvm / 9de0bdb
Shrink various scheduling tables by using narrower types. 16 bits ought to be enough for everyone. This shrinks clang by ~1MB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325941 91177308-0d34-0410-b5e6-96231b3b80d8 Benjamin Kramer 2 years ago
4 changed file(s) with 35 addition(s) and 30 deletion(s). Raw diff Collapse all Expand all
9393 /// cycle in which operands are read and written.
9494 ///
9595 struct InstrItinerary {
96 int NumMicroOps; ///< # of micro-ops, -1 means it's variable
97 unsigned FirstStage; ///< Index of first stage in itinerary
98 unsigned LastStage; ///< Index of last + 1 stage in itinerary
99 unsigned FirstOperandCycle; ///< Index of first operand rd/wr
100 unsigned LastOperandCycle; ///< Index of last + 1 operand rd/wr
96 int16_t NumMicroOps; ///< # of micro-ops, -1 means it's variable
97 uint16_t FirstStage; ///< Index of first stage in itinerary
98 uint16_t LastStage; ///< Index of last + 1 stage in itinerary
99 uint16_t FirstOperandCycle; ///< Index of first operand rd/wr
100 uint16_t LastOperandCycle; ///< Index of last + 1 operand rd/wr
101101 };
102102
103103 //===----------------------------------------------------------------------===//
124124
125125 /// \brief Returns true if the index is for the end marker itinerary.
126126 bool isEndMarker(unsigned ItinClassIndx) const {
127 return ((Itineraries[ItinClassIndx].FirstStage == ~0U) &&
128 (Itineraries[ItinClassIndx].LastStage == ~0U));
127 return ((Itineraries[ItinClassIndx].FirstStage == UINT16_MAX) &&
128 (Itineraries[ItinClassIndx].LastStage == UINT16_MAX));
129129 }
130130
131131 /// \brief Return the first stage of the itinerary.
5757 /// Identify one of the processor resource kinds consumed by a particular
5858 /// scheduling class for the specified number of cycles.
5959 struct MCWriteProcResEntry {
60 unsigned ProcResourceIdx;
61 unsigned Cycles;
60 uint16_t ProcResourceIdx;
61 uint16_t Cycles;
6262
6363 bool operator==(const MCWriteProcResEntry &Other) const {
6464 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
7171 /// the WriteResources of this def. When the operand expands to a sequence of
7272 /// writes, this ID is the last write in the sequence.
7373 struct MCWriteLatencyEntry {
74 int Cycles;
75 unsigned WriteResourceID;
74 int16_t Cycles;
75 uint16_t WriteResourceID;
7676
7777 bool operator==(const MCWriteLatencyEntry &Other) const {
7878 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
103103 ///
104104 /// Defined as an aggregate struct for creating tables with initializer lists.
105105 struct MCSchedClassDesc {
106 static const unsigned short InvalidNumMicroOps = UINT16_MAX;
107 static const unsigned short VariantNumMicroOps = UINT16_MAX - 1;
106 static const unsigned short InvalidNumMicroOps = (1U << 14) - 1;
107 static const unsigned short VariantNumMicroOps = InvalidNumMicroOps - 1;
108108
109109 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
110110 const char* Name;
111111 #endif
112 unsigned short NumMicroOps;
113 bool BeginGroup;
114 bool EndGroup;
115 unsigned WriteProcResIdx; // First index into WriteProcResTable.
116 unsigned NumWriteProcResEntries;
117 unsigned WriteLatencyIdx; // First index into WriteLatencyTable.
118 unsigned NumWriteLatencyEntries;
119 unsigned ReadAdvanceIdx; // First index into ReadAdvanceTable.
120 unsigned NumReadAdvanceEntries;
112 uint16_t NumMicroOps : 14;
113 bool BeginGroup : 1;
114 bool EndGroup : 1;
115 uint16_t WriteProcResIdx; // First index into WriteProcResTable.
116 uint16_t NumWriteProcResEntries;
117 uint16_t WriteLatencyIdx; // First index into WriteLatencyTable.
118 uint16_t NumWriteLatencyEntries;
119 uint16_t ReadAdvanceIdx; // First index into ReadAdvanceTable.
120 uint16_t NumReadAdvanceEntries;
121121
122122 bool isValid() const {
123123 return NumMicroOps != InvalidNumMicroOps;
208208 return NoInformationAvailable;
209209
210210 // Compute output latency.
211 int Latency = 0;
211 int16_t Latency = 0;
212212 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
213213 DefIdx != DefEnd; ++DefIdx) {
214214 // Lookup the definition's write latency in SubtargetInfo.
443443 }
444444
445445 // Check to see if stage already exists and create if it doesn't
446 unsigned FindStage = 0;
446 uint16_t FindStage = 0;
447447 if (NStages > 0) {
448448 FindStage = ItinStageMap[ItinStageString];
449449 if (FindStage == 0) {
459459 }
460460
461461 // Check to see if operand cycle already exists and create if it doesn't
462 unsigned FindOperandCycle = 0;
462 uint16_t FindOperandCycle = 0;
463463 if (NOperandCycles > 0) {
464464 std::string ItinOperandString = ItinOperandCycleString+ItinBypassString;
465465 FindOperandCycle = ItinOperandMap[ItinOperandString];
481481 }
482482
483483 // Set up itinerary as location and location + stage count
484 int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
485 InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
486 FindOperandCycle,
487 FindOperandCycle + NOperandCycles };
484 int16_t NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
485 InstrItinerary Intinerary = {
486 NumUOps,
487 FindStage,
488 uint16_t(FindStage + NStages),
489 FindOperandCycle,
490 uint16_t(FindOperandCycle + NOperandCycles),
491 };
488492
489493 // Inject - empty slots will be 0, 0
490494 ItinList[SchedClassIdx] = Intinerary;
560564 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
561565 }
562566 // End processor itinerary table
563 OS << " { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n";
567 OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }"
568 "// end marker\n";
564569 OS << "};\n";
565570 }
566571 }