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The Mips specific function for instruction cache invalidation cannot be compiled on mips32r1 processors because it uses synci and rdhwr instructions which are supported only on mips32r2, so I replaced this function with the call to function cacheflush which works for both mips32r1 and mips32r2. Patch by Sasa Stankovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141564 91177308-0d34-0410-b5e6-96231b3b80d8 Bruno Cardoso Lopes 8 years ago
1 changed file(s) with 5 addition(s) and 34 deletion(s). Raw diff Collapse all Expand all
1515 #include "llvm/Support/Valgrind.h"
1616 #include "llvm/Config/config.h"
1717
18 #if defined(__mips__)
19 #include
20 #endif
21
1822 namespace llvm {
1923 using namespace sys;
2024 }
2832 #endif
2933
3034 extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
31
32 /// ClearMipsCache - Invalidates instruction cache for Mips. This assembly code
33 /// is copied from the MIPS32 Instruction Set Reference. Since the code ends
34 /// with the return instruction "jr.hb ra" (Jump Register with Hazard Barrier),
35 /// it must be implemented as a function (which is called from the
36 /// InvalidateInstructionCache function). It cannot be directly inlined into
37 /// InvalidateInstructionCache function, because in that case the epilog of
38 /// InvalidateInstructionCache will not be executed.
39 #if defined(__mips__)
40 extern "C" void ClearMipsCache(const void* Addr, size_t Size);
41 asm volatile(
42 ".text\n"
43 ".align 2\n"
44 ".globl ClearMipsCache\n"
45 "ClearMipsCache:\n"
46 ".set noreorder\n"
47 "beq $a1, $zero, 20f\n" /* If size==0, branch around */
48 "nop\n"
49 "addu $a1, $a0, $a1\n" /* Calculate end address + 1 */
50 "rdhwr $v0, $1\n" /* Get step size for SYNCI */
51 /* $1 is $HW_SYNCI_Step */
52 "beq $v0, $zero, 20f\n" /* If no caches require synchronization, */
53 /* branch around */
54 "nop\n"
55 "10: synci 0($a0)\n" /* Synchronize all caches around address */
56 "sltu $v1, $a0, $a1\n" /* Compare current with end address */
57 "bne $v1, $zero, 10b\n" /* Branch if more to do */
58 "addu $a0, $a0, $v0\n" /* Add step size in delay slot */
59 "sync\n" /* Clear memory hazards */
60 "20: jr.hb $ra\n" /* Return, clearing instruction hazards */
61 "nop\n"
62 );
63 #endif
6435
6536 /// InvalidateInstructionCache - Before the JIT can run a block of code
6637 /// that has been emitted it must invalidate the instruction cache on some
9970 char *End = Start + Len;
10071 __clear_cache(Start, End);
10172 # elif defined(__mips__)
102 ClearMipsCache(Addr, Len);
73 cacheflush((char*)Addr, Len, BCACHE);
10374 # endif
10475
10576 #endif // end apple