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[X86] DAGCombine should not assume arbitrary vector types are simple The X86-specific DAGCombine for stores should not assume vector types are always simple. This fixes PR23476. Differential Revision: http://reviews.llvm.org/D9659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237097 91177308-0d34-0410-b5e6-96231b3b80d8 Michael Kuperstein 5 years ago
2 changed file(s) with 12 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
2331423314 SDValue OldExtract = St->getOperand(1);
2331523315 SDValue ExtOp0 = OldExtract.getOperand(0);
2331623316 unsigned VecSize = ExtOp0.getValueSizeInBits();
23317 MVT VecVT = MVT::getVectorVT(MVT::f64, VecSize / 64);
23317 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
2331823318 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
2331923319 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
2332023320 BitCast, OldExtract.getOperand(1));
6262 ret void
6363 }
6464
65 ; PR23476
66 ; Handle extraction from a non-simple / pre-legalization type.
67
68 define void @PR23476(<5 x i64> %in, i64* %out, i32 %index) {
69 ; X32-LABEL: PR23476:
70 ; X32: movsd {{.*#+}} xmm0 = mem[0],zero
71 ; X32-NEXT: movsd %xmm0, (%eax)
72 %ext = extractelement <5 x i64> %in, i32 %index
73 store i64 %ext, i64* %out, align 8
74 ret void
75 }