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Prioritize smaller register classes for urgent evictions. It helps compile exotic inline asm. In the test case, normal GR32 virtual registers use up eax-edx so the final GR32_ABCD live range has no registers left. Since all the live ranges were tiny, we had no way of prioritizing the smaller register class. This patch allows tiny unspillable live ranges to be evicted by tiny unspillable live ranges from a smaller register class. <rdar://problem/11542429> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157715 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 7 years ago
2 changed file(s) with 16 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
557557 // Once a live range becomes small enough, it is urgent that we find a
558558 // register for it. This is indicated by an infinite spill weight. These
559559 // urgent live ranges get to evict almost anything.
560 bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable();
560 //
561 // Also allow urgent evictions of unspillable ranges from a strictly
562 // larger allocation order.
563 bool Urgent = !VirtReg.isSpillable() &&
564 (Intf->isSpillable() ||
565 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
566 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
561567 // Only evict older cascades or live ranges without a cascade.
562568 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
563569 if (Cascade <= IntfCascade) {
4242 %0 = tail call i8 asm sideeffect "xchg $0, $1", "=r,*m,0,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %p, i1 %desired) nounwind
4343 ret void
4444 }
45
46 ;
47 ; The constrained GR32_ABCD register class of the 'q' constraint requires
48 ; special handling after the preceding outputs used up eax-edx.
49 define void @constrain_abcd(i8* %h) nounwind ssp {
50 entry:
51 %0 = call { i32, i32, i32, i32, i32 } asm sideeffect "", "=&r,=&r,=&r,=&r,=&q,r,~{ecx},~{memory},~{dirflag},~{fpsr},~{flags}"(i8* %h) nounwind
52 ret void
53 }