llvm.org GIT mirror llvm / 9c3636f
[X86][BMI] Pull out schedule classes from bmi_andn<> and bmi_bls<> Stop hardwiring classes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375470 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 1 year, 1 month ago
2 changed file(s) with 15 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
12701270 // ANDN Instruction
12711271 //
12721272 multiclass bmi_andn
1273 PatFrag ld_frag> {
1273 PatFrag ld_frag, X86FoldableSchedWrite sched> {
12741274 def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
12751275 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
12761276 [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))]>,
1277 Sched<[WriteALU]>;
1277 Sched<[sched]>;
12781278 def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
12791279 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
12801280 [(set RC:$dst, EFLAGS,
12811281 (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))]>,
1282 Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>;
1282 Sched<[sched.Folded, sched.ReadAfterFold]>;
12831283 }
12841284
12851285 // Complexity is reduced to give and with immediate a chance to match first.
12861286 let Predicates = [HasBMI], Defs = [EFLAGS], AddedComplexity = -6 in {
1287 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8PS, VEX_4V;
1288 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8PS, VEX_4V, VEX_W;
1287 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32, WriteALU>, T8PS, VEX_4V;
1288 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64, WriteALU>, T8PS, VEX_4V, VEX_W;
12891289 }
12901290
12911291 let Predicates = [HasBMI], AddedComplexity = -6 in {
24172417 }
24182418
24192419 multiclass bmi_bls
2420 RegisterClass RC, X86MemOperand x86memop> {
2420 RegisterClass RC, X86MemOperand x86memop,
2421 X86FoldableSchedWrite sched> {
24212422 let hasSideEffects = 0 in {
24222423 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
24232424 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
2424 T8PS, VEX_4V, Sched<[WriteBLS]>;
2425 T8PS, VEX_4V, Sched<[sched]>;
24252426 let mayLoad = 1 in
24262427 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
24272428 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>,
2428 T8PS, VEX_4V, Sched<[WriteBLS.Folded]>;
2429 T8PS, VEX_4V, Sched<[sched.Folded]>;
24292430 }
24302431 }
24312432
24322433 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2433 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2434 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2435 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2436 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2437 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2438 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2434 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS>;
2435 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS>, VEX_W;
2436 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS>;
2437 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS>, VEX_W;
2438 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, WriteBLS>;
2439 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS>, VEX_W;
24392440 }
24402441
24412442 //===----------------------------------------------------------------------===//