llvm.org GIT mirror llvm / 9c34723
[GlobalISel][X86] support G_FPEXT operation. Summary: Support G_FPEXT operation. Selection done via TableGen'erated code. Reviewers: zvi, guyblank, aymanmus, m_zuckerman Reviewed By: zvi Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34816 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313135 91177308-0d34-0410-b5e6-96231b3b80d8 Igor Breger 2 years ago
6 changed file(s) with 129 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
169169 if (!Subtarget.hasSSE2())
170170 return;
171171
172 const LLT s32 = LLT::scalar(32);
172173 const LLT s64 = LLT::scalar(64);
173174 const LLT v16s8 = LLT::vector(16, 8);
174175 const LLT v8s16 = LLT::vector(8, 16);
184185 setAction({BinOp, Ty}, Legal);
185186
186187 setAction({G_MUL, v8s16}, Legal);
188
189 setAction({G_FPEXT, s64}, Legal);
190 setAction({G_FPEXT, 1, s32}, Legal);
187191 }
188192
189193 void X86LegalizerInfo::setLegalizerInfoSSE41() {
181181 }
182182
183183 unsigned NumOperands = MI.getNumOperands();
184
185 // Track the bank of each register, use NotFP mapping (all scalars in GPRs)
186184 SmallVector OpRegBankIdx(NumOperands);
187 getInstrPartialMappingIdxs(MI, MRI, /* isFP */ false, OpRegBankIdx);
185
186 switch (Opc) {
187 case TargetOpcode::G_FPEXT:
188 // Instruction having only floating-point operands (all scalars in VECRReg)
189 getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx);
190 break;
191 default:
192 // Track the bank of each register, use NotFP mapping (all scalars in GPRs)
193 getInstrPartialMappingIdxs(MI, MRI, /* isFP */ false, OpRegBankIdx);
194 break;
195 }
188196
189197 // Finally construct the computed mapping.
190198 SmallVector OpdsMapping(NumOperands);
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=CHECK
2
3 define double @test(float %a) {
4 ; CHECK-LABEL: test:
5 ; CHECK: # BB#0: # %entry
6 ; CHECK-NEXT: cvtss2sd %xmm0, %xmm0
7 ; CHECK-NEXT: retq
8 entry:
9 %conv = fpext float %a to double
10 ret double %conv
11 }
0 # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL
1 --- |
2
3 define double @test(float %a) {
4 entry:
5 %conv = fpext float %a to double
6 ret double %conv
7 }
8
9 ...
10 ---
11 name: test
12 # ALL-LABEL: name: test
13 alignment: 4
14 legalized: false
15 regBankSelected: false
16 registers:
17 - { id: 0, class: _, preferred-register: '' }
18 - { id: 1, class: _, preferred-register: '' }
19 # ALL: %0(s32) = COPY %xmm0
20 # ALL-NEXT: %1(s64) = G_FPEXT %0(s32)
21 # ALL-NEXT: %xmm0 = COPY %1(s64)
22 # ALL-NEXT: RET 0, implicit %xmm0
23 body: |
24 bb.1.entry:
25 liveins: %xmm0
26
27 %0(s32) = COPY %xmm0
28 %1(s64) = G_FPEXT %0(s32)
29 %xmm0 = COPY %1(s64)
30 RET 0, implicit %xmm0
31
32 ...
230230 ret float %cond
231231 }
232232
233
233 define double @test_fpext(float %a) {
234 entry:
235 %conv = fpext float %a to double
236 ret double %conv
237 }
238
234239 ...
235240 ---
236241 name: test_add_i8
13831388 RET 0, implicit %xmm0
13841389
13851390 ...
1391 ---
1392 name: test_fpext
1393 # CHECK-LABEL: name: test_fpext
1394 alignment: 4
1395 legalized: true
1396 regBankSelected: false
1397 # CHECK: registers:
1398 # CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
1399 # CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
1400 registers:
1401 - { id: 0, class: _, preferred-register: '' }
1402 - { id: 1, class: _, preferred-register: '' }
1403 body: |
1404 bb.1.entry:
1405 liveins: %xmm0
1406
1407 %0(s32) = COPY %xmm0
1408 %1(s64) = G_FPEXT %0(s32)
1409 %xmm0 = COPY %1(s64)
1410 RET 0, implicit %xmm0
1411
1412 ...
1413
0 # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
1 --- |
2
3 define double @test(float %a) {
4 entry:
5 %conv = fpext float %a to double
6 ret double %conv
7 }
8
9 ...
10 ---
11 name: test
12 # ALL-LABEL: name: test
13 alignment: 4
14 legalized: true
15 regBankSelected: true
16 # ALL: registers:
17 # ALL-NEXT: - { id: 0, class: fr32, preferred-register: '' }
18 # ALL-NEXT: - { id: 1, class: fr64, preferred-register: '' }
19 registers:
20 - { id: 0, class: vecr, preferred-register: '' }
21 - { id: 1, class: vecr, preferred-register: '' }
22 liveins:
23 fixedStack:
24 stack:
25 constants:
26 # ALL: %0 = COPY %xmm0
27 # ALL-NEXT: %1 = CVTSS2SDrr %0
28 # ALL-NEXT: %xmm0 = COPY %1
29 # ALL-NEXT: RET 0, implicit %xmm0
30 body: |
31 bb.1.entry:
32 liveins: %xmm0
33
34 %0(s32) = COPY %xmm0
35 %1(s64) = G_FPEXT %0(s32)
36 %xmm0 = COPY %1(s64)
37 RET 0, implicit %xmm0
38
39 ...