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R600/SI: remove image sample writemask Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179164 91177308-0d34-0410-b5e6-96231b3b80d8 Christian Konig 7 years ago
3 changed file(s) with 30 addition(s) and 31 deletion(s). Raw diff Collapse all Expand all
12181218
12191219 /* int_SI_sample for simple 1D texture lookup */
12201220 def : Pat <
1221 (int_SI_sample imm:$writemask, VReg_32:$addr,
1222 SReg_256:$rsrc, SReg_128:$sampler, imm),
1223 (IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_32:$addr,
1221 (int_SI_sample VReg_32:$addr, SReg_256:$rsrc, SReg_128:$sampler, imm),
1222 (IMAGE_SAMPLE 0xf, 0, 0, 0, 0, 0, 0, 0, VReg_32:$addr,
12241223 SReg_256:$rsrc, SReg_128:$sampler)
12251224 >;
12261225
12271226 class SamplePattern
12281227 ValueType addr_type> : Pat <
1229 (name imm:$writemask, (addr_type addr_class:$addr),
1228 (name (addr_type addr_class:$addr),
12301229 SReg_256:$rsrc, SReg_128:$sampler, imm),
1231 (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr,
1230 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr,
12321231 SReg_256:$rsrc, SReg_128:$sampler)
12331232 >;
12341233
12351234 class SampleRectPattern
12361235 ValueType addr_type> : Pat <
1237 (name imm:$writemask, (addr_type addr_class:$addr),
1236 (name (addr_type addr_class:$addr),
12381237 SReg_256:$rsrc, SReg_128:$sampler, TEX_RECT),
1239 (opcode imm:$writemask, 1, 0, 0, 0, 0, 0, 0, addr_class:$addr,
1238 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, addr_class:$addr,
12401239 SReg_256:$rsrc, SReg_128:$sampler)
12411240 >;
12421241
12431242 class SampleArrayPattern
12441243 ValueType addr_type> : Pat <
1245 (name imm:$writemask, (addr_type addr_class:$addr),
1244 (name (addr_type addr_class:$addr),
12461245 SReg_256:$rsrc, SReg_128:$sampler, TEX_ARRAY),
1247 (opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr,
1246 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr,
12481247 SReg_256:$rsrc, SReg_128:$sampler)
12491248 >;
12501249
12511250 class SampleShadowPattern
12521251 RegisterClass addr_class, ValueType addr_type> : Pat <
1253 (name imm:$writemask, (addr_type addr_class:$addr),
1252 (name (addr_type addr_class:$addr),
12541253 SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW),
1255 (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr,
1254 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr,
12561255 SReg_256:$rsrc, SReg_128:$sampler)
12571256 >;
12581257
12591258 class SampleShadowArrayPattern
12601259 RegisterClass addr_class, ValueType addr_type> : Pat <
1261 (name imm:$writemask, (addr_type addr_class:$addr),
1260 (name (addr_type addr_class:$addr),
12621261 SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW_ARRAY),
1263 (opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr,
1262 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr,
12641263 SReg_256:$rsrc, SReg_128:$sampler)
12651264 >;
12661265
1818 def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
1919 def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_v16i8_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;
2020
21 class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_anyvector_ty, llvm_v32i8_ty, llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
21 class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
2222
2323 def int_SI_sample : Sample;
2424 def int_SI_sampleb : Sample;
3333 %v14 = insertelement <4 x i32> undef, i32 %a4, i32 1
3434 %v15 = insertelement <4 x i32> undef, i32 %a4, i32 2
3535 %v16 = insertelement <4 x i32> undef, i32 %a4, i32 3
36 %res1 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v1,
36 %res1 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v1,
3737 <8 x i32> undef, <4 x i32> undef, i32 1)
38 %res2 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v2,
38 %res2 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v2,
3939 <8 x i32> undef, <4 x i32> undef, i32 2)
40 %res3 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v3,
40 %res3 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v3,
4141 <8 x i32> undef, <4 x i32> undef, i32 3)
42 %res4 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v4,
42 %res4 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v4,
4343 <8 x i32> undef, <4 x i32> undef, i32 4)
44 %res5 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v5,
44 %res5 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v5,
4545 <8 x i32> undef, <4 x i32> undef, i32 5)
46 %res6 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v6,
46 %res6 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v6,
4747 <8 x i32> undef, <4 x i32> undef, i32 6)
48 %res7 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v7,
48 %res7 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v7,
4949 <8 x i32> undef, <4 x i32> undef, i32 7)
50 %res8 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v8,
50 %res8 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v8,
5151 <8 x i32> undef, <4 x i32> undef, i32 8)
52 %res9 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v9,
52 %res9 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v9,
5353 <8 x i32> undef, <4 x i32> undef, i32 9)
54 %res10 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v10,
54 %res10 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v10,
5555 <8 x i32> undef, <4 x i32> undef, i32 10)
56 %res11 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v11,
56 %res11 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v11,
5757 <8 x i32> undef, <4 x i32> undef, i32 11)
58 %res12 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v12,
58 %res12 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v12,
5959 <8 x i32> undef, <4 x i32> undef, i32 12)
60 %res13 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v13,
60 %res13 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v13,
6161 <8 x i32> undef, <4 x i32> undef, i32 13)
62 %res14 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v14,
62 %res14 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v14,
6363 <8 x i32> undef, <4 x i32> undef, i32 14)
64 %res15 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v15,
64 %res15 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v15,
6565 <8 x i32> undef, <4 x i32> undef, i32 15)
66 %res16 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v16,
66 %res16 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v16,
6767 <8 x i32> undef, <4 x i32> undef, i32 16)
6868 %e1 = extractelement <4 x float> %res1, i32 0
6969 %e2 = extractelement <4 x float> %res2, i32 0
100100 ret void
101101 }
102102
103 declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone
103 declare <4 x float> @llvm.SI.sample.(<4 x i32>, <8 x i32>, <4 x i32>, i32) readnone
104104
105105 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)