llvm.org GIT mirror llvm / 9bfd5f3
introduce a new OpKind abstraction which wraps up operand flavors in a tidy little wrapper. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129680 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 9 years ago
1 changed file(s) with 48 addition(s) and 22 deletion(s). Raw diff Collapse all Expand all
3939 /// types. It has utility methods for emitting text based on the operands.
4040 ///
4141 struct OperandsSignature {
42 SmallVector Operands;
42 class OpKind {
43 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
44 char Repr;
45 public:
46
47 OpKind() : Repr(OK_Invalid) {}
48
49 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
50
51 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; }
52 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; }
53 static OpKind getImm() { OpKind K; K.Repr = OK_Imm; return K; }
54
55 bool isReg() const { return Repr == OK_Reg; }
56 bool isFP() const { return Repr == OK_FP; }
57 bool isImm() const { return Repr == OK_Imm; }
58
59 void printManglingSuffix(raw_ostream &OS) const {
60 if (isReg())
61 OS << 'r';
62 else if (isFP())
63 OS << 'f';
64 else
65 OS << 'i';
66 }
67 };
68
69 SmallVector Operands;
4370
4471 bool operator<(const OperandsSignature &O) const {
4572 return Operands < O.Operands;
5683
5784 if (!InstPatNode->isLeaf()) {
5885 if (InstPatNode->getOperator()->getName() == "imm") {
59 Operands.push_back('i');
86 Operands.push_back(OpKind::getImm());
6087 return true;
6188 }
6289 if (InstPatNode->getOperator()->getName() == "fpimm") {
63 Operands.push_back('f');
90 Operands.push_back(OpKind::getFP());
6491 return true;
6592 }
6693 }
77104
78105 if (!Op->isLeaf()) {
79106 if (Op->getOperator()->getName() == "imm") {
80 Operands.push_back('i');
107 Operands.push_back(OpKind::getImm());
81108 continue;
82109 }
83110 if (Op->getOperator()->getName() == "fpimm") {
84 Operands.push_back('f');
111 Operands.push_back(OpKind::getFP());
85112 continue;
86113 }
87114 // For now, ignore other non-leaf nodes.
100127 if (!OpDI)
101128 return false;
102129 Record *OpLeafRec = OpDI->getDef();
130
103131 // For now, the only other thing we accept is register operands.
104
105132 const CodeGenRegisterClass *RC = 0;
106133 if (OpLeafRec->isSubClassOf("RegisterClass"))
107134 RC = &Target.getRegisterClass(OpLeafRec);
121148 return false;
122149 } else
123150 DstRC = RC;
124 Operands.push_back('r');
151 Operands.push_back(OpKind::getReg());
125152 }
126153 return true;
127154 }
128155
129156 void PrintParameters(raw_ostream &OS) const {
130157 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
131 if (Operands[i] == 'r') {
158 if (Operands[i].isReg()) {
132159 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
133 } else if (Operands[i] == 'i') {
160 } else if (Operands[i].isImm()) {
134161 OS << "uint64_t imm" << i;
135 } else if (Operands[i] == 'f') {
162 } else if (Operands[i].isFP()) {
136163 OS << "ConstantFP *f" << i;
137164 } else {
138165 assert("Unknown operand kind!");
144171 }
145172
146173 void PrintArguments(raw_ostream &OS,
147 const std::vector& PR) const {
174 const std::vector &PR) const {
148175 assert(PR.size() == Operands.size());
149176 bool PrintedArg = false;
150177 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
154181
155182 if (PrintedArg)
156183 OS << ", ";
157 if (Operands[i] == 'r') {
184 if (Operands[i].isReg()) {
158185 OS << "Op" << i << ", Op" << i << "IsKill";
159186 PrintedArg = true;
160 } else if (Operands[i] == 'i') {
187 } else if (Operands[i].isImm()) {
161188 OS << "imm" << i;
162189 PrintedArg = true;
163 } else if (Operands[i] == 'f') {
190 } else if (Operands[i].isFP()) {
164191 OS << "f" << i;
165192 PrintedArg = true;
166193 } else {
172199
173200 void PrintArguments(raw_ostream &OS) const {
174201 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
175 if (Operands[i] == 'r') {
202 if (Operands[i].isReg()) {
176203 OS << "Op" << i << ", Op" << i << "IsKill";
177 } else if (Operands[i] == 'i') {
204 } else if (Operands[i].isImm()) {
178205 OS << "imm" << i;
179 } else if (Operands[i] == 'f') {
206 } else if (Operands[i].isFP()) {
180207 OS << "f" << i;
181208 } else {
182209 assert("Unknown operand kind!");
189216
190217
191218 void PrintManglingSuffix(raw_ostream &OS,
192 const std::vector& PR) const {
219 const std::vector &PR) const {
193220 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
194221 if (PR[i] != "")
195222 // Implicit physical register operand. e.g. Instruction::Mul expect to
198225 // like a binary instruction except for the very inner FastEmitInst_*
199226 // call.
200227 continue;
201 OS << Operands[i];
228 Operands[i].printManglingSuffix(OS);
202229 }
203230 }
204231
205232 void PrintManglingSuffix(raw_ostream &OS) const {
206 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
207 OS << Operands[i];
208 }
233 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
234 Operands[i].printManglingSuffix(OS);
209235 }
210236 };
211237