llvm.org GIT mirror llvm / 9bf7351
Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225160 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 5 years ago
16 changed file(s) with 38 addition(s) and 56 deletion(s). Raw diff Collapse all Expand all
39693969 isa(Val) ||
39703970 canCauseUndefinedBehavior(ToBePromoted, U.getOperandNo()));
39713971 } else
3972 assert(0 && "Did you modified shouldPromote and forgot to update this?");
3972 llvm_unreachable("Did you modified shouldPromote and forgot to update "
3973 "this?");
39733974 ToBePromoted->setOperand(U.getOperandNo(), NewVal);
39743975 }
39753976 Transition->removeFromParent();
116116 if (!isa(C))
117117 C->replaceUsesOfWithOnConstant(GV, V, U);
118118 } else {
119 assert(false && "The Use of a Function symbol is neither an instruction nor"
120 " a constant");
119 llvm_unreachable("The Use of a Function symbol is neither an instruction "
120 "nor a constant");
121121 }
122122
123123 return true;
97349734 } else if (ConstantFPSDNode *C = dyn_cast(Val)) {
97359735 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
97369736 } else {
9737 assert(false && "Invalid constant element type");
9737 llvm_unreachable("Invalid constant element type");
97389738 }
97399739 }
97409740
5050 /// getShiftName - Get the string encoding for the shift type.
5151 static inline const char *getShiftExtendName(AArch64_AM::ShiftExtendType ST) {
5252 switch (ST) {
53 default: assert(false && "unhandled shift type!");
53 default: llvm_unreachable("unhandled shift type!");
5454 case AArch64_AM::LSL: return "lsl";
5555 case AArch64_AM::LSR: return "lsr";
5656 case AArch64_AM::ASR: return "asr";
131131 int64_t SignedValue = static_cast(Value);
132132 switch (Kind) {
133133 default:
134 assert(false && "Unknown fixup kind!");
134 llvm_unreachable("Unknown fixup kind!");
135135 case AArch64::fixup_aarch64_pcrel_adr_imm21:
136136 if (SignedValue > 2097151 || SignedValue < -2097152)
137137 report_fatal_error("fixup value out of range");
238238
239239 void AArch64AsmBackend::relaxInstruction(const MCInst &Inst,
240240 MCInst &Res) const {
241 assert(false && "AArch64AsmBackend::relaxInstruction() unimplemented");
241 llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
242242 }
243243
244244 bool AArch64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
436436 return 3;
437437 }
438438
439 assert(false && "Invalid value for vector shift amount!");
440 return 0;
439 llvm_unreachable("Invalid value for vector shift amount!");
441440 }
442441
443442 uint32_t
890890 continue;
891891 }
892892 else {
893 assert(false && "Unexpected operand type");
893 llvm_unreachable("Unexpected operand type");
894894 }
895895 }
896896 }
14111411 bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
14121412 SmallVectorImpl &Instructions) {
14131413 switch (Inst.getOpcode()) {
1414 default:
1415 assert(0 && "unimplemented expansion");
1416 return true;
1414 default: llvm_unreachable("unimplemented expansion");
14171415 case Mips::LoadImm32Reg:
14181416 return expandLoadImm(Inst, IDLoc, Instructions);
14191417 case Mips::LoadImm64Reg:
133133 } else if (const MipsMCExpr *ME = dyn_cast(Expr)) {
134134 ME->print(OS);
135135 return;
136 } else if (!(SRE = dyn_cast(Expr)))
137 assert(false && "Unexpected MCExpr type.");
136 } else
137 SRE = cast(Expr);
138138
139139 MCSymbolRefExpr::VariantKind Kind = SRE->getKind();
140140
143143 /// opcode, e.g. turning BEQ to BNE.
144144 unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const {
145145 switch (Opc) {
146 default: llvm_unreachable("Illegal opcode!");
147146 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
148147 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
149148 case Mips::BeqzRxImm16: return Mips::BnezRxImm16;
165164 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
166165 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
167166 }
168 assert(false && "Implement this function.");
169 return 0;
167 llvm_unreachable("Illegal opcode!");
170168 }
171169
172170 static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
287285 void Mips16InstrInfo::adjustStackPtrBigUnrestricted(
288286 unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
289287 MachineBasicBlock::iterator I) const {
290 assert(false && "adjust stack pointer amount exceeded");
288 llvm_unreachable("adjust stack pointer amount exceeded");
291289 }
292290
293291 /// Adjust SP by Amount bytes.
109109 return MO.getMBB();
110110 }
111111
112 assert(false && "This instruction does not have an MBB operand.");
113 return nullptr;
112 llvm_unreachable("This instruction does not have an MBB operand.");
114113 }
115114
116115 // Traverse the list of instructions backwards until a non-debug instruction is
373373 } else if (isa(Ty)) {
374374 O << ".param .b" << TLI->getPointerTy().getSizeInBits()
375375 << " func_retval0";
376 } else {
377 if ((Ty->getTypeID() == Type::StructTyID) || isa(Ty)) {
378 unsigned totalsz = TD->getTypeAllocSize(Ty);
379 unsigned retAlignment = 0;
380 if (!llvm::getAlign(*F, 0, retAlignment))
381 retAlignment = TD->getABITypeAlignment(Ty);
382 O << ".param .align " << retAlignment << " .b8 func_retval0[" << totalsz
383 << "]";
384 } else
385 assert(false && "Unknown return type");
386 }
376 } else if ((Ty->getTypeID() == Type::StructTyID) || isa(Ty)) {
377 unsigned totalsz = TD->getTypeAllocSize(Ty);
378 unsigned retAlignment = 0;
379 if (!llvm::getAlign(*F, 0, retAlignment))
380 retAlignment = TD->getABITypeAlignment(Ty);
381 O << ".param .align " << retAlignment << " .b8 func_retval0[" << totalsz
382 << "]";
383 } else
384 llvm_unreachable("Unknown return type");
387385 } else {
388386 SmallVector vtparts;
389387 ComputeValueVTs(*TLI, Ty, vtparts);
904904 O << ".param .b" << size << " _";
905905 } else if (isa(retTy)) {
906906 O << ".param .b" << getPointerTy().getSizeInBits() << " _";
907 } else if ((retTy->getTypeID() == Type::StructTyID) ||
908 isa(retTy)) {
909 O << ".param .align "
910 << retAlignment
911 << " .b8 _["
912 << getDataLayout()->getTypeAllocSize(retTy) << "]";
907913 } else {
908 if((retTy->getTypeID() == Type::StructTyID) ||
909 isa(retTy)) {
910 O << ".param .align "
911 << retAlignment
912 << " .b8 _["
913 << getDataLayout()->getTypeAllocSize(retTy) << "]";
914 } else {
915 assert(false && "Unknown return type");
916 }
914 llvm_unreachable("Unknown return type");
917915 }
918916 O << ") ";
919917 }
665665 .addImm(7));
666666
667667 switch (AccessSize) {
668 default: llvm_unreachable("Incorrect access size");
668669 case 1:
669670 break;
670671 case 2: {
680681 .addReg(ScratchRegI32)
681682 .addReg(ScratchRegI32)
682683 .addImm(3));
683 break;
684 default:
685 assert(false && "Incorrect access size");
686684 break;
687685 }
688686
714712 {
715713 MCInst Inst;
716714 switch (AccessSize) {
715 default: llvm_unreachable("Incorrect access size");
717716 case 8:
718717 Inst.setOpcode(X86::CMP8mi);
719718 break;
720719 case 16:
721720 Inst.setOpcode(X86::CMP16mi);
722 break;
723 default:
724 assert(false && "Incorrect access size");
725721 break;
726722 }
727723 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
940936 .addImm(7));
941937
942938 switch (AccessSize) {
939 default: llvm_unreachable("Incorrect access size");
943940 case 1:
944941 break;
945942 case 2: {
955952 .addReg(ScratchRegI32)
956953 .addReg(ScratchRegI32)
957954 .addImm(3));
958 break;
959 default:
960 assert(false && "Incorrect access size");
961955 break;
962956 }
963957
989983 {
990984 MCInst Inst;
991985 switch (AccessSize) {
986 default: llvm_unreachable("Incorrect access size");
992987 case 8:
993988 Inst.setOpcode(X86::CMP8mi);
994989 break;
995990 case 16:
996991 Inst.setOpcode(X86::CMP16mi);
997 break;
998 default:
999 assert(false && "Incorrect access size");
1000992 break;
1001993 }
1002994 const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
282282 return;
283283 int addrr_opcode, addri_opcode;
284284 switch (opcode) {
285 default: llvm_unreachable("Unexpected LEA instruction");
285286 case X86::LEA16r:
286287 addrr_opcode = X86::ADD16rr;
287288 addri_opcode = X86::ADD16ri;
295296 addrr_opcode = X86::ADD64rr;
296297 addri_opcode = X86::ADD64ri32;
297298 break;
298 default:
299 assert(false && "Unexpected LEA instruction");
300299 }
301300 DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
302301 DEBUG(dbgs() << "FixLEA: Replaced by: ";);
421421 static ConstantInt *createOrdering(IRBuilder<> *IRB, AtomicOrdering ord) {
422422 uint32_t v = 0;
423423 switch (ord) {
424 case NotAtomic: assert(false);
424 case NotAtomic: llvm_unreachable("unexpected atomic ordering!");
425425 case Unordered: // Fall-through.
426426 case Monotonic: v = 0; break;
427427 // case Consume: v = 1; break; // Not specified yet.