llvm.org GIT mirror llvm / 9bf45d0
Let the inline asm 'q' constraint match float, and on 64-bit double too. Fixes PR9602! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134665 91177308-0d34-0410-b5e6-96231b3b80d8 Nick Lewycky 8 years ago
2 changed file(s) with 16 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
1289012890 // in the normal allocation?
1289112891 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
1289212892 if (Subtarget->is64Bit()) {
12893 if (VT == MVT::i32)
12893 if (VT == MVT::i32 || VT == MVT::f32)
1289412894 return std::make_pair(0U, X86::GR32RegisterClass);
1289512895 else if (VT == MVT::i16)
1289612896 return std::make_pair(0U, X86::GR16RegisterClass);
1289712897 else if (VT == MVT::i8)
1289812898 return std::make_pair(0U, X86::GR8RegisterClass);
12899 else if (VT == MVT::i64)
12899 else if (VT == MVT::i64 || VT == MVT::f64)
1290012900 return std::make_pair(0U, X86::GR64RegisterClass);
1290112901 break;
1290212902 }
1290312903 // 32-bit fallthrough
1290412904 case 'Q': // Q_REGS
12905 if (VT == MVT::i32)
12905 if (VT == MVT::i32 || VT == MVT::f32)
1290612906 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
1290712907 else if (VT == MVT::i16)
1290812908 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
22
33 %0 = type { i64, i64, i64, i64, i64 } ; type %0
44
5 define void @t() nounwind {
5 define void @test1() nounwind {
66 entry:
77 %asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0]
88 ret void
99 }
10
11 ; PR9602
12 define void @test2(float %tmp) nounwind {
13 call void asm sideeffect "$0", "q"(float %tmp) nounwind
14 call void asm sideeffect "$0", "Q"(float %tmp) nounwind
15 ret void
16 }
17
18 define void @test3(double %tmp) nounwind {
19 call void asm sideeffect "$0", "q"(double %tmp) nounwind
20 ret void
21 }