llvm.org GIT mirror llvm / 9bb7f7c
reverting r209132 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209139 91177308-0d34-0410-b5e6-96231b3b80d8 Jyotsna Verma 6 years ago
4 changed file(s) with 250 addition(s) and 703 deletion(s). Raw diff Collapse all Expand all
1212 // March 4, 2008
1313 //===----------------------------------------------------------------------===//
1414
15 // MTYPE / MPYS / Scalar 16x16 multiply signed/unsigned.
16 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
17
18 // M2_mpyu_lh_s1:
19 let hasNewValue = 1, opNewValue = 0 in
20 class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd,
21 bit hasShift, bit isUnsigned, Intrinsic IntID >
22 : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
23 "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l")
24 #", $Rt."#!if(LHbits{0},"h)","l)")
25 #!if(hasShift,":<<1","")
26 #!if(isRnd,":rnd","")
27 #!if(isSat,":sat",""),
28 [(set IntRegs:$Rd, (IntID IntRegs:$Rs, IntRegs:$Rt))], "", M_tc_3x_SLOT23 > {
29 bits<5> Rd;
30 bits<5> Rs;
31 bits<5> Rt;
32
33 let IClass = 0b1110;
34
35 let Inst{27-24} = 0b1100;
36 let Inst{23} = hasShift;
37 let Inst{22} = isUnsigned;
38 let Inst{21} = isRnd;
39 let Inst{7} = isSat;
40 let Inst{6-5} = LHbits;
41 let Inst{4-0} = Rd;
42 let Inst{20-16} = Rs;
43 let Inst{12-8} = Rt;
44 }
45
46 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]
47 def HEXAGON_M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0, int_hexagon_M2_mpy_ll_s1>;
48 def HEXAGON_M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0, int_hexagon_M2_mpy_ll_s0>;
49 def HEXAGON_M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0, int_hexagon_M2_mpy_lh_s1>;
50 def HEXAGON_M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0, int_hexagon_M2_mpy_lh_s0>;
51 def HEXAGON_M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0, int_hexagon_M2_mpy_hl_s1>;
52 def HEXAGON_M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0, int_hexagon_M2_mpy_hl_s0>;
53 def HEXAGON_M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0, int_hexagon_M2_mpy_hh_s1>;
54 def HEXAGON_M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0, int_hexagon_M2_mpy_hh_s0>;
55
56 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1]
57 def HEXAGON_M2_mpyu_ll_s1:
58 T_M2_mpy<0b00, 0, 0, 1, 1, int_hexagon_M2_mpyu_ll_s1>;
59 def HEXAGON_M2_mpyu_ll_s0:
60 T_M2_mpy<0b00, 0, 0, 0, 1, int_hexagon_M2_mpyu_ll_s0>;
61 def HEXAGON_M2_mpyu_lh_s1:
62 T_M2_mpy<0b01, 0, 0, 1, 1, int_hexagon_M2_mpyu_lh_s1>;
63 def HEXAGON_M2_mpyu_lh_s0:
64 T_M2_mpy<0b01, 0, 0, 0, 1, int_hexagon_M2_mpyu_lh_s0>;
65 def HEXAGON_M2_mpyu_hl_s1:
66 T_M2_mpy<0b10, 0, 0, 1, 1, int_hexagon_M2_mpyu_hl_s1>;
67 def HEXAGON_M2_mpyu_hl_s0:
68 T_M2_mpy<0b10, 0, 0, 0, 1, int_hexagon_M2_mpyu_hl_s0>;
69 def HEXAGON_M2_mpyu_hh_s1:
70 T_M2_mpy<0b11, 0, 0, 1, 1, int_hexagon_M2_mpyu_hh_s1>;
71 def HEXAGON_M2_mpyu_hh_s0:
72 T_M2_mpy<0b11, 0, 0, 0, 1, int_hexagon_M2_mpyu_hh_s0>;
73
74 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat]
75 let Defs = [USR] in {
76 def HEXAGON_M2_mpy_sat_ll_s1 :
77 T_M2_mpy <0b00, 1, 0, 1, 0, int_hexagon_M2_mpy_sat_ll_s1>;
78 def HEXAGON_M2_mpy_sat_ll_s0 :
79 T_M2_mpy <0b00, 1, 0, 0, 0, int_hexagon_M2_mpy_sat_ll_s0>;
80 def HEXAGON_M2_mpy_sat_lh_s1 :
81 T_M2_mpy <0b01, 1, 0, 1, 0, int_hexagon_M2_mpy_sat_lh_s1>;
82 def HEXAGON_M2_mpy_sat_lh_s0 :
83 T_M2_mpy <0b01, 1, 0, 0, 0, int_hexagon_M2_mpy_sat_lh_s0>;
84 def HEXAGON_M2_mpy_sat_hl_s1 :
85 T_M2_mpy <0b10, 1, 0, 1, 0, int_hexagon_M2_mpy_sat_hl_s1>;
86 def HEXAGON_M2_mpy_sat_hl_s0 :
87 T_M2_mpy <0b10, 1, 0, 0, 0, int_hexagon_M2_mpy_sat_hl_s0>;
88 def HEXAGON_M2_mpy_sat_hh_s1 :
89 T_M2_mpy <0b11, 1, 0, 1, 0, int_hexagon_M2_mpy_sat_hh_s1>;
90 def HEXAGON_M2_mpy_sat_hh_s0 :
91 T_M2_mpy <0b11, 1, 0, 0, 0, int_hexagon_M2_mpy_sat_hh_s0>;
92 }
93
94 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd]
95 def HEXAGON_M2_mpy_rnd_ll_s1 :
96 T_M2_mpy <0b00, 0, 1, 1, 0, int_hexagon_M2_mpy_rnd_ll_s1>;
97 def HEXAGON_M2_mpy_rnd_ll_s0 :
98 T_M2_mpy <0b00, 0, 1, 0, 0, int_hexagon_M2_mpy_rnd_ll_s0>;
99 def HEXAGON_M2_mpy_rnd_lh_s1 :
100 T_M2_mpy <0b01, 0, 1, 1, 0, int_hexagon_M2_mpy_rnd_lh_s1>;
101 def HEXAGON_M2_mpy_rnd_lh_s0 :
102 T_M2_mpy <0b01, 0, 1, 0, 0, int_hexagon_M2_mpy_rnd_lh_s0>;
103 def HEXAGON_M2_mpy_rnd_hl_s1 :
104 T_M2_mpy <0b10, 0, 1, 1, 0, int_hexagon_M2_mpy_rnd_hl_s1>;
105 def HEXAGON_M2_mpy_rnd_hl_s0 :
106 T_M2_mpy <0b10, 0, 1, 0, 0, int_hexagon_M2_mpy_rnd_hl_s0>;
107 def HEXAGON_M2_mpy_rnd_hh_s1 :
108 T_M2_mpy <0b11, 0, 1, 1, 0, int_hexagon_M2_mpy_rnd_hh_s1>;
109 def HEXAGON_M2_mpy_rnd_hh_s0 :
110 T_M2_mpy <0b11, 0, 1, 0, 0, int_hexagon_M2_mpy_rnd_hh_s0>;
111
112 //Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
113 let Defs = [USR] in {
114 def HEXAGON_M2_mpy_sat_rnd_ll_s1 :
115 T_M2_mpy <0b00, 1, 1, 1, 0, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
116 def HEXAGON_M2_mpy_sat_rnd_ll_s0 :
117 T_M2_mpy <0b00, 1, 1, 0, 0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
118 def HEXAGON_M2_mpy_sat_rnd_lh_s1 :
119 T_M2_mpy <0b01, 1, 1, 1, 0, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
120 def HEXAGON_M2_mpy_sat_rnd_lh_s0 :
121 T_M2_mpy <0b01, 1, 1, 0, 0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
122 def HEXAGON_M2_mpy_sat_rnd_hl_s1 :
123 T_M2_mpy <0b10, 1, 1, 1, 0, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
124 def HEXAGON_M2_mpy_sat_rnd_hl_s0 :
125 T_M2_mpy <0b10, 1, 1, 0, 0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
126 def HEXAGON_M2_mpy_sat_rnd_hh_s1 :
127 T_M2_mpy <0b11, 1, 1, 1, 0, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
128 def HEXAGON_M2_mpy_sat_rnd_hh_s0 :
129 T_M2_mpy <0b11, 1, 1, 0, 0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
130 }
131
13215 //
13316 // ALU 32 types.
13417 //
983866 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
984867 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
985868
869 class si_MInst_sisi_hh_s1
870 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
871 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
872 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
873
986874 class si_MInst_sisi_lh
987875 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
988876 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
989877 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
990878
879 class si_MInst_sisi_lh_s1
880 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
881 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
882 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
883
991884 class si_MInst_sisi_hl
992885 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
993886 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
994887 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
995888
889 class si_MInst_sisi_hl_s1
890 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
891 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
892 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
893
996894 class si_MInst_sisi_ll
997895 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
998896 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
897 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
898
899 class si_MInst_sisi_ll_s1
900 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
901 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
999902 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1000903
1001904 class si_MInst_sisi_up
15561459 : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
15571460 !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
15581461 [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1462
1463 class si_MInst_sisi_sat_hh
1464 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1465 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
1466 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1467
1468 class si_MInst_sisi_sat_hh_s1
1469 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1470 !strconcat("$dst = ", !strconcat(opc ,
1471 "($src1.H, $src2.H):<<1:sat")),
1472 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1473
1474 class si_MInst_sisi_sat_hl
1475 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1476 !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
1477 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1478
1479 class si_MInst_sisi_sat_hl_s1
1480 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1481 !strconcat("$dst = ", !strconcat(opc ,
1482 "($src1.H, $src2.L):<<1:sat")),
1483 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1484
1485 class si_MInst_sisi_sat_lh
1486 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1487 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1488 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1489
1490 class si_MInst_sisi_sat_lh_s1
1491 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1492 !strconcat("$dst = ", !strconcat(opc ,
1493 "($src1.L, $src2.H):<<1:sat")),
1494 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1495
1496 class si_MInst_sisi_sat_ll
1497 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1498 !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
1499 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1500
1501 class si_MInst_sisi_sat_ll_s1
1502 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1503 !strconcat("$dst = ", !strconcat(opc ,
1504 "($src1.L, $src2.L):<<1:sat")),
1505 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1506
1507 class si_MInst_sisi_sat_rnd_hh
1508 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1509 !strconcat("$dst = ", !strconcat(opc ,
1510 "($src1.H, $src2.H):rnd:sat")),
1511 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1512
1513 class si_MInst_sisi_rnd_hh
1514 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1515 !strconcat("$dst = ", !strconcat(opc ,
1516 "($src1.H, $src2.H):rnd")),
1517 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1518
1519 class si_MInst_sisi_rnd_hh_s1
1520 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1521 !strconcat("$dst = ", !strconcat(opc ,
1522 "($src1.H, $src2.H):<<1:rnd")),
1523 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1524
1525 class si_MInst_sisi_sat_rnd_hh_s1
1526 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1527 !strconcat("$dst = ",
1528 !strconcat(opc ,
1529 "($src1.H, $src2.H):<<1:rnd:sat")),
1530 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1531
1532 class si_MInst_sisi_rnd_hl
1533 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1534 !strconcat("$dst = ",
1535 !strconcat(opc , "($src1.H, $src2.L):rnd")),
1536 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1537
1538 class si_MInst_sisi_rnd_hl_s1
1539 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1540 !strconcat("$dst = ",
1541 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
1542 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1543
1544 class si_MInst_sisi_sat_rnd_hl
1545 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1546 !strconcat("$dst = ",
1547 !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
1548 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1549
1550 class si_MInst_sisi_sat_rnd_hl_s1
1551 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1552 !strconcat("$dst = ",
1553 !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
1554 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1555
1556 class si_MInst_sisi_rnd_lh
1557 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1558 !strconcat("$dst = ",
1559 !strconcat(opc , "($src1.L, $src2.H):rnd")),
1560 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1561
1562 class si_MInst_sisi_sat_rnd_lh
1563 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1564 !strconcat("$dst = ",
1565 !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
1566 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1567
1568 class si_MInst_sisi_sat_rnd_lh_s1
1569 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1570 !strconcat("$dst = ",
1571 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
1572 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1573
1574 class si_MInst_sisi_rnd_lh_s1
1575 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1576 !strconcat("$dst = ",
1577 !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
1578 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1579
1580 class si_MInst_sisi_sat_rnd_ll
1581 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1582 !strconcat("$dst = ",
1583 !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
1584 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1585
1586 class si_MInst_sisi_sat_rnd_ll_s1
1587 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1588 !strconcat("$dst = ",
1589 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
1590 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1591
1592 class si_MInst_sisi_rnd_ll
1593 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1594 !strconcat("$dst = ",
1595 !strconcat(opc , "($src1.L, $src2.L):rnd")),
1596 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1597
1598 class si_MInst_sisi_rnd_ll_s1
1599 : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1600 !strconcat("$dst = ",
1601 !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
1602 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
15591603
15601604 class di_MInst_dididi_acc_sat
15611605 : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
25192563 // MTYPE / MPYS / Scalar 16x16 multiply signed.
25202564 //Rd=mpy(Rs.[H|L],Rt.[H|L:<<0|:<<1]|
25212565 // [:<<0[:rnd|:sat|:rnd:sat]|:<<1[:rnd|:sat|:rnd:sat]]]
2566 def HEXAGON_M2_mpy_hh_s0:
2567 si_MInst_sisi_hh <"mpy", int_hexagon_M2_mpy_hh_s0>;
2568 def HEXAGON_M2_mpy_hh_s1:
2569 si_MInst_sisi_hh_s1 <"mpy", int_hexagon_M2_mpy_hh_s1>;
2570 def HEXAGON_M2_mpy_rnd_hh_s1:
2571 si_MInst_sisi_rnd_hh_s1 <"mpy", int_hexagon_M2_mpy_rnd_hh_s1>;
2572 def HEXAGON_M2_mpy_sat_rnd_hh_s1:
2573 si_MInst_sisi_sat_rnd_hh_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_hh_s1>;
2574 def HEXAGON_M2_mpy_sat_hh_s1:
2575 si_MInst_sisi_sat_hh_s1 <"mpy", int_hexagon_M2_mpy_sat_hh_s1>;
2576 def HEXAGON_M2_mpy_rnd_hh_s0:
2577 si_MInst_sisi_rnd_hh <"mpy", int_hexagon_M2_mpy_rnd_hh_s0>;
2578 def HEXAGON_M2_mpy_sat_rnd_hh_s0:
2579 si_MInst_sisi_sat_rnd_hh <"mpy", int_hexagon_M2_mpy_sat_rnd_hh_s0>;
2580 def HEXAGON_M2_mpy_sat_hh_s0:
2581 si_MInst_sisi_sat_hh <"mpy", int_hexagon_M2_mpy_sat_hh_s0>;
2582
2583 def HEXAGON_M2_mpy_hl_s0:
2584 si_MInst_sisi_hl <"mpy", int_hexagon_M2_mpy_hl_s0>;
2585 def HEXAGON_M2_mpy_hl_s1:
2586 si_MInst_sisi_hl_s1 <"mpy", int_hexagon_M2_mpy_hl_s1>;
2587 def HEXAGON_M2_mpy_rnd_hl_s1:
2588 si_MInst_sisi_rnd_hl_s1 <"mpy", int_hexagon_M2_mpy_rnd_hl_s1>;
2589 def HEXAGON_M2_mpy_sat_rnd_hl_s1:
2590 si_MInst_sisi_sat_rnd_hl_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_hl_s1>;
2591 def HEXAGON_M2_mpy_sat_hl_s1:
2592 si_MInst_sisi_sat_hl_s1 <"mpy", int_hexagon_M2_mpy_sat_hl_s1>;
2593 def HEXAGON_M2_mpy_rnd_hl_s0:
2594 si_MInst_sisi_rnd_hl <"mpy", int_hexagon_M2_mpy_rnd_hl_s0>;
2595 def HEXAGON_M2_mpy_sat_rnd_hl_s0:
2596 si_MInst_sisi_sat_rnd_hl <"mpy", int_hexagon_M2_mpy_sat_rnd_hl_s0>;
2597 def HEXAGON_M2_mpy_sat_hl_s0:
2598 si_MInst_sisi_sat_hl <"mpy", int_hexagon_M2_mpy_sat_hl_s0>;
2599
2600 def HEXAGON_M2_mpy_lh_s0:
2601 si_MInst_sisi_lh <"mpy", int_hexagon_M2_mpy_lh_s0>;
2602 def HEXAGON_M2_mpy_lh_s1:
2603 si_MInst_sisi_lh_s1 <"mpy", int_hexagon_M2_mpy_lh_s1>;
2604 def HEXAGON_M2_mpy_rnd_lh_s1:
2605 si_MInst_sisi_rnd_lh_s1 <"mpy", int_hexagon_M2_mpy_rnd_lh_s1>;
2606 def HEXAGON_M2_mpy_sat_rnd_lh_s1:
2607 si_MInst_sisi_sat_rnd_lh_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_lh_s1>;
2608 def HEXAGON_M2_mpy_sat_lh_s1:
2609 si_MInst_sisi_sat_lh_s1 <"mpy", int_hexagon_M2_mpy_sat_lh_s1>;
2610 def HEXAGON_M2_mpy_rnd_lh_s0:
2611 si_MInst_sisi_rnd_lh <"mpy", int_hexagon_M2_mpy_rnd_lh_s0>;
2612 def HEXAGON_M2_mpy_sat_rnd_lh_s0:
2613 si_MInst_sisi_sat_rnd_lh <"mpy", int_hexagon_M2_mpy_sat_rnd_lh_s0>;
2614 def HEXAGON_M2_mpy_sat_lh_s0:
2615 si_MInst_sisi_sat_lh <"mpy", int_hexagon_M2_mpy_sat_lh_s0>;
2616
2617 def HEXAGON_M2_mpy_ll_s0:
2618 si_MInst_sisi_ll <"mpy", int_hexagon_M2_mpy_ll_s0>;
2619 def HEXAGON_M2_mpy_ll_s1:
2620 si_MInst_sisi_ll_s1 <"mpy", int_hexagon_M2_mpy_ll_s1>;
2621 def HEXAGON_M2_mpy_rnd_ll_s1:
2622 si_MInst_sisi_rnd_ll_s1 <"mpy", int_hexagon_M2_mpy_rnd_ll_s1>;
2623 def HEXAGON_M2_mpy_sat_rnd_ll_s1:
2624 si_MInst_sisi_sat_rnd_ll_s1 <"mpy", int_hexagon_M2_mpy_sat_rnd_ll_s1>;
2625 def HEXAGON_M2_mpy_sat_ll_s1:
2626 si_MInst_sisi_sat_ll_s1 <"mpy", int_hexagon_M2_mpy_sat_ll_s1>;
2627 def HEXAGON_M2_mpy_rnd_ll_s0:
2628 si_MInst_sisi_rnd_ll <"mpy", int_hexagon_M2_mpy_rnd_ll_s0>;
2629 def HEXAGON_M2_mpy_sat_rnd_ll_s0:
2630 si_MInst_sisi_sat_rnd_ll <"mpy", int_hexagon_M2_mpy_sat_rnd_ll_s0>;
2631 def HEXAGON_M2_mpy_sat_ll_s0:
2632 si_MInst_sisi_sat_ll <"mpy", int_hexagon_M2_mpy_sat_ll_s0>;
2633
25222634 //Rdd=mpy(Rs.[H|L],Rt.[H|L])[[:<<0|:<<1]|[:<<0:rnd|:<<1:rnd]]
25232635 def HEXAGON_M2_mpyd_hh_s0:
25242636 di_MInst_sisi_hh <"mpy", int_hexagon_M2_mpyd_hh_s0>;
26722784 def HEXAGON_M2_mpyd_nac_ll_s1:
26732785 di_MInst_disisi_nac_ll_s1 <"mpy", int_hexagon_M2_mpyd_nac_ll_s1>;
26742786
2787 // MTYPE / MPYS / Scalar 16x16 multiply unsigned.
2788 //Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
2789 def HEXAGON_M2_mpyu_hh_s0:
2790 si_MInst_sisi_hh <"mpyu", int_hexagon_M2_mpyu_hh_s0>;
2791 def HEXAGON_M2_mpyu_hh_s1:
2792 si_MInst_sisi_hh_s1 <"mpyu", int_hexagon_M2_mpyu_hh_s1>;
2793 def HEXAGON_M2_mpyu_hl_s0:
2794 si_MInst_sisi_hl <"mpyu", int_hexagon_M2_mpyu_hl_s0>;
2795 def HEXAGON_M2_mpyu_hl_s1:
2796 si_MInst_sisi_hl_s1 <"mpyu", int_hexagon_M2_mpyu_hl_s1>;
2797 def HEXAGON_M2_mpyu_lh_s0:
2798 si_MInst_sisi_lh <"mpyu", int_hexagon_M2_mpyu_lh_s0>;
2799 def HEXAGON_M2_mpyu_lh_s1:
2800 si_MInst_sisi_lh_s1 <"mpyu", int_hexagon_M2_mpyu_lh_s1>;
2801 def HEXAGON_M2_mpyu_ll_s0:
2802 si_MInst_sisi_ll <"mpyu", int_hexagon_M2_mpyu_ll_s0>;
2803 def HEXAGON_M2_mpyu_ll_s1:
2804 si_MInst_sisi_ll_s1 <"mpyu", int_hexagon_M2_mpyu_ll_s1>;
26752805
26762806 //Rdd=mpyu(Rs.[H|L],Rt.[H|L])[:<<0|:<<1]
26772807 def HEXAGON_M2_mpyud_hh_s0:
133133 def M0 : Rc<6, "m0">, DwarfRegNum<[71]>;
134134 def M1 : Rc<7, "m1">, DwarfRegNum<[72]>;
135135
136 def USR : Rc<8, "usr">, DwarfRegNum<[34]>;
137 def PC : Rc<9, "pc">, DwarfRegNum<[32]>;
138 def GP : Rc<11, "gp">, DwarfRegNum<[33]>;
136 def PC : Rc<9, "pc">, DwarfRegNum<[32]>; // is the Dwarf number correct?
137 def GP : Rc<11, "gp">, DwarfRegNum<[33]>; // is the Dwarf number correct?
139138 }
140139
141140 // Register classes.
162161 def CRRegs : RegisterClass<"Hexagon", [i32], 32,
163162 (add (sequence "LC%u", 0, 1),
164163 (sequence "SA%u", 0, 1),
165 (sequence "M%u", 0, 1), PC, GP, USR)> {
164 (sequence "M%u", 0, 1), PC, GP)> {
166165 let Size = 32;
167166 }
+0
-456
test/CodeGen/Hexagon/intrinsics-mpy.ll less more
None ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
1
2 ; Verify that the mpy intrinsics are lowered into the right instructions.
3
4 @c = external global i32
5
6 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l)
7
8 define void @test1(i32 %a1, i32 %b1) #0 {
9 entry:
10 %0 = tail call i32 @llvm.hexagon.M2.mpy.ll.s0(i32 %a1, i32 %b1)
11 store i32 %0, i32* @c, align 4, !tbaa !1
12 ret void
13 }
14
15 declare i32 @llvm.hexagon.M2.mpy.ll.s0(i32, i32) #1
16
17 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h)
18
19 define void @test2(i32 %a2, i32 %b2) #0 {
20 entry:
21 %0 = tail call i32 @llvm.hexagon.M2.mpy.lh.s0(i32 %a2, i32 %b2)
22 store i32 %0, i32* @c, align 4, !tbaa !1
23 ret void
24 }
25
26 declare i32 @llvm.hexagon.M2.mpy.lh.s0(i32, i32) #1
27
28 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l)
29
30 define void @test3(i32 %a3, i32 %b3) #0 {
31 entry:
32 %0 = tail call i32 @llvm.hexagon.M2.mpy.hl.s0(i32 %a3, i32 %b3)
33 store i32 %0, i32* @c, align 4, !tbaa !1
34 ret void
35 }
36
37 declare i32 @llvm.hexagon.M2.mpy.hl.s0(i32, i32) #1
38
39 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h)
40
41 define void @test4(i32 %a4, i32 %b4) #0 {
42 entry:
43 %0 = tail call i32 @llvm.hexagon.M2.mpy.hh.s0(i32 %a4, i32 %b4)
44 store i32 %0, i32* @c, align 4, !tbaa !1
45 ret void
46 }
47
48 declare i32 @llvm.hexagon.M2.mpy.hh.s0(i32, i32) #1
49
50 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):sat
51
52 define void @test5(i32 %a5, i32 %b5) #0 {
53 entry:
54 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.ll.s0(i32 %a5, i32 %b5)
55 store i32 %0, i32* @c, align 4, !tbaa !1
56 ret void
57 }
58
59 declare i32 @llvm.hexagon.M2.mpy.sat.ll.s0(i32, i32) #1
60
61 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):sat
62
63 define void @test6(i32 %a6, i32 %b6) #0 {
64 entry:
65 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.lh.s0(i32 %a6, i32 %b6)
66 store i32 %0, i32* @c, align 4, !tbaa !1
67 ret void
68 }
69
70 declare i32 @llvm.hexagon.M2.mpy.sat.lh.s0(i32, i32) #1
71
72 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):sat
73
74 define void @test7(i32 %a7, i32 %b7) #0 {
75 entry:
76 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.hl.s0(i32 %a7, i32 %b7)
77 store i32 %0, i32* @c, align 4, !tbaa !1
78 ret void
79 }
80
81 declare i32 @llvm.hexagon.M2.mpy.sat.hl.s0(i32, i32) #1
82
83 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):sat
84
85 define void @test8(i32 %a8, i32 %b8) #0 {
86 entry:
87 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.hh.s0(i32 %a8, i32 %b8)
88 store i32 %0, i32* @c, align 4, !tbaa !1
89 ret void
90 }
91
92 declare i32 @llvm.hexagon.M2.mpy.sat.hh.s0(i32, i32) #1
93
94 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):rnd
95
96 define void @test9(i32 %a9, i32 %b9) #0 {
97 entry:
98 %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.ll.s0(i32 %a9, i32 %b9)
99 store i32 %0, i32* @c, align 4, !tbaa !1
100 ret void
101 }
102
103 declare i32 @llvm.hexagon.M2.mpy.rnd.ll.s0(i32, i32) #1
104
105 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):rnd
106
107 define void @test10(i32 %a10, i32 %b10) #0 {
108 entry:
109 %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.lh.s0(i32 %a10, i32 %b10)
110 store i32 %0, i32* @c, align 4, !tbaa !1
111 ret void
112 }
113
114 declare i32 @llvm.hexagon.M2.mpy.rnd.lh.s0(i32, i32) #1
115
116 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):rnd
117
118 define void @test11(i32 %a11, i32 %b11) #0 {
119 entry:
120 %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.hl.s0(i32 %a11, i32 %b11)
121 store i32 %0, i32* @c, align 4, !tbaa !1
122 ret void
123 }
124
125 declare i32 @llvm.hexagon.M2.mpy.rnd.hl.s0(i32, i32) #1
126
127 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):rnd
128
129 define void @test12(i32 %a12, i32 %b12) #0 {
130 entry:
131 %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.hh.s0(i32 %a12, i32 %b12)
132 store i32 %0, i32* @c, align 4, !tbaa !1
133 ret void
134 }
135
136 declare i32 @llvm.hexagon.M2.mpy.rnd.hh.s0(i32, i32) #1
137
138 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):rnd:sat
139
140 define void @test13(i32 %a13, i32 %b13) #0 {
141 entry:
142 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s0(i32 %a13, i32 %b13)
143 store i32 %0, i32* @c, align 4, !tbaa !1
144 ret void
145 }
146
147 declare i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s0(i32, i32) #1
148
149 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):rnd:sat
150
151 define void @test14(i32 %a14, i32 %b14) #0 {
152 entry:
153 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s0(i32 %a14, i32 %b14)
154 store i32 %0, i32* @c, align 4, !tbaa !1
155 ret void
156 }
157
158 declare i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s0(i32, i32) #1
159
160 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):rnd:sat
161
162 define void @test15(i32 %a15, i32 %b15) #0 {
163 entry:
164 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s0(i32 %a15, i32 %b15)
165 store i32 %0, i32* @c, align 4, !tbaa !1
166 ret void
167 }
168
169 declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s0(i32, i32) #1
170
171 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):rnd:sat
172
173 define void @test16(i32 %a16, i32 %b16) #0 {
174 entry:
175 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s0(i32 %a16, i32 %b16)
176 store i32 %0, i32* @c, align 4, !tbaa !1
177 ret void
178 }
179
180 declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s0(i32, i32) #1
181
182 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l)
183
184 define void @test17(i32 %a17, i32 %b17) #0 {
185 entry:
186 %0 = tail call i32 @llvm.hexagon.M2.mpyu.ll.s0(i32 %a17, i32 %b17)
187 store i32 %0, i32* @c, align 4, !tbaa !1
188 ret void
189 }
190
191 declare i32 @llvm.hexagon.M2.mpyu.ll.s0(i32, i32) #1
192
193 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h)
194
195 define void @test18(i32 %a18, i32 %b18) #0 {
196 entry:
197 %0 = tail call i32 @llvm.hexagon.M2.mpyu.lh.s0(i32 %a18, i32 %b18)
198 store i32 %0, i32* @c, align 4, !tbaa !1
199 ret void
200 }
201
202 declare i32 @llvm.hexagon.M2.mpyu.lh.s0(i32, i32) #1
203
204 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l)
205
206 define void @test19(i32 %a19, i32 %b19) #0 {
207 entry:
208 %0 = tail call i32 @llvm.hexagon.M2.mpyu.hl.s0(i32 %a19, i32 %b19)
209 store i32 %0, i32* @c, align 4, !tbaa !1
210 ret void
211 }
212
213 declare i32 @llvm.hexagon.M2.mpyu.hl.s0(i32, i32) #1
214
215 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h)
216
217 define void @test20(i32 %a20, i32 %b20) #0 {
218 entry:
219 %0 = tail call i32 @llvm.hexagon.M2.mpyu.hh.s0(i32 %a20, i32 %b20)
220 store i32 %0, i32* @c, align 4, !tbaa !1
221 ret void
222 }
223
224 declare i32 @llvm.hexagon.M2.mpyu.hh.s0(i32, i32) #1
225
226 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
227
228 define void @test21(i32 %a21, i32 %b21) #0 {
229 entry:
230 %0 = tail call i32 @llvm.hexagon.M2.mpy.ll.s1(i32 %a21, i32 %b21)
231 store i32 %0, i32* @c, align 4, !tbaa !1
232 ret void
233 }
234
235 declare i32 @llvm.hexagon.M2.mpy.ll.s1(i32, i32) #1
236
237 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
238
239 define void @test22(i32 %a22, i32 %b22) #0 {
240 entry:
241 %0 = tail call i32 @llvm.hexagon.M2.mpy.lh.s1(i32 %a22, i32 %b22)
242 store i32 %0, i32* @c, align 4, !tbaa !1
243 ret void
244 }
245
246 declare i32 @llvm.hexagon.M2.mpy.lh.s1(i32, i32) #1
247
248 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
249
250 define void @test23(i32 %a23, i32 %b23) #0 {
251 entry:
252 %0 = tail call i32 @llvm.hexagon.M2.mpy.hl.s1(i32 %a23, i32 %b23)
253 store i32 %0, i32* @c, align 4, !tbaa !1
254 ret void
255 }
256
257 declare i32 @llvm.hexagon.M2.mpy.hl.s1(i32, i32) #1
258
259 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
260
261 define void @test24(i32 %a24, i32 %b24) #0 {
262 entry:
263 %0 = tail call i32 @llvm.hexagon.M2.mpy.hh.s1(i32 %a24, i32 %b24)
264 store i32 %0, i32* @c, align 4, !tbaa !1
265 ret void
266 }
267
268 declare i32 @llvm.hexagon.M2.mpy.hh.s1(i32, i32) #1
269
270 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:sat
271
272 define void @test25(i32 %a25, i32 %b25) #0 {
273 entry:
274 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32 %a25, i32 %b25)
275 store i32 %0, i32* @c, align 4, !tbaa !1
276 ret void
277 }
278
279 declare i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32, i32) #1
280
281 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:sat
282
283 define void @test26(i32 %a26, i32 %b26) #0 {
284 entry:
285 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.lh.s1(i32 %a26, i32 %b26)
286 store i32 %0, i32* @c, align 4, !tbaa !1
287 ret void
288 }
289
290 declare i32 @llvm.hexagon.M2.mpy.sat.lh.s1(i32, i32) #1
291
292 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:sat
293
294 define void @test27(i32 %a27, i32 %b27) #0 {
295 entry:
296 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.hl.s1(i32 %a27, i32 %b27)
297 store i32 %0, i32* @c, align 4, !tbaa !1
298 ret void
299 }
300
301 declare i32 @llvm.hexagon.M2.mpy.sat.hl.s1(i32, i32) #1
302
303 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:sat
304
305 define void @test28(i32 %a28, i32 %b28) #0 {
306 entry:
307 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.hh.s1(i32 %a28, i32 %b28)
308 store i32 %0, i32* @c, align 4, !tbaa !1
309 ret void
310 }
311
312 declare i32 @llvm.hexagon.M2.mpy.sat.hh.s1(i32, i32) #1
313
314 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:rnd
315
316 define void @test29(i32 %a29, i32 %b29) #0 {
317 entry:
318 %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.ll.s1(i32 %a29, i32 %b29)
319 store i32 %0, i32* @c, align 4, !tbaa !1
320 ret void
321 }
322
323 declare i32 @llvm.hexagon.M2.mpy.rnd.ll.s1(i32, i32) #1
324
325 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:rnd
326
327 define void @test30(i32 %a30, i32 %b30) #0 {
328 entry:
329 %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.lh.s1(i32 %a30, i32 %b30)
330 store i32 %0, i32* @c, align 4, !tbaa !1
331 ret void
332 }
333
334 declare i32 @llvm.hexagon.M2.mpy.rnd.lh.s1(i32, i32) #1
335
336 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:rnd
337
338 define void @test31(i32 %a31, i32 %b31) #0 {
339 entry:
340 %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.hl.s1(i32 %a31, i32 %b31)
341 store i32 %0, i32* @c, align 4, !tbaa !1
342 ret void
343 }
344
345 declare i32 @llvm.hexagon.M2.mpy.rnd.hl.s1(i32, i32) #1
346
347 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:rnd
348
349 define void @test32(i32 %a32, i32 %b32) #0 {
350 entry:
351 %0 = tail call i32 @llvm.hexagon.M2.mpy.rnd.hh.s1(i32 %a32, i32 %b32)
352 store i32 %0, i32* @c, align 4, !tbaa !1
353 ret void
354 }
355
356 declare i32 @llvm.hexagon.M2.mpy.rnd.hh.s1(i32, i32) #1
357
358 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:rnd:sat
359
360 define void @test33(i32 %a33, i32 %b33) #0 {
361 entry:
362 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s1(i32 %a33, i32 %b33)
363 store i32 %0, i32* @c, align 4, !tbaa !1
364 ret void
365 }
366
367 declare i32 @llvm.hexagon.M2.mpy.sat.rnd.ll.s1(i32, i32) #1
368
369 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:rnd:sat
370
371 define void @test34(i32 %a34, i32 %b34) #0 {
372 entry:
373 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s1(i32 %a34, i32 %b34)
374 store i32 %0, i32* @c, align 4, !tbaa !1
375 ret void
376 }
377
378 declare i32 @llvm.hexagon.M2.mpy.sat.rnd.lh.s1(i32, i32) #1
379
380 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1:rnd:sat
381
382 define void @test35(i32 %a35, i32 %b35) #0 {
383 entry:
384 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s1(i32 %a35, i32 %b35)
385 store i32 %0, i32* @c, align 4, !tbaa !1
386 ret void
387 }
388
389 declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hl.s1(i32, i32) #1
390
391 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1:rnd:sat
392
393 define void @test36(i32 %a36, i32 %b36) #0 {
394 entry:
395 %0 = tail call i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s1(i32 %a36, i32 %b36)
396 store i32 %0, i32* @c, align 4, !tbaa !1
397 ret void
398 }
399
400 declare i32 @llvm.hexagon.M2.mpy.sat.rnd.hh.s1(i32, i32) #1
401
402 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
403
404 define void @test37(i32 %a37, i32 %b37) #0 {
405 entry:
406 %0 = tail call i32 @llvm.hexagon.M2.mpyu.ll.s1(i32 %a37, i32 %b37)
407 store i32 %0, i32* @c, align 4, !tbaa !1
408 ret void
409 }
410
411 declare i32 @llvm.hexagon.M2.mpyu.ll.s1(i32, i32) #1
412
413 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
414
415 define void @test38(i32 %a38, i32 %b38) #0 {
416 entry:
417 %0 = tail call i32 @llvm.hexagon.M2.mpyu.lh.s1(i32 %a38, i32 %b38)
418 store i32 %0, i32* @c, align 4, !tbaa !1
419 ret void
420 }
421
422 declare i32 @llvm.hexagon.M2.mpyu.lh.s1(i32, i32) #1
423
424 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
425
426 define void @test39(i32 %a39, i32 %b39) #0 {
427 entry:
428 %0 = tail call i32 @llvm.hexagon.M2.mpyu.hl.s1(i32 %a39, i32 %b39)
429 store i32 %0, i32* @c, align 4, !tbaa !1
430 ret void
431 }
432
433 declare i32 @llvm.hexagon.M2.mpyu.hl.s1(i32, i32) #1
434
435 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
436
437 define void @test40(i32 %a40, i32 %b40) #0 {
438 entry:
439 %0 = tail call i32 @llvm.hexagon.M2.mpyu.hh.s1(i32 %a40, i32 %b40)
440 store i32 %0, i32* @c, align 4, !tbaa !1
441 ret void
442 }
443
444 declare i32 @llvm.hexagon.M2.mpyu.hh.s1(i32, i32) #1
445
446 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
447 attributes #1 = { nounwind readnone }
448
449 !llvm.ident = !{!0}
450
451 !0 = metadata !{metadata !"QuIC LLVM Hexagon Clang version 7.1-internal"}
452 !1 = metadata !{metadata !2, metadata !2, i64 0}
453 !2 = metadata !{metadata !"int", metadata !3, i64 0}
454 !3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}
455 !4 = metadata !{metadata !"Simple C/C++ TBAA"}
+0
-126
test/MC/Hexagon/mpy.s less more
None #REQUIRES: object-emission
1 #This test will be enabled when assembler support has been added.
2
3 #RUN: llvm-mc -filetype=obj %s | llvm-objdump -d - | FileCheck %s
4
5 # Check encoding bits for half-word multiply instructions.
6
7 r7=mpy(r28.l,r20.h):<<1:rnd
8 #CHECK: ecbcd427 { r7 = mpy(r28.l, r20.h):<<1:rnd }
9
10 r18=mpy(r9.l,r21.h):rnd
11 #CHECK: ec29d532 { r18 = mpy(r9.l, r21.h):rnd }
12
13 r19=mpyu(r23.l,r20.l)
14 #CHECK: ec57d413 { r19 = mpyu(r23.l, r20.l) }
15
16 r22=mpyu(r19.l,r30.l):<<1
17 #CHECK: ecd3de16 { r22 = mpyu(r19.l, r30.l):<<1 }
18
19 r19=mpy(r16.h,r19.h)
20 #CHECK: ec10d373 { r19 = mpy(r16.h, r19.h) }
21
22 r30=mpy(r0.h,r16.h):<<1
23 #CHECK: ec80d07e { r30 = mpy(r0.h, r16.h):<<1 }
24
25 lr=mpy(r15.h,r25.l)
26 #CHECK: ec0fd95f { r31 = mpy(r15.h, r25.l) }
27
28 r29=mpy(r28.h,r15.l):<<1
29 #CHECK: ec9ccf5d { r29 = mpy(r28.h, r15.l):<<1 }
30
31 r20=mpy(r31.l,r19.h)
32 #CHECK: ec1fd334 { r20 = mpy(r31.l, r19.h) }
33
34 r24=mpy(r19.l,r15.h):<<1
35 #CHECK: ec93cf38 { r24 = mpy(r19.l, r15.h):<<1 }
36
37 r30=mpy(r10.l,sp.l)
38 #CHECK: ec0add1e { r30 = mpy(r10.l, r29.l) }
39
40 r7=mpy(r3.l,r4.l):<<1
41 #CHECK: ec83c407 { r7 = mpy(r3.l, r4.l):<<1 }
42
43 r30=mpy(r23.h,r2.h):rnd:sat
44 #CHECK: ec37c2fe { r30 = mpy(r23.h, r2.h):rnd:sat }
45
46 r5=mpy(r28.h,r27.h):<<1:rnd:sat
47 #CHECK: ecbcdbe5 { r5 = mpy(r28.h, r27.h):<<1:rnd:sat }
48
49 r26=mpy(r21.l,r23.l):rnd
50 #CHECK: ec35d71a { r26 = mpy(r21.l, r23.l):rnd }
51
52 sp=mpy(r25.h,r12.h):<<1:rnd
53 #CHECK: ecb9cc7d { r29 = mpy(r25.h, r12.h):<<1:rnd }
54
55 r1=mpy(r27.h,r29.h):rnd
56 #CHECK: ec3bdd61 { r1 = mpy(r27.h, r29.h):rnd }
57
58 r0=mpy(r2.h,r11.h):<<1:sat
59 #CHECK: ec82cbe0 { r0 = mpy(r2.h, r11.h):<<1:sat }
60
61 r3=mpy(r20.l,r30.l):rnd:sat
62 #CHECK: ec34de83 { r3 = mpy(r20.l, r30.l):rnd:sat }
63
64 r4=mpy(r21.h,r5.l):<<1:sat
65 #CHECK: ec95c5c4 { r4 = mpy(r21.h, r5.l):<<1:sat }
66
67 fp=mpy(r20.l,r12.h):rnd:sat
68 #CHECK: ec34ccbe { r30 = mpy(r20.l, r12.h):rnd:sat }
69
70 r12=mpy(sp.l,r30.h):<<1:rnd:sat
71 #CHECK: ecbddeac { r12 = mpy(r29.l, r30.h):<<1:rnd:sat }
72
73 r6=mpy(r10.h,fp.l):rnd:sat
74 #CHECK: ec2adec6 { r6 = mpy(r10.h, r30.l):rnd:sat }
75
76 r24=mpy(r12.h,r1.h):sat
77 #CHECK: ec0cc1f8 { r24 = mpy(r12.h, r1.h):sat }
78
79 r29=mpyu(r25.h,sp.l)
80 #CHECK: ec59dd5d { r29 = mpyu(r25.h, r29.l) }
81
82 r24=mpyu(lr.h,r29.l):<<1
83 #CHECK: ecdfdd58 { r24 = mpyu(r31.h, r29.l):<<1 }
84
85 r26=mpyu(r21.l,r18.h)
86 #CHECK: ec55d23a { r26 = mpyu(r21.l, r18.h) }
87
88 r29=mpyu(r4.l,r26.h):<<1
89 #CHECK: ecc4da3d { r29 = mpyu(r4.l, r26.h):<<1 }
90
91 fp=mpy(r8.l,r0.l):sat
92 #CHECK: ec08c09e { r30 = mpy(r8.l, r0.l):sat }
93
94 r1=mpy(r26.l,r16.l):<<1:sat
95 #CHECK: ec9ad081 { r1 = mpy(r26.l, r16.l):<<1:sat }
96
97 r16=mpyu(r26.h,r6.h)
98 #CHECK: ec5ac670 { r16 = mpyu(r26.h, r6.h) }
99
100 lr=mpyu(r23.h,r13.h):<<1
101 #CHECK: ecd7cd7f { r31 = mpyu(r23.h, r13.h):<<1 }
102
103 r14=mpy(r2.l,r7.h):sat
104 #CHECK: ec02c7ae { r14 = mpy(r2.l, r7.h):sat }
105
106 r9=mpy(r1.l,r9.h):<<1:sat
107 #CHECK: ec81c9a9 { r9 = mpy(r1.l, r9.h):<<1:sat }
108
109 r9=mpy(r30.l,r4.l):<<1:rnd:sat
110 #CHECK: ecbec489 { r9 = mpy(r30.l, r4.l):<<1:rnd:sat }
111
112 r9=mpy(r15.h,r27.l):<<1:rnd
113 #CHECK: ecafdb49 { r9 = mpy(r15.h, r27.l):<<1:rnd }
114
115 r16=mpy(r6.h,r16.l):rnd
116 #CHECK: ec26d050 { r16 = mpy(r6.h, r16.l):rnd }
117
118 r1=mpy(r10.l,r29.l):<<1:rnd
119 #CHECK: ecaadd01 { r1 = mpy(r10.l, r29.l):<<1:rnd }
120
121 r7=mpy(r4.h,r23.l):sat
122 #CHECK: ec04d7c7 { r7 = mpy(r4.h, r23.l):sat }
123
124 r17=mpy(r12.h,r26.l):<<1:rnd:sat
125 #CHECK: ecacdad1 { r17 = mpy(r12.h, r26.l):<<1:rnd:sat }