llvm.org GIT mirror llvm / 9bb272c
Override TRI::getSubClassWithSubReg for X86. There are fewer registers with sub_8bit sub-registers in 32-bit mode than in 64-bit mode. In 32-bit mode, sub_8bit behaves the same as sub_8bit_hi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141206 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
2 changed file(s) with 15 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
108108 reg += 8;
109109 }
110110 return reg;
111 }
112
113 const TargetRegisterClass *
114 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
115 unsigned Idx) const {
116 // The sub_8bit sub-register index is more constrained in 32-bit mode.
117 // It behaves just like the sub_8bit_hi index.
118 if (!Is64Bit && Idx == X86::sub_8bit)
119 Idx = X86::sub_8bit_hi;
120
121 // Forward to TableGen's default version.
122 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
111123 }
112124
113125 const TargetRegisterClass *
7373 getMatchingSuperRegClass(const TargetRegisterClass *A,
7474 const TargetRegisterClass *B, unsigned Idx) const;
7575
76 virtual const TargetRegisterClass *
77 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const;
78
7679 const TargetRegisterClass*
7780 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
7881