llvm.org GIT mirror llvm / 9b88d2d
Tighten a ARM dag combine condition to avoid an identity transformation, which ends up introducing a cycle in the DAG. rdar://10196296 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 8 years ago
2 changed file(s) with 31 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
73437343 // movne r0, y
73447344 /// FIXME: Turn this into a target neutral optimization?
73457345 SDValue Res;
7346 if (CC == ARMCC::NE && FalseVal == RHS) {
7346 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
73477347 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
73487348 N->getOperand(3), Cmp);
73497349 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
0 ; RUN: llc -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 < %s
1
2 ; rdar://10196296
3 ; ARM target specific dag combine created a cycle in DAG.
4
5 define void @t() nounwind ssp {
6 %1 = load i64* undef, align 4
7 %2 = shl i32 5, 0
8 %3 = zext i32 %2 to i64
9 %4 = and i64 %1, %3
10 %5 = lshr i64 %4, undef
11 switch i64 %5, label %8 [
12 i64 0, label %9
13 i64 1, label %6
14 i64 4, label %9
15 i64 5, label %7
16 ]
17
18 ;
19 unreachable
20
21 ;
22 unreachable
23
24 ;
25 unreachable
26
27 ;
28 ret void
29 }