llvm.org GIT mirror llvm / 9b14371
Update tests to use sse4.2 instead of sse42. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189145 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 6 years ago
23 changed file(s) with 24 addition(s) and 24 deletion(s). Raw diff Collapse all Expand all
None ; RUN: llc -march=x86-64 -mattr=-sse42,+sse4.1 < %s | FileCheck %s
0 ; RUN: llc -march=x86-64 -mattr=-sse4.2,+sse4.1 < %s | FileCheck %s
11 ; Make sure we don't load from the location pointed to by %p
22 ; twice: it has non-obvious performance implications, and
33 ; the relevant transformation doesn't know how to update
None ; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86-64 -mattr=+sse4.2 | FileCheck %s
11
22
33 define float @extractFloat1() nounwind {
None ; RUN: llc < %s -march=x86 -mattr=+mmx,+sse42 -mtriple=x86_64-apple-darwin10 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mattr=+mmx,+sse4.2 -mtriple=x86_64-apple-darwin10 | FileCheck %s
11 ; There are no MMX operations in bork; promoted to XMM.
22
33 define void @bork(<1 x i64>* %x) {
None ; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86-64 -mattr=+sse4.2 | FileCheck %s
11
22 ; Verify when widening a divide/remainder operation, we only generate a
33 ; divide/rem per element since divide/remainder can trap.
None ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X32
1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64
0 ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4.2 | FileCheck %s -check-prefix=X32
1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse4.2 | FileCheck %s -check-prefix=X64
22
33 declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
44 declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
None ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse4.2 | FileCheck %s -check-prefix=X64
11
22 declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind
33 declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind
0 ; RUN: llc < %s -march=x86 -mattr=-sse3,+sse2 | FileCheck %s -check-prefix=SSE2
11 ; RUN: llc < %s -march=x86 -mattr=-sse4.2,+sse4.1 | FileCheck %s -check-prefix=SSE41
2 ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s -check-prefix=SSE42
2 ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s -check-prefix=SSE42
33
44 define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind {
55 ; SSE42-LABEL: test1:
None ; RUN: llc < %s -march=x86 -mattr=+mmx,+sse42 -mtriple=i686-apple-darwin9 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mattr=+mmx,+sse4.2 -mtriple=i686-apple-darwin9 | FileCheck %s
11 ; MMX insertelement is not available; these are promoted to XMM.
22 ; (Without SSE they are split to two ints, and the code is much better.)
33
None ; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+sse4.2 | FileCheck %s
11
22 define void @update(<3 x i8>* %dst, <3 x i8>* %src, i32 %n) nounwind {
33 entry:
None ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
11 ; CHECK: padd
22 ; CHECK: pand
33
None ; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86-64 -mattr=+sse4.2 | FileCheck %s
11 ; CHECK: psubw
22 ; CHECK-NEXT: pmullw
33
None ; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86-64 -mattr=+sse4.2 | FileCheck %s
11 ; CHECK: movdqa
22 ; CHECK: pslld $2
33 ; CHECK: psubd
None ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
11 ; CHECK: mulps
22 ; CHECK: addps
33
None ; RUN: llc < %s -march=x86 -mcpu=nehalem -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mcpu=nehalem -mattr=+sse4.2 | FileCheck %s
11 ; CHECK: pextrd
22 ; CHECK: pextrd
33 ; CHECK: movd
None ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
11 ; CHECK: paddd
22 ; CHECK: pextrd
33 ; CHECK: pextrd
None ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
11 ; CHECK: psraw
22 ; CHECK: psraw
33
None ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
11 ; CHECK: movl
22 ; CHECK: movlpd
33
None ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
11 ; CHECK: paddq
22
33 ; truncate v2i64 to v2i32
None ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
11 ; CHECK: cwtl
22 ; CHECK: cwtl
33
None ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
11 ; CHECK: cvtsi2ss
22
33 ; sign to float v2i16 to v2f32
None ; RUN: llc < %s -march=x86 -mcpu=nehalem -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mcpu=nehalem -mattr=+sse4.2 | FileCheck %s
11 ; CHECK-NOT: cvtsi2ss
22
33 ; unsigned to float v7i16 to v7f32
None ; RUN: llc < %s -march=x86-64 -mcpu=nehalem -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86-64 -mcpu=nehalem -mattr=+sse4.2 | FileCheck %s
11 ; widen extract subvector
22
33 define void @convert(<2 x double>* %dst.addr, <3 x double> %src) {
None ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
0 ; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
11
22 ; widening shuffle v3float and then a add
33 define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {