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[X86][AVX512] Tidied up VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2 comment generation Now matches other shuffles git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272464 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 4 years ago
1 changed file(s) with 19 addition(s) and 37 deletion(s). Raw diff Collapse all Expand all
128128 }
129129 }
130130
131 /// \brief Extracts the types and if it has memory operand for a given
132 /// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction.
133 static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) {
134 HasMemOp = false;
135 switch (MI->getOpcode()) {
136 default:
137 llvm_unreachable("Unknown VSHUF64x2 family instructions.");
138 break;
139 CASE_VSHUF(64X2, m)
140 HasMemOp = true; // FALL THROUGH.
141 CASE_VSHUF(64X2, r)
142 VT = getRegOperandVectorVT(MI, MVT::i64, 0);
143 break;
144 CASE_VSHUF(32X4, m)
145 HasMemOp = true; // FALL THROUGH.
146 CASE_VSHUF(32X4, r)
147 VT = getRegOperandVectorVT(MI, MVT::i32, 0);
148 break;
149 }
150 }
151
152131 //===----------------------------------------------------------------------===//
153132 // Top Level Entrypoint
154133 //===----------------------------------------------------------------------===//
538517 break;
539518
540519 CASE_VSHUF(64X2, r)
520 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
521 RegForm = true;
522 // FALL THROUGH.
541523 CASE_VSHUF(64X2, m)
524 decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i64, 0),
525 MI->getOperand(NumOperands - 1).getImm(),
526 ShuffleMask);
527 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
528 DestName = getRegName(MI->getOperand(0).getReg());
529 break;
530
542531 CASE_VSHUF(32X4, r)
543 CASE_VSHUF(32X4, m) {
544 MVT VT;
545 bool HasMemOp;
546 getVSHUF64x2FamilyInfo(MI, VT, HasMemOp);
547 decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOperands - 1).getImm(),
532 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
533 RegForm = true;
534 // FALL THROUGH.
535 CASE_VSHUF(32X4, m)
536 decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i32, 0),
537 MI->getOperand(NumOperands - 1).getImm(),
548538 ShuffleMask);
549 DestName = getRegName(MI->getOperand(0).getReg());
550 if (HasMemOp) {
551 assert((NumOperands >= 8) && "Expected at least 8 operands!");
552 Src1Name = getRegName(MI->getOperand(NumOperands - 7).getReg());
553 } else {
554 assert((NumOperands >= 4) && "Expected at least 4 operands!");
555 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
556 Src1Name = getRegName(MI->getOperand(NumOperands - 3).getReg());
557 }
558 break;
559 }
539 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
540 DestName = getRegName(MI->getOperand(0).getReg());
541 break;
560542
561543 CASE_UNPCK(UNPCKLPD, r)
562544 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());