llvm.org GIT mirror llvm / 9ad7000
[ARM] Relax constraints on operands of VQxDMLxDH instructions Summary: According to a recently updated Armv8-M spec (https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf) the 32-bit width versions of the following instructions: * VQDMLADH * VQDMLADHX * VQRDMLADH * VQRDMLADHX * VQDMLSDH * VQDMLSDHX * VQRDMLSDH * VQRDMLSDHX are no longer unpredictable when their output register is the same as one of the input registers. This patch updates the assembler parser and the corresponding tests and also removes @earlyclobber from the instruction constraints. Reviewers: simon_tatham, ostannard, dmgreen, SjoerdMeijer, samparker Reviewed By: simon_tatham Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64250 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365306 91177308-0d34-0410-b5e6-96231b3b80d8 Mikhail Maltsev 1 year, 1 month ago
3 changed file(s) with 14 addition(s) and 21 deletion(s). Raw diff Collapse all Expand all
28332833 }
28342834
28352835 class MVE_VQxDMLxDH
2836 string suffix, bits<2> size, bit earlyclobber,
2837 list pattern=[]>
2836 string suffix, bits<2> size, list pattern=[]>
28382837 : MVE_qDest_qSrc
28392838 (ins MQPR:$Qd_src, MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
2840 vpred_n,
2841 !if(earlyclobber, "@earlyclobber $Qd,", "") # "$Qd = $Qd_src",
2842 pattern> {
2839 vpred_n, "$Qd = $Qd_src", pattern> {
28432840 bits<4> Qn;
28442841
28452842 let Inst{28} = subtract;
28542851
28552852 multiclass MVE_VQxDMLxDH_multi
28562853 bit round, bit subtract> {
2857 def s8 : MVE_VQxDMLxDH;
2858 def s16 : MVE_VQxDMLxDH;
2859 def s32 : MVE_VQxDMLxDH>;
2854 def s8 : MVE_VQxDMLxDH>;
2855 def s16 : MVE_VQxDMLxDH;
2856 def s32 : MVE_VQxDMLxDH;
28602857 }
28612858
28622859 defm MVE_VQDMLADH : MVE_VQxDMLxDH_multi<"vqdmladh", 0b0, 0b0, 0b0>;
78647864 case ARM::MVE_VMULLs32bh:
78657865 case ARM::MVE_VMULLs32th:
78667866 case ARM::MVE_VMULLu32bh:
7867 case ARM::MVE_VMULLu32th:
7868 case ARM::MVE_VQDMLADHs32:
7869 case ARM::MVE_VQDMLADHXs32:
7870 case ARM::MVE_VQRDMLADHs32:
7871 case ARM::MVE_VQRDMLADHXs32:
7872 case ARM::MVE_VQDMLSDHs32:
7873 case ARM::MVE_VQDMLSDHXs32:
7874 case ARM::MVE_VQRDMLSDHs32:
7875 case ARM::MVE_VQRDMLSDHXs32: {
7867 case ARM::MVE_VMULLu32th: {
78767868 if (Operands[3]->getReg() == Operands[4]->getReg()) {
78777869 return Error (Operands[3]->getStartLoc(),
78787870 "Qd register and Qn register can't be identical");
5959 # CHECK-NOFP: vqrdmladhx.s32 q1, q0, q4 @ encoding: [0x20,0xee,0x09,0x3e]
6060 vqrdmladhx.s32 q1, q0, q4
6161
62 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
62 # CHECK: vqrdmladhx.s32 q1, q1, q0 @ encoding: [0x22,0xee,0x01,0x3e]
63 # CHECK-NOFP: vqrdmladhx.s32 q1, q1, q0 @ encoding: [0x22,0xee,0x01,0x3e]
6364 vqrdmladhx.s32 q1, q1, q0
6465
65 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
66 # CHECK: vqrdmladhx.s32 q1, q0, q1 @ encoding: [0x20,0xee,0x03,0x3e]
67 # CHECK-NOFP: vqrdmladhx.s32 q1, q0, q1 @ encoding: [0x20,0xee,0x03,0x3e]
6668 vqrdmladhx.s32 q1, q0, q1
6769
6870 # CHECK: vqrdmladh.s8 q0, q6, q2 @ encoding: [0x0c,0xee,0x05,0x0e]
125127 # CHECK-NOFP: vqrdmlsdh.s32 q0, q6, q7 @ encoding: [0x2c,0xfe,0x0f,0x0e]
126128 vqrdmlsdh.s32 q0, q6, q7
127129
128 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qn register can't be identical
130 # CHECK: vqrdmlsdh.s32 q0, q0, q7 @ encoding: [0x20,0xfe,0x0f,0x0e]
131 # CHECK-NOFP: vqrdmlsdh.s32 q0, q0, q7 @ encoding: [0x20,0xfe,0x0f,0x0e]
129132 vqrdmlsdh.s32 q0, q0, q7
130133
131 # ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: Qd register and Qm register can't be identical
134 # CHECK: vqrdmlsdh.s32 q0, q6, q0 @ encoding: [0x2c,0xfe,0x01,0x0e]
135 # CHECK-NOFP: vqrdmlsdh.s32 q0, q6, q0 @ encoding: [0x2c,0xfe,0x01,0x0e]
132136 vqrdmlsdh.s32 q0, q6, q0
133137
134138 # CHECK: vcmul.f16 q0, q1, q2, #90 @ encoding: [0x32,0xee,0x05,0x0e]