llvm.org GIT mirror llvm / 9ac8aec
[RISCV] Allow conversion of CC logic to bitwise logic Indicates in the TargetLowering interface that conversions from CC logic to bitwise logic are allowed. Adds tests that show the benefit when optimization opportunities are detected. Also adds tests that show that when the optimization is not applied correct code is generated (but opportunities for other optimizations remain). Differential Revision: https://reviews.llvm.org/D59596 Patch by Luís Marques. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356740 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Bradbury 1 year, 8 months ago
2 changed file(s) with 134 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
9797 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
9898 EVT VT) const override;
9999
100 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
101 return VT.isScalarInteger();
102 }
103
100104 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
101105 return isa(I) || isa(I);
102106 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
2 ; RUN: | FileCheck %s -check-prefix=RV32I
3 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
4 ; RUN: | FileCheck %s -check-prefix=RV64I
5
6 define i1 @and_icmp_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
7 ; RV32I-LABEL: and_icmp_eq:
8 ; RV32I: # %bb.0:
9 ; RV32I-NEXT: xor a2, a2, a3
10 ; RV32I-NEXT: xor a0, a0, a1
11 ; RV32I-NEXT: or a0, a0, a2
12 ; RV32I-NEXT: seqz a0, a0
13 ; RV32I-NEXT: ret
14 ;
15 ; RV64I-LABEL: and_icmp_eq:
16 ; RV64I: # %bb.0:
17 ; RV64I-NEXT: xor a2, a2, a3
18 ; RV64I-NEXT: xor a0, a0, a1
19 ; RV64I-NEXT: or a0, a0, a2
20 ; RV64I-NEXT: slli a0, a0, 32
21 ; RV64I-NEXT: srli a0, a0, 32
22 ; RV64I-NEXT: seqz a0, a0
23 ; RV64I-NEXT: ret
24 %cmp1 = icmp eq i32 %a, %b
25 %cmp2 = icmp eq i32 %c, %d
26 %and = and i1 %cmp1, %cmp2
27 ret i1 %and
28 }
29
30 define i1 @or_icmp_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
31 ; RV32I-LABEL: or_icmp_ne:
32 ; RV32I: # %bb.0:
33 ; RV32I-NEXT: xor a2, a2, a3
34 ; RV32I-NEXT: xor a0, a0, a1
35 ; RV32I-NEXT: or a0, a0, a2
36 ; RV32I-NEXT: snez a0, a0
37 ; RV32I-NEXT: ret
38 ;
39 ; RV64I-LABEL: or_icmp_ne:
40 ; RV64I: # %bb.0:
41 ; RV64I-NEXT: xor a2, a2, a3
42 ; RV64I-NEXT: xor a0, a0, a1
43 ; RV64I-NEXT: or a0, a0, a2
44 ; RV64I-NEXT: slli a0, a0, 32
45 ; RV64I-NEXT: srli a0, a0, 32
46 ; RV64I-NEXT: snez a0, a0
47 ; RV64I-NEXT: ret
48 %cmp1 = icmp ne i32 %a, %b
49 %cmp2 = icmp ne i32 %c, %d
50 %or = or i1 %cmp1, %cmp2
51 ret i1 %or
52 }
53
54 define i1 @or_icmps_const_1bit_diff(i64 %x) nounwind {
55 ; RV32I-LABEL: or_icmps_const_1bit_diff:
56 ; RV32I: # %bb.0:
57 ; RV32I-NEXT: addi a2, a0, -13
58 ; RV32I-NEXT: sltu a0, a2, a0
59 ; RV32I-NEXT: add a0, a1, a0
60 ; RV32I-NEXT: addi a0, a0, -1
61 ; RV32I-NEXT: andi a1, a2, -5
62 ; RV32I-NEXT: or a0, a1, a0
63 ; RV32I-NEXT: seqz a0, a0
64 ; RV32I-NEXT: ret
65 ;
66 ; RV64I-LABEL: or_icmps_const_1bit_diff:
67 ; RV64I: # %bb.0:
68 ; RV64I-NEXT: addi a0, a0, -13
69 ; RV64I-NEXT: andi a0, a0, -5
70 ; RV64I-NEXT: seqz a0, a0
71 ; RV64I-NEXT: ret
72 %a = icmp eq i64 %x, 17
73 %b = icmp eq i64 %x, 13
74 %r = or i1 %a, %b
75 ret i1 %r
76 }
77
78 define i1 @and_icmps_const_1bit_diff(i32 %x) nounwind {
79 ; RV32I-LABEL: and_icmps_const_1bit_diff:
80 ; RV32I: # %bb.0:
81 ; RV32I-NEXT: addi a0, a0, -44
82 ; RV32I-NEXT: andi a0, a0, -17
83 ; RV32I-NEXT: snez a0, a0
84 ; RV32I-NEXT: ret
85 ;
86 ; RV64I-LABEL: and_icmps_const_1bit_diff:
87 ; RV64I: # %bb.0:
88 ; RV64I-NEXT: addi a0, a0, -44
89 ; RV64I-NEXT: addi a1, zero, 1
90 ; RV64I-NEXT: slli a1, a1, 32
91 ; RV64I-NEXT: addi a1, a1, -17
92 ; RV64I-NEXT: and a0, a0, a1
93 ; RV64I-NEXT: snez a0, a0
94 ; RV64I-NEXT: ret
95 %a = icmp ne i32 %x, 44
96 %b = icmp ne i32 %x, 60
97 %r = and i1 %a, %b
98 ret i1 %r
99 }
100
101 define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind {
102 ; RV32I-LABEL: and_icmps_const_not1bit_diff:
103 ; RV32I: # %bb.0:
104 ; RV32I-NEXT: addi a1, zero, 44
105 ; RV32I-NEXT: xor a1, a0, a1
106 ; RV32I-NEXT: addi a2, zero, 92
107 ; RV32I-NEXT: xor a0, a0, a2
108 ; RV32I-NEXT: snez a0, a0
109 ; RV32I-NEXT: snez a1, a1
110 ; RV32I-NEXT: and a0, a1, a0
111 ; RV32I-NEXT: ret
112 ;
113 ; RV64I-LABEL: and_icmps_const_not1bit_diff:
114 ; RV64I: # %bb.0:
115 ; RV64I-NEXT: slli a0, a0, 32
116 ; RV64I-NEXT: srli a0, a0, 32
117 ; RV64I-NEXT: addi a1, zero, 44
118 ; RV64I-NEXT: xor a1, a0, a1
119 ; RV64I-NEXT: addi a2, zero, 92
120 ; RV64I-NEXT: xor a0, a0, a2
121 ; RV64I-NEXT: snez a0, a0
122 ; RV64I-NEXT: snez a1, a1
123 ; RV64I-NEXT: and a0, a1, a0
124 ; RV64I-NEXT: ret
125 %a = icmp ne i32 %x, 44
126 %b = icmp ne i32 %x, 92
127 %r = and i1 %a, %b
128 ret i1 %r
129 }