llvm.org GIT mirror llvm / 9a23576
[NFC][InstCombine] Redundant masking before left-shift: tests with assume If the legality check is `(shiftNbits-maskNbits) s>= 0`, then we can simplify it to `shiftNbits u>= maskNbits`, which is easier to check for. However, currently switching the `dropRedundantMaskingOfLeftShiftInput()` to `SimplifyICmpInst()` does not catch these cases and regresses currently-handled cases, so i'll leave it as is for now. https://rise4fun.com/Alive/25P git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366564 91177308-0d34-0410-b5e6-96231b3b80d8 Roman Lebedev a month ago
4 changed file(s) with 130 addition(s) and 22 deletion(s). Raw diff Collapse all Expand all
236236 ret i32 %t2
237237 }
238238
239 ; Special test
240
241 declare void @llvm.assume(i1 %cond)
242
243 ; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
244 define i32 @t11_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
245 ; CHECK-LABEL: @t11_assume_uge(
246 ; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
247 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
248 ; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[MASKNBITS]]
249 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
250 ; CHECK-NEXT: call void @use32(i32 [[T0]])
251 ; CHECK-NEXT: call void @use32(i32 [[T1]])
252 ; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[SHIFTNBITS]]
253 ; CHECK-NEXT: ret i32 [[T2]]
254 ;
255 %cmp = icmp uge i32 %shiftnbits, %masknbits
256 call void @llvm.assume(i1 %cmp)
257 %t0 = lshr i32 -1, %masknbits
258 %t1 = and i32 %t0, %x
259 call void @use32(i32 %t0)
260 call void @use32(i32 %t1)
261 %t2 = shl i32 %t1, %shiftnbits
262 ret i32 %t2
263 }
264
239265 ; Negative tests
240266
241 define i32 @n11_not_minus_one(i32 %x, i32 %nbits) {
242 ; CHECK-LABEL: @n11_not_minus_one(
267 define i32 @n12_not_minus_one(i32 %x, i32 %nbits) {
268 ; CHECK-LABEL: @n12_not_minus_one(
243269 ; CHECK-NEXT: [[T0:%.*]] = lshr i32 -2, [[NBITS:%.*]]
244270 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
245271 ; CHECK-NEXT: call void @use32(i32 [[T0]])
255281 ret i32 %t2
256282 }
257283
258 define i32 @n12_shamt_is_smaller(i32 %x, i32 %nbits) {
259 ; CHECK-LABEL: @n12_shamt_is_smaller(
284 define i32 @n13_shamt_is_smaller(i32 %x, i32 %nbits) {
285 ; CHECK-LABEL: @n13_shamt_is_smaller(
260286 ; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
261287 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
262288 ; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
287287 ret i32 %t3
288288 }
289289
290 ; Special test
291
292 declare void @llvm.assume(i1 %cond)
293
294 ; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
295 define i32 @t11_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
296 ; CHECK-LABEL: @t11_assume_uge(
297 ; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
298 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
299 ; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[MASKNBITS]]
300 ; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[MASKNBITS]]
301 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
302 ; CHECK-NEXT: call void @use32(i32 [[T0]])
303 ; CHECK-NEXT: call void @use32(i32 [[T1]])
304 ; CHECK-NEXT: call void @use32(i32 [[T2]])
305 ; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[SHIFTNBITS]]
306 ; CHECK-NEXT: ret i32 [[T4]]
307 ;
308 %cmp = icmp uge i32 %shiftnbits, %masknbits
309 call void @llvm.assume(i1 %cmp)
310 %t0 = shl i32 -1, %masknbits
311 %t1 = lshr i32 %t0, %masknbits
312 %t2 = and i32 %t1, %x
313 call void @use32(i32 %t0)
314 call void @use32(i32 %t1)
315 call void @use32(i32 %t2)
316 %t4 = shl i32 %t2, %shiftnbits
317 ret i32 %t4
318 }
319
290320 ; Negative tests
291321
292 define i32 @n11_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
293 ; CHECK-LABEL: @n11_different_shamts0(
322 define i32 @n12_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
323 ; CHECK-LABEL: @n12_different_shamts0(
294324 ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
295325 ; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
296326 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X]]
310340 ret i32 %t3
311341 }
312342
313 define i32 @n12_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
314 ; CHECK-LABEL: @n12_different_shamts1(
343 define i32 @n13_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
344 ; CHECK-LABEL: @n13_different_shamts1(
315345 ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
316346 ; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
317347 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X]]
331361 ret i32 %t3
332362 }
333363
334 define i32 @n13_shamt_is_smaller(i32 %x, i32 %nbits) {
335 ; CHECK-LABEL: @n13_shamt_is_smaller(
364 define i32 @n14_shamt_is_smaller(i32 %x, i32 %nbits) {
365 ; CHECK-LABEL: @n14_shamt_is_smaller(
336366 ; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
337367 ; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
338368 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
172172 ret i32 %t2
173173 }
174174
175 ; Special test
176
177 declare void @llvm.assume(i1 %cond)
178
179 ; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
180 define i32 @t8_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
181 ; CHECK-LABEL: @t8_assume_uge(
182 ; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
183 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
184 ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[MASKNBITS]]
185 ; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[MASKNBITS]]
186 ; CHECK-NEXT: call void @use32(i32 [[T0]])
187 ; CHECK-NEXT: call void @use32(i32 [[T1]])
188 ; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[SHIFTNBITS]]
189 ; CHECK-NEXT: ret i32 [[T2]]
190 ;
191 %cmp = icmp uge i32 %shiftnbits, %masknbits
192 call void @llvm.assume(i1 %cmp)
193 %t0 = shl i32 %x, %masknbits
194 %t1 = lshr i32 %t0, %masknbits
195 call void @use32(i32 %t0)
196 call void @use32(i32 %t1)
197 %t2 = shl i32 %t1, %shiftnbits
198 ret i32 %t2
199 }
200
175201 ; Negative tests
176202
177 define i32 @n8_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
178 ; CHECK-LABEL: @n8_different_shamts0(
203 define i32 @n9_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
204 ; CHECK-LABEL: @n9_different_shamts0(
179205 ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
180206 ; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
181207 ; CHECK-NEXT: call void @use32(i32 [[T0]])
191217 ret i32 %t2
192218 }
193219
194 define i32 @n9_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
195 ; CHECK-LABEL: @n9_different_shamts1(
220 define i32 @n10_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
221 ; CHECK-LABEL: @n10_different_shamts1(
196222 ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
197223 ; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
198224 ; CHECK-NEXT: call void @use32(i32 [[T0]])
208234 ret i32 %t2
209235 }
210236
211 define i32 @n10_shamt_is_smaller(i32 %x, i32 %nbits) {
212 ; CHECK-LABEL: @n10_shamt_is_smaller(
237 define i32 @n11_shamt_is_smaller(i32 %x, i32 %nbits) {
238 ; CHECK-LABEL: @n11_shamt_is_smaller(
213239 ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
214240 ; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
215241 ; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
172172 ret i32 %t2
173173 }
174174
175 ; Special test
176
177 declare void @llvm.assume(i1 %cond)
178
179 ; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
180 define i32 @t8_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
181 ; CHECK-LABEL: @t8_assume_uge(
182 ; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
183 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
184 ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[MASKNBITS]]
185 ; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[MASKNBITS]]
186 ; CHECK-NEXT: call void @use32(i32 [[T0]])
187 ; CHECK-NEXT: call void @use32(i32 [[T1]])
188 ; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[SHIFTNBITS]]
189 ; CHECK-NEXT: ret i32 [[T2]]
190 ;
191 %cmp = icmp uge i32 %shiftnbits, %masknbits
192 call void @llvm.assume(i1 %cmp)
193 %t0 = shl i32 %x, %masknbits
194 %t1 = ashr i32 %t0, %masknbits
195 call void @use32(i32 %t0)
196 call void @use32(i32 %t1)
197 %t2 = shl i32 %t1, %shiftnbits
198 ret i32 %t2
199 }
200
175201 ; Negative tests
176202
177 define i32 @n8_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
178 ; CHECK-LABEL: @n8_different_shamts0(
203 define i32 @n9_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
204 ; CHECK-LABEL: @n9_different_shamts0(
179205 ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
180206 ; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS1:%.*]]
181207 ; CHECK-NEXT: call void @use32(i32 [[T0]])
191217 ret i32 %t2
192218 }
193219
194 define i32 @n9_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
195 ; CHECK-LABEL: @n9_different_shamts1(
220 define i32 @n10_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
221 ; CHECK-LABEL: @n10_different_shamts1(
196222 ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
197223 ; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS1:%.*]]
198224 ; CHECK-NEXT: call void @use32(i32 [[T0]])
208234 ret i32 %t2
209235 }
210236
211 define i32 @n10_shamt_is_smaller(i32 %x, i32 %nbits) {
212 ; CHECK-LABEL: @n10_shamt_is_smaller(
237 define i32 @n11_shamt_is_smaller(i32 %x, i32 %nbits) {
238 ; CHECK-LABEL: @n11_shamt_is_smaller(
213239 ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
214240 ; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
215241 ; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1