llvm.org GIT mirror llvm / 9a1ceae
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 11 years ago
31 changed file(s) with 156 addition(s) and 159 deletion(s). Raw diff Collapse all Expand all
270270 if (!Modifier || strcmp(Modifier, "no_hash") != 0)
271271 O << "#";
272272
273 O << (int)MO.getImmedValue();
273 O << (int)MO.getImm();
274274 break;
275275 }
276276 case MachineOperand::MO_MachineBasicBlock:
350350 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
351351 const MachineOperand &MO = MI->getOperand(OpNum);
352352 assert(MO.isImmediate() && "Not a valid so_imm value!");
353 printSOImm(O, MO.getImmedValue(), TAI);
353 printSOImm(O, MO.getImm(), TAI);
354354 }
355355
356356 /// printSOImm2PartOperand - SOImm is broken into two pieces using a mov
358358 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
359359 const MachineOperand &MO = MI->getOperand(OpNum);
360360 assert(MO.isImmediate() && "Not a valid so_imm value!");
361 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImmedValue());
362 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImmedValue());
361 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
362 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
363363 printSOImm(O, ARM_AM::getSOImmVal(V1), TAI);
364364 O << "\n\torr";
365365 printPredicateOperand(MI, 2);
386386
387387 // Print the shift opc.
388388 O << ", "
389 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImmedValue()))
389 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
390390 << " ";
391391
392392 if (MO2.getReg()) {
425425
426426 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
427427 O << ", "
428 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImmedValue()))
428 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
429429 << " #" << ShImm;
430430 O << "]";
431431 }
448448
449449 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
450450 O << ", "
451 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImmedValue()))
451 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
452452 << " #" << ShImm;
453453 }
454454
616616 }
617617
618618 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int opNum) {
619 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(opNum).getImmedValue();
619 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(opNum).getImm();
620620 if (CC != ARMCC::AL)
621621 O << ARMCondCodeToString(CC);
622622 }
630630 }
631631
632632 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int opNum) {
633 int Id = (int)MI->getOperand(opNum).getImmedValue();
633 int Id = (int)MI->getOperand(opNum).getImm();
634634 O << TAI->getPrivateGlobalPrefix() << "PC" << Id;
635635 }
636636
676676 const MachineOperand &MO2 = MI->getOperand(OpNo+1); // Unique Id
677677 unsigned JTI = MO1.getJumpTableIndex();
678678 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
679 << '_' << JTI << '_' << MO2.getImmedValue() << ":\n";
679 << '_' << JTI << '_' << MO2.getImm() << ":\n";
680680
681681 const char *JTEntryDirective = TAI->getJumpTableDirective();
682682 if (!JTEntryDirective)
691691 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
692692 MachineBasicBlock *MBB = JTBBs[i];
693693 if (UseSet && JTSets.insert(MBB).second)
694 printPICJumpTableSetLabel(JTI, MO2.getImmedValue(), MBB);
694 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
695695
696696 O << JTEntryDirective << ' ';
697697 if (UseSet)
698698 O << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
699 << '_' << JTI << '_' << MO2.getImmedValue()
699 << '_' << JTI << '_' << MO2.getImm()
700700 << "_set_" << MBB->getNumber();
701701 else if (TM.getRelocationModel() == Reloc::PIC_) {
702702 printBasicBlockLabel(MBB, false, false);
703703 // If the arch uses custom Jump Table directives, don't calc relative to JT
704704 if (!TAI->getJumpTableDirective())
705705 O << '-' << TAI->getPrivateGlobalPrefix() << "JTI"
706 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImmedValue();
706 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
707707 } else
708708 printBasicBlockLabel(MBB, false, false);
709709 if (i != e-1)
110110 /// machine operand.
111111 int Emitter::getShiftOp(const MachineOperand &MO) {
112112 unsigned ShiftOp = 0x0;
113 switch(ARM_AM::getAM2ShiftOpc(MO.getImmedValue())) {
113 switch(ARM_AM::getAM2ShiftOpc(MO.getImm())) {
114114 default: assert(0 && "Unknown shift opc!");
115115 case ARM_AM::asr:
116116 ShiftOp = 0X2;
136136 assert(MRegisterInfo::isPhysicalRegister(MO.getReg()));
137137 rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
138138 } else if (MO.isImmediate()) {
139 rv = MO.getImmedValue();
139 rv = MO.getImm();
140140 } else if (MO.isGlobalAddress()) {
141141 emitGlobalAddressForCall(MO.getGlobal(), false);
142142 } else if (MO.isExternalSymbol()) {
411411 Value |= 1 << ARMII::I_BitShift;
412412 // set immed_8 field
413413 const MachineOperand &MO = MI.getOperand(OperandIndex);
414 op = ARM_AM::getSOImmVal(MO.getImmedValue());
414 op = ARM_AM::getSOImmVal(MO.getImm());
415415 Value |= op;
416416
417417 break;
440440 // LSR - 011 if it is in register shifts encoding; 010, otherwise.
441441 // ROR - 111 if it is in register shifts encoding; 110, otherwise.
442442 // RRX - 110 and bit[11:7] clear.
443 switch(ARM_AM::getSORegShOp(MO2.getImmedValue())) {
443 switch(ARM_AM::getSORegShOp(MO2.getImm())) {
444444 default: assert(0 && "Unknown shift opc!");
445445 case ARM_AM::asr: {
446446 if(IsShiftByRegister)
474474 }
475475 }
476476 // set the field related to shift operations (except rrx).
477 if(ARM_AM::getSORegShOp(MO2.getImmedValue()) != ARM_AM::rrx)
477 if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx)
478478 if(IsShiftByRegister) {
479479 // set the value of bit[11:8] (register Rs).
480480 assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));
11871187 // bge L2
11881188 // b L1
11891189 // L2:
1190 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImmedValue();
1190 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm();
11911191 CC = ARMCC::getOppositeCondition(CC);
11921192 unsigned CCReg = MI->getOperand(2).getReg();
11931193
6969 MI->getOperand(2).isRegister() &&
7070 MI->getOperand(3).isImmediate() &&
7171 MI->getOperand(2).getReg() == 0 &&
72 MI->getOperand(3).getImmedValue() == 0) {
72 MI->getOperand(3).getImm() == 0) {
7373 FrameIndex = MI->getOperand(1).getFrameIndex();
7474 return MI->getOperand(0).getReg();
7575 }
7878 case ARM::FLDS:
7979 if (MI->getOperand(1).isFrameIndex() &&
8080 MI->getOperand(2).isImmediate() &&
81 MI->getOperand(2).getImmedValue() == 0) {
81 MI->getOperand(2).getImm() == 0) {
8282 FrameIndex = MI->getOperand(1).getFrameIndex();
8383 return MI->getOperand(0).getReg();
8484 }
8686 case ARM::tRestore:
8787 if (MI->getOperand(1).isFrameIndex() &&
8888 MI->getOperand(2).isImmediate() &&
89 MI->getOperand(2).getImmedValue() == 0) {
89 MI->getOperand(2).getImm() == 0) {
9090 FrameIndex = MI->getOperand(1).getFrameIndex();
9191 return MI->getOperand(0).getReg();
9292 }
103103 MI->getOperand(2).isRegister() &&
104104 MI->getOperand(3).isImmediate() &&
105105 MI->getOperand(2).getReg() == 0 &&
106 MI->getOperand(3).getImmedValue() == 0) {
106 MI->getOperand(3).getImm() == 0) {
107107 FrameIndex = MI->getOperand(1).getFrameIndex();
108108 return MI->getOperand(0).getReg();
109109 }
112112 case ARM::FSTS:
113113 if (MI->getOperand(1).isFrameIndex() &&
114114 MI->getOperand(2).isImmediate() &&
115 MI->getOperand(2).getImmedValue() == 0) {
115 MI->getOperand(2).getImm() == 0) {
116116 FrameIndex = MI->getOperand(1).getFrameIndex();
117117 return MI->getOperand(0).getReg();
118118 }
120120 case ARM::tSpill:
121121 if (MI->getOperand(1).isFrameIndex() &&
122122 MI->getOperand(2).isImmediate() &&
123 MI->getOperand(2).getImmedValue() == 0) {
123 MI->getOperand(2).getImm() == 0) {
124124 FrameIndex = MI->getOperand(1).getFrameIndex();
125125 return MI->getOperand(0).getReg();
126126 }
460460
461461 bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
462462 int PIdx = MI->findFirstPredOperandIdx();
463 return PIdx != -1 && MI->getOperand(PIdx).getImmedValue() != ARMCC::AL;
463 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
464464 }
465465
466466 bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
476476 int PIdx = MI->findFirstPredOperandIdx();
477477 if (PIdx != -1) {
478478 MachineOperand &PMO = MI->getOperand(PIdx);
479 PMO.setImm(Pred[0].getImmedValue());
479 PMO.setImm(Pred[0].getImm());
480480 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
481481 return true;
482482 }
489489 if (Pred1.size() > 2 || Pred2.size() > 2)
490490 return false;
491491
492 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImmedValue();
493 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImmedValue();
492 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
493 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
494494 if (CC1 == CC2)
495495 return true;
496496
254254 }
255255
256256 PredReg = MI->getOperand(PIdx+1).getReg();
257 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImmedValue();
257 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
258258 }
259259
260260 static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
320320 const MachineInstr *Orig) const {
321321 if (Orig->getOpcode() == ARM::MOVi2pieces) {
322322 emitLoadConstPool(MBB, I, DestReg,
323 Orig->getOperand(1).getImmedValue(),
324 (ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(),
323 Orig->getOperand(1).getImm(),
324 (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
325325 Orig->getOperand(3).getReg(),
326326 TII, false);
327327 return;
359359 if (MI->getOperand(4).getReg() == ARM::CPSR)
360360 // If it is updating CPSR, then it cannot be foled.
361361 break;
362 unsigned Pred = MI->getOperand(2).getImmedValue();
362 unsigned Pred = MI->getOperand(2).getImm();
363363 unsigned PredReg = MI->getOperand(3).getReg();
364364 if (OpNum == 0) { // move -> store
365365 unsigned SrcReg = MI->getOperand(1).getReg();
391391 break;
392392 }
393393 case ARM::FCPYS: {
394 unsigned Pred = MI->getOperand(2).getImmedValue();
394 unsigned Pred = MI->getOperand(2).getImm();
395395 unsigned PredReg = MI->getOperand(3).getReg();
396396 if (OpNum == 0) { // move -> store
397397 unsigned SrcReg = MI->getOperand(1).getReg();
405405 break;
406406 }
407407 case ARM::FCPYD: {
408 unsigned Pred = MI->getOperand(2).getImmedValue();
408 unsigned Pred = MI->getOperand(2).getImm();
409409 unsigned PredReg = MI->getOperand(3).getReg();
410410 if (OpNum == 0) { // move -> store
411411 unsigned SrcReg = MI->getOperand(1).getReg();
791791 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
792792 // ADJCALLSTACKUP -> add, sp, sp, amount
793793 MachineInstr *Old = I;
794 unsigned Amount = Old->getOperand(0).getImmedValue();
794 unsigned Amount = Old->getOperand(0).getImm();
795795 if (Amount != 0) {
796796 ARMFunctionInfo *AFI = MF.getInfo();
797797 // We need to keep the stack aligned properly. To do this, we round the
804804 unsigned Opc = Old->getOpcode();
805805 bool isThumb = AFI->isThumbFunction();
806806 ARMCC::CondCodes Pred = isThumb
807 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue();
807 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImm();
808808 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
809809 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
810810 unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
11591159 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
11601160 int PIdx = MI.findFirstPredOperandIdx();
11611161 ARMCC::CondCodes Pred = (PIdx == -1)
1162 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue();
1162 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
11631163 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
11641164 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
11651165 isSub ? -Offset : Offset, Pred, PredReg, TII);
7777 assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
7878 O << TM.getRegisterInfo()->get(MO.getReg()).Name;
7979 } else if (MO.isImmediate()) {
80 O << MO.getImmedValue();
81 assert(MO.getImmedValue() < (1 << 30));
80 O << MO.getImm();
81 assert(MO.getImm() < (1 << 30));
8282 } else {
8383 printOp(MO);
8484 }
150150 if (MO.isRegister()) {
151151 rv = getAlphaRegNumber(MO.getReg());
152152 } else if (MO.isImmediate()) {
153 rv = MO.getImmedValue();
153 rv = MO.getImm();
154154 } else if (MO.isGlobalAddress() || MO.isExternalSymbol()
155155 || MO.isConstantPoolIndex()) {
156156 DOUT << MO << " is a relocated op for " << MI << "\n";
186186 case Alpha::LDAg:
187187 case Alpha::LDAHg:
188188 Reloc = Alpha::reloc_gpdist;
189 Offset = MI.getOperand(3).getImmedValue();
189 Offset = MI.getOperand(3).getImm();
190190 break;
191191 default:
192192 assert(0 && "unknown relocatable instruction");
194194 }
195195 if (MO.isGlobalAddress())
196196 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
197 Reloc, MO.getGlobal(), Offset,
198 false, useGOT));
197 Reloc, MO.getGlobal(), Offset,
198 false, useGOT));
199199 else if (MO.isExternalSymbol())
200200 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
201 Reloc, MO.getSymbolName(), Offset,
202 true));
201 Reloc, MO.getSymbolName(),
202 Offset, true));
203203 else
204204 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
205205 Reloc, MO.getConstantPoolIndex(),
6666 case Alpha::STW: case Alpha::STB:
6767 case Alpha::STT: case Alpha::STS:
6868 if (MI->getOperand(2).getReg() == Alpha::R30) {
69 if (prev[0]
70 && prev[0]->getOperand(2).getReg() ==
71 MI->getOperand(2).getReg()
72 && prev[0]->getOperand(1).getImmedValue() ==
73 MI->getOperand(1).getImmedValue()) {
69 if (prev[0] &&
70 prev[0]->getOperand(2).getReg() == MI->getOperand(2).getReg()&&
71 prev[0]->getOperand(1).getImm() == MI->getOperand(1).getImm()){
7472 prev[0] = prev[1];
7573 prev[1] = prev[2];
7674 prev[2] = 0;
8280 } else if (prev[1]
8381 && prev[1]->getOperand(2).getReg() ==
8482 MI->getOperand(2).getReg()
85 && prev[1]->getOperand(1).getImmedValue() ==
86 MI->getOperand(1).getImmedValue()) {
83 && prev[1]->getOperand(1).getImm() ==
84 MI->getOperand(1).getImm()) {
8785 prev[0] = prev[2];
8886 prev[1] = prev[2] = 0;
8987 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
9795 } else if (prev[2]
9896 && prev[2]->getOperand(2).getReg() ==
9997 MI->getOperand(2).getReg()
100 && prev[2]->getOperand(1).getImmedValue() ==
101 MI->getOperand(1).getImmedValue()) {
98 && prev[2]->getOperand(1).getImm() ==
99 MI->getOperand(1).getImm()) {
102100 prev[0] = prev[1] = prev[2] = 0;
103101 BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
104102 .addReg(Alpha::R31);
279279 // 'sub ESP, ' and the adjcallstackdown instruction into 'add ESP,
280280 // '
281281 MachineInstr *Old = I;
282 uint64_t Amount = Old->getOperand(0).getImmedValue();
282 uint64_t Amount = Old->getOperand(0).getImm();
283283 if (Amount != 0) {
284284 // We need to keep the stack aligned properly. To do this, we round the
285285 // amount of space needed for the outgoing arguments up to the next
8282 assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
8383 O << TM.getRegisterInfo()->get(MO.getReg()).Name;
8484 } else if (MO.isImmediate()) {
85 O << MO.getImmedValue();
85 O << MO.getImm();
8686 } else {
8787 printOp(MO);
8888 }
9797 void
9898 printS7ImmOperand(const MachineInstr *MI, unsigned OpNo)
9999 {
100 int value = MI->getOperand(OpNo).getImmedValue();
100 int value = MI->getOperand(OpNo).getImm();
101101 value = (value << (32 - 7)) >> (32 - 7);
102102
103103 assert((value >= -(1 << 8) && value <= (1 << 7) - 1)
108108 void
109109 printU7ImmOperand(const MachineInstr *MI, unsigned OpNo)
110110 {
111 unsigned int value = MI->getOperand(OpNo).getImmedValue();
111 unsigned int value = MI->getOperand(OpNo).getImm();
112112 assert(value < (1 << 8) && "Invalid u7 argument");
113113 O << value;
114114 }
116116 void
117117 printMemRegImmS7(const MachineInstr *MI, unsigned OpNo)
118118 {
119 char value = MI->getOperand(OpNo).getImmedValue();
119 char value = MI->getOperand(OpNo).getImm();
120120 O << (int) value;
121121 O << "(";
122122 printOperand(MI, OpNo+1);
126126 void
127127 printS16ImmOperand(const MachineInstr *MI, unsigned OpNo)
128128 {
129 O << (short) MI->getOperand(OpNo).getImmedValue();
129 O << (short) MI->getOperand(OpNo).getImm();
130130 }
131131
132132 void
133133 printU16ImmOperand(const MachineInstr *MI, unsigned OpNo)
134134 {
135 O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
135 O << (unsigned short)MI->getOperand(OpNo).getImm();
136136 }
137137
138138 void
139139 printU32ImmOperand(const MachineInstr *MI, unsigned OpNo)
140140 {
141 O << (unsigned)MI->getOperand(OpNo).getImmedValue();
141 O << (unsigned)MI->getOperand(OpNo).getImm();
142142 }
143143
144144 void
155155 void
156156 printU18ImmOperand(const MachineInstr *MI, unsigned OpNo)
157157 {
158 unsigned int value = MI->getOperand(OpNo).getImmedValue();
158 unsigned int value = MI->getOperand(OpNo).getImm();
159159 assert(value <= (1 << 19) - 1 && "Invalid u18 argument");
160160 O << value;
161161 }
163163 void
164164 printS10ImmOperand(const MachineInstr *MI, unsigned OpNo)
165165 {
166 short value = (short) (((int) MI->getOperand(OpNo).getImmedValue() << 16)
166 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
167167 >> 16);
168168 assert((value >= -(1 << 9) && value <= (1 << 9) - 1)
169169 && "Invalid s10 argument");
173173 void
174174 printU10ImmOperand(const MachineInstr *MI, unsigned OpNo)
175175 {
176 short value = (short) (((int) MI->getOperand(OpNo).getImmedValue() << 16)
176 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
177177 >> 16);
178178 assert((value <= (1 << 10) - 1) && "Invalid u10 argument");
179179 O << value;
237237
238238 void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
239239 if (MI->getOperand(OpNo).isImmediate()) {
240 int value = (int) MI->getOperand(OpNo).getImmedValue();
240 int value = (int) MI->getOperand(OpNo).getImm();
241241 assert((value >= 0 && value < 16)
242242 && "Invalid negated immediate rotate 7-bit argument");
243243 O << -value;
244244 } else {
245 assert(0 && "Invalid/non-immediate rotate amount in printRotateNeg7Imm");
245 assert(0 &&"Invalid/non-immediate rotate amount in printRotateNeg7Imm");
246246 }
247247 }
248248
249249 void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
250250 if (MI->getOperand(OpNo).isImmediate()) {
251 int value = (int) MI->getOperand(OpNo).getImmedValue();
251 int value = (int) MI->getOperand(OpNo).getImm();
252252 assert((value >= 0 && value < 32)
253253 && "Invalid negated immediate rotate 7-bit argument");
254254 O << -value;
255255 } else {
256 assert(0 && "Invalid/non-immediate rotate amount in printRotateNeg7Imm");
256 assert(0 &&"Invalid/non-immediate rotate amount in printRotateNeg7Imm");
257257 }
258258 }
259259
6363 MI.getOperand(1).isRegister() &&
6464 MI.getOperand(2).isImmediate() &&
6565 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
66 if (MI.getOperand(2).getImmedValue() == 0) {
66 if (MI.getOperand(2).getImm() == 0) {
6767 sourceReg = MI.getOperand(1).getReg();
6868 destReg = MI.getOperand(0).getReg();
6969 return true;
7676 (MI.getOperand(1).isRegister() ||
7777 MI.getOperand(1).isFrameIndex()) &&
7878 (MI.getOperand(2).isImmediate() &&
79 MI.getOperand(2).getImmedValue() == 0)) {
79 MI.getOperand(2).getImm() == 0)) {
8080 sourceReg = MI.getOperand(1).getReg();
8181 destReg = MI.getOperand(0).getReg();
8282 return true;
136136 case SPU::LQXr64:
137137 case SPU::LQXr32:
138138 case SPU::LQXr16:
139 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
139 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
140140 MI->getOperand(2).isFrameIndex()) {
141141 FrameIndex = MI->getOperand(2).getFrameIndex();
142142 return MI->getOperand(0).getReg();
170170 case SPU::STQXr32:
171171 case SPU::STQXr16:
172172 // case SPU::STQXr8:
173 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
173 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
174174 MI->getOperand(2).isFrameIndex()) {
175175 FrameIndex = MI->getOperand(2).getFrameIndex();
176176 return MI->getOperand(0).getReg();
262262 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
263263 MachineOperand &MO = Addr[i];
264264 if (MO.isRegister())
265 MIB.addReg(MO.getReg());
265 MIB.addReg(MO.getReg());
266266 else if (MO.isImmediate())
267 MIB.addImm(MO.getImmedValue());
267 MIB.addImm(MO.getImm());
268268 else
269 MIB.addFrameIndex(MO.getFrameIndex());
269 MIB.addFrameIndex(MO.getFrameIndex());
270270 }
271271 NewMIs.push_back(MIB);
272272 }
348348 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
349349 MachineOperand &MO = Addr[i];
350350 if (MO.isRegister())
351 MIB.addReg(MO.getReg());
351 MIB.addReg(MO.getReg());
352352 else if (MO.isImmediate())
353 MIB.addImm(MO.getImmedValue());
353 MIB.addImm(MO.getImm());
354354 else
355 MIB.addFrameIndex(MO.getFrameIndex());
355 MIB.addFrameIndex(MO.getFrameIndex());
356356 }
357357 NewMIs.push_back(MIB);
358358 }
609609 MachineOperand &MO = MI.getOperand(OpNo);
610610
611611 // Offset is biased by $lr's slot at the bottom.
612 Offset += MO.getImmedValue() + MFI->getStackSize()
613 + SPUFrameInfo::minStackSize();
612 Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize();
614613 assert((Offset & 0xf) == 0
615 && "16-byte alignment violated in SPURegisterInfo::eliminateFrameIndex");
614 && "16-byte alignment violated in eliminateFrameIndex");
616615
617616 // Replace the FrameIndex with base register with $sp (aka $r1)
618617 SPOp.ChangeToRegister(SPU::R1, false);
6161 }
6262
6363 void printS8ImmOperand(const MachineInstr *MI, unsigned OpNo) {
64 int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
64 int val=(unsigned int)MI->getOperand(OpNo).getImm();
6565 if(val>=128) val=val-256; // if negative, flip sign
6666 O << val;
6767 }
6868 void printS14ImmOperand(const MachineInstr *MI, unsigned OpNo) {
69 int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
69 int val=(unsigned int)MI->getOperand(OpNo).getImm();
7070 if(val>=8192) val=val-16384; // if negative, flip sign
7171 O << val;
7272 }
7373 void printS22ImmOperand(const MachineInstr *MI, unsigned OpNo) {
74 int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
74 int val=(unsigned int)MI->getOperand(OpNo).getImm();
7575 if(val>=2097152) val=val-4194304; // if negative, flip sign
7676 O << val;
7777 }
7878 void printU64ImmOperand(const MachineInstr *MI, unsigned OpNo) {
79 O << (uint64_t)MI->getOperand(OpNo).getImmedValue();
79 O << (uint64_t)MI->getOperand(OpNo).getImm();
8080 }
8181 void printS64ImmOperand(const MachineInstr *MI, unsigned OpNo) {
8282 // XXX : nasty hack to avoid GPREL22 "relocation truncated to fit" linker
8989 // If it's an immediate, print it the old fashioned way. If it's
9090 // not, we print it as a constant pool index.
9191 if(MI->getOperand(OpNo).isImmediate()) {
92 O << (int64_t)MI->getOperand(OpNo).getImmedValue();
92 O << (int64_t)MI->getOperand(OpNo).getImm();
9393 } else { // this is a constant pool reference: FIXME: assert this
9494 printOp(MI->getOperand(OpNo));
9595 }
171171 return;
172172
173173 case MachineOperand::MO_Immediate:
174 O << MO.getImmedValue();
174 O << MO.getImm();
175175 return;
176176 case MachineOperand::MO_MachineBasicBlock:
177177 printBasicBlockLabel(MO.getMachineBasicBlock());
8383 if (MO.isRegister())
8484 MIB.addReg(MO.getReg());
8585 else if (MO.isImmediate())
86 MIB.addImm(MO.getImmedValue());
86 MIB.addImm(MO.getImm());
8787 else
8888 MIB.addFrameIndex(MO.getFrameIndex());
8989 }
135135 if (MO.isRegister())
136136 MIB.addReg(MO.getReg());
137137 else if (MO.isImmediate())
138 MIB.addImm(MO.getImmedValue());
138 MIB.addImm(MO.getImm());
139139 else
140140 MIB.addFrameIndex(MO.getFrameIndex());
141141 }
219219 // 'sub SP, ' and the adjcallstackdown instruction into 'add SP,
220220 // '
221221 MachineInstr *Old = I;
222 unsigned Amount = Old->getOperand(0).getImmedValue();
222 unsigned Amount = Old->getOperand(0).getImm();
223223 if (Amount != 0) {
224224 // We need to keep the stack aligned properly. To do this, we round the
225225 // amount of space needed for the outgoing arguments up to the next
373373 case MachineOperand::MO_Immediate:
374374 if ((MI->getOpcode() == Mips::SLTiu) || (MI->getOpcode() == Mips::ORi) ||
375375 (MI->getOpcode() == Mips::LUi) || (MI->getOpcode() == Mips::ANDi))
376 O << (unsigned short int)MO.getImmedValue();
376 O << (unsigned short int)MO.getImm();
377377 else
378 O << (short int)MO.getImmedValue();
378 O << (short int)MO.getImm();
379379 break;
380380
381381 case MachineOperand::MO_MachineBasicBlock:
2424 TM(tm), RI(*this) {}
2525
2626 static bool isZeroImm(const MachineOperand &op) {
27 return op.isImmediate() && op.getImmedValue() == 0;
27 return op.isImmediate() && op.getImm() == 0;
2828 }
2929
3030 /// Return true if the instruction is a register to register move and
108108 if (MO.isRegister())
109109 MIB.addReg(MO.getReg());
110110 else if (MO.isImmediate())
111 MIB.addImm(MO.getImmedValue());
111 MIB.addImm(MO.getImm());
112112 else
113113 MIB.addFrameIndex(MO.getFrameIndex());
114114 }
139139 if (MO.isRegister())
140140 MIB.addReg(MO.getReg());
141141 else if (MO.isImmediate())
142 MIB.addImm(MO.getImmedValue());
142 MIB.addImm(MO.getImm());
143143 else
144144 MIB.addFrameIndex(MO.getFrameIndex());
145145 }
123123 if (MO.isRegister()) {
124124 printRegister(MO, false);
125125 } else if (MO.isImmediate()) {
126 O << MO.getImmedValue();
126 O << MO.getImm();
127127 } else {
128128 printOp(MO);
129129 }
136136
137137
138138 void printS5ImmOperand(const MachineInstr *MI, unsigned OpNo) {
139 char value = MI->getOperand(OpNo).getImmedValue();
139 char value = MI->getOperand(OpNo).getImm();
140140 value = (value << (32-5)) >> (32-5);
141141 O << (int)value;
142142 }
143143 void printU5ImmOperand(const MachineInstr *MI, unsigned OpNo) {
144 unsigned char value = MI->getOperand(OpNo).getImmedValue();
144 unsigned char value = MI->getOperand(OpNo).getImm();
145145 assert(value <= 31 && "Invalid u5imm argument!");
146146 O << (unsigned int)value;
147147 }
148148 void printU6ImmOperand(const MachineInstr *MI, unsigned OpNo) {
149 unsigned char value = MI->getOperand(OpNo).getImmedValue();
149 unsigned char value = MI->getOperand(OpNo).getImm();
150150 assert(value <= 63 && "Invalid u6imm argument!");
151151 O << (unsigned int)value;
152152 }
153153 void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo) {
154 O << (short)MI->getOperand(OpNo).getImmedValue();
154 O << (short)MI->getOperand(OpNo).getImm();
155155 }
156156 void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo) {
157 O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
157 O << (unsigned short)MI->getOperand(OpNo).getImm();
158158 }
159159 void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo) {
160160 if (MI->getOperand(OpNo).isImmediate()) {
161 O << (short)(MI->getOperand(OpNo).getImmedValue()*4);
161 O << (short)(MI->getOperand(OpNo).getImm()*4);
162162 } else {
163163 O << "lo16(";
164164 printOp(MI->getOperand(OpNo));
172172 // Branches can take an immediate operand. This is used by the branch
173173 // selection pass to print $+8, an eight byte displacement from the PC.
174174 if (MI->getOperand(OpNo).isImmediate()) {
175 O << "$+" << MI->getOperand(OpNo).getImmedValue()*4;
175 O << "$+" << MI->getOperand(OpNo).getImm()*4;
176176 } else {
177177 printOp(MI->getOperand(OpNo));
178178 }
204204 printOp(MI->getOperand(OpNo));
205205 }
206206 void printAbsAddrOperand(const MachineInstr *MI, unsigned OpNo) {
207 O << (int)MI->getOperand(OpNo).getImmedValue()*4;
207 O << (int)MI->getOperand(OpNo).getImm()*4;
208208 }
209209 void printPICLabel(const MachineInstr *MI, unsigned OpNo) {
210210 O << "\"L" << getFunctionNumber() << "$pb\"\n";
508508 // Check for slwi/srwi mnemonics.
509509 if (MI->getOpcode() == PPC::RLWINM) {
510510 bool FoundMnemonic = false;
511 unsigned char SH = MI->getOperand(2).getImmedValue();
512 unsigned char MB = MI->getOperand(3).getImmedValue();
513 unsigned char ME = MI->getOperand(4).getImmedValue();
511 unsigned char SH = MI->getOperand(2).getImm();
512 unsigned char MB = MI->getOperand(3).getImm();
513 unsigned char ME = MI->getOperand(4).getImm();
514514 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
515515 O << "slwi "; FoundMnemonic = true;
516516 }
535535 return;
536536 }
537537 } else if (MI->getOpcode() == PPC::RLDICR) {
538 unsigned char SH = MI->getOperand(2).getImmedValue();
539 unsigned char ME = MI->getOperand(3).getImmedValue();
538 unsigned char SH = MI->getOperand(2).getImm();
539 unsigned char ME = MI->getOperand(3).getImm();
540540 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
541541 if (63-SH == ME) {
542542 O << "sldi ";
130130 rv = 0x80 >> rv;
131131 }
132132 } else if (MO.isImmediate()) {
133 rv = MO.getImmedValue();
133 rv = MO.getImm();
134134 } else if (MO.isGlobalAddress() || MO.isExternalSymbol() ||
135135 MO.isConstantPoolIndex() || MO.isJumpTableIndex()) {
136136 unsigned Reloc = 0;
5353 MI.getOperand(0).isRegister() &&
5454 MI.getOperand(2).isImmediate() &&
5555 "invalid PPC ADDI instruction!");
56 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
56 if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
5757 sourceReg = MI.getOperand(1).getReg();
5858 destReg = MI.getOperand(0).getReg();
5959 return true;
6464 MI.getOperand(1).isRegister() &&
6565 MI.getOperand(2).isImmediate() &&
6666 "invalid PPC ORI instruction!");
67 if (MI.getOperand(2).getImmedValue()==0) {
67 if (MI.getOperand(2).getImm() == 0) {
6868 sourceReg = MI.getOperand(1).getReg();
6969 destReg = MI.getOperand(0).getReg();
7070 return true;
9898 case PPC::LWZ:
9999 case PPC::LFS:
100100 case PPC::LFD:
101 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
101 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
102102 MI->getOperand(2).isFrameIndex()) {
103103 FrameIndex = MI->getOperand(2).getFrameIndex();
104104 return MI->getOperand(0).getReg();
116116 case PPC::STW:
117117 case PPC::STFS:
118118 case PPC::STFD:
119 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
119 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
120120 MI->getOperand(2).isFrameIndex()) {
121121 FrameIndex = MI->getOperand(2).getFrameIndex();
122122 return MI->getOperand(0).getReg();
134134 return TargetInstrInfo::commuteInstruction(MI);
135135
136136 // Cannot commute if it has a non-zero rotate count.
137 if (MI->getOperand(3).getImmedValue() != 0)
137 if (MI->getOperand(3).getImm() != 0)
138138 return 0;
139139
140140 // If we have a zero rotate count, we have:
161161 MI->getOperand(1).unsetIsKill();
162162
163163 // Swap the mask around.
164 unsigned MB = MI->getOperand(4).getImmedValue();
165 unsigned ME = MI->getOperand(5).getImmedValue();
166 MI->getOperand(4).setImmedValue((ME+1) & 31);
167 MI->getOperand(5).setImmedValue((MB-1) & 31);
164 unsigned MB = MI->getOperand(4).getImm();
165 unsigned ME = MI->getOperand(5).getImm();
166 MI->getOperand(4).setImm((ME+1) & 31);
167 MI->getOperand(5).setImm((MB-1) & 31);
168168 return MI;
169169 }
170170
213213 if (MO.isRegister())
214214 MIB.addReg(MO.getReg());
215215 else if (MO.isImmediate())
216 MIB.addImm(MO.getImmedValue());
216 MIB.addImm(MO.getImm());
217217 else
218218 MIB.addFrameIndex(MO.getFrameIndex());
219219 }
323323 if (MO.isRegister())
324324 MIB.addReg(MO.getReg());
325325 else if (MO.isImmediate())
326 MIB.addImm(MO.getImmedValue());
326 MIB.addImm(MO.getImm());
327327 else
328328 MIB.addFrameIndex(MO.getFrameIndex());
329329 }
801801 // Now add the frame object offset to the offset from r1.
802802 int Offset = MFI->getObjectOffset(FrameIndex);
803803 if (!isIXAddr)
804 Offset += MI.getOperand(OffsetOperandNo).getImmedValue();
804 Offset += MI.getOperand(OffsetOperandNo).getImm();
805805 else
806 Offset += MI.getOperand(OffsetOperandNo).getImmedValue() << 2;
806 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
807807
808808 // If we're not using a Frame Pointer that has been set to the value of the
809809 // SP before having the stack size subtracted from it, then add the stack size
151151 break;
152152
153153 case MachineOperand::MO_Immediate:
154 O << (int)MO.getImmedValue();
154 O << (int)MO.getImm();
155155 break;
156156 case MachineOperand::MO_MachineBasicBlock:
157157 printBasicBlockLabel(MO.getMachineBasicBlock());
187187 MI->getOperand(opNum+1).getReg() == SP::G0)
188188 return; // don't print "+%g0"
189189 if (MI->getOperand(opNum+1).isImmediate() &&
190 MI->getOperand(opNum+1).getImmedValue() == 0)
190 MI->getOperand(opNum+1).getImm() == 0)
191191 return; // don't print "+0"
192192
193193 O << "+";
202202 }
203203
204204 void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) {
205 int CC = (int)MI->getOperand(opNum).getImmedValue();
205 int CC = (int)MI->getOperand(opNum).getImm();
206206 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
207207 }
208208
911911 break;
912912 }
913913
914 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
914 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
915915
916916 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
917917 // control-flow pattern. The incoming instruction knows the destination vreg
2323 }
2424
2525 static bool isZeroImm(const MachineOperand &op) {
26 return op.isImmediate() && op.getImmedValue() == 0;
26 return op.isImmediate() && op.getImm() == 0;
2727 }
2828
2929 /// Return true if the instruction is a register to register move and
7070 MI->getOpcode() == SP::LDFri ||
7171 MI->getOpcode() == SP::LDDFri) {
7272 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
73 MI->getOperand(2).getImmedValue() == 0) {
73 MI->getOperand(2).getImm() == 0) {
7474 FrameIndex = MI->getOperand(1).getFrameIndex();
7575 return MI->getOperand(0).getReg();
7676 }
8989 MI->getOpcode() == SP::STFri ||
9090 MI->getOpcode() == SP::STDFri) {
9191 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
92 MI->getOperand(1).getImmedValue() == 0) {
92 MI->getOperand(1).getImm() == 0) {
9393 FrameIndex = MI->getOperand(0).getFrameIndex();
9494 return MI->getOperand(2).getReg();
9595 }
6767 if (MO.isRegister())
6868 MIB.addReg(MO.getReg());
6969 else if (MO.isImmediate())
70 MIB.addImm(MO.getImmedValue());
70 MIB.addImm(MO.getImm());
7171 else
7272 MIB.addFrameIndex(MO.getFrameIndex());
7373 }
109109 if (MO.isRegister())
110110 MIB.addReg(MO.getReg());
111111 else if (MO.isImmediate())
112 MIB.addImm(MO.getImmedValue());
112 MIB.addImm(MO.getImm());
113113 else
114114 MIB.addFrameIndex(MO.getFrameIndex());
115115 }
221221 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
222222 MachineBasicBlock::iterator I) const {
223223 MachineInstr &MI = *I;
224 int Size = MI.getOperand(0).getImmedValue();
224 int Size = MI.getOperand(0).getImm();
225225 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
226226 Size = -Size;
227227 if (Size)
245245 // Addressable stack objects are accessed using neg. offsets from %fp
246246 MachineFunction &MF = *MI.getParent()->getParent();
247247 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
248 MI.getOperand(i+1).getImmedValue();
248 MI.getOperand(i+1).getImm();
249249
250250 // Replace frame index with a frame pointer reference.
251251 if (Offset >= -4096 && Offset <= 4095) {
7171 MO.setReg(Pred[j].getReg());
7272 MadeChange = true;
7373 } else if (MO.isImmediate()) {
74 MO.setImm(Pred[j].getImmedValue());
74 MO.setImm(Pred[j].getImm());
7575 MadeChange = true;
7676 } else if (MO.isMachineBasicBlock()) {
7777 MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock());
228228 if (!Modifier ||
229229 (strcmp(Modifier, "debug") && strcmp(Modifier, "mem")))
230230 O << '$';
231 O << MO.getImmedValue();
231 O << MO.getImm();
232232 return;
233233 case MachineOperand::MO_MachineBasicBlock:
234234 printBasicBlockLabel(MO.getMachineBasicBlock());
439439 }
440440
441441 void X86ATTAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
442 unsigned char value = MI->getOperand(Op).getImmedValue();
442 unsigned char value = MI->getOperand(Op).getImm();
443443 assert(value <= 7 && "Invalid ssecc argument!");
444444 switch (value) {
445445 case 0: O << "eq"; break;
466466 DispSpec.isJumpTableIndex()) {
467467 printOperand(MI, Op+3, "mem", NotRIPRel);
468468 } else {
469 int DispVal = DispSpec.getImmedValue();
469 int DispVal = DispSpec.getImm();
470470 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
471471 O << DispVal;
472472 }
473473
474474 if (IndexReg.getReg() || BaseReg.getReg()) {
475 unsigned ScaleVal = MI->getOperand(Op+1).getImmedValue();
475 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
476476 unsigned BaseRegOperand = 0, IndexRegOperand = 2;
477477
478478 // There are cases where we can end up with ESP/RSP in the indexreg slot.
7676
7777 inline static bool isScale(const MachineOperand &MO) {
7878 return MO.isImmediate() &&
79 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
80 MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
79 (MO.getImm() == 1 || MO.getImm() == 2 ||
80 MO.getImm() == 4 || MO.getImm() == 8);
8181 }
8282
8383 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
7272 case X86::MMX_MOVQ64rm:
7373 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
7474 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
75 MI->getOperand(2).getImmedValue() == 1 &&
75 MI->getOperand(2).getImm() == 1 &&
7676 MI->getOperand(3).getReg() == 0 &&
77 MI->getOperand(4).getImmedValue() == 0) {
77 MI->getOperand(4).getImm() == 0) {
7878 FrameIndex = MI->getOperand(1).getFrameIndex();
7979 return MI->getOperand(0).getReg();
8080 }
103103 case X86::MMX_MOVNTQmr:
104104 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
105105 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
106 MI->getOperand(1).getImmedValue() == 1 &&
106 MI->getOperand(1).getImm() == 1 &&
107107 MI->getOperand(2).getReg() == 0 &&
108 MI->getOperand(3).getImmedValue() == 0) {
108 MI->getOperand(3).getImm() == 0) {
109109 FrameIndex = MI->getOperand(0).getFrameIndex();
110110 return MI->getOperand(4).getReg();
111111 }
135135 return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
136136 MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() &&
137137 MI->getOperand(1).getReg() == 0 &&
138 MI->getOperand(2).getImmedValue() == 1 &&
138 MI->getOperand(2).getImm() == 1 &&
139139 MI->getOperand(3).getReg() == 0;
140140 }
141141 // All other instructions marked M_REMATERIALIZABLE are always trivially
193193 MI->getOperand(2).isImmediate() &&
194194 MI->getOperand(3).isRegister() &&
195195 MI->getOperand(4).isGlobalAddress() &&
196 MI->getOperand(2).getImmedValue() == 1 &&
196 MI->getOperand(2).getImm() == 1 &&
197197 MI->getOperand(3).getReg() == 0)
198198 return true;
199199 }
216216 MI->getOperand(3).isRegister() &&
217217 MI->getOperand(4).isConstantPoolIndex() &&
218218 MI->getOperand(1).getReg() == 0 &&
219 MI->getOperand(2).getImmedValue() == 1 &&
219 MI->getOperand(2).getImm() == 1 &&
220220 MI->getOperand(3).getReg() == 0;
221221 }
222222
403403 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
404404 if (MI->getOperand(2).isImmediate())
405405 NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
406 MI->getOperand(2).getImmedValue());
406 MI->getOperand(2).getImm());
407407 break;
408408 case X86::ADD32ri:
409409 case X86::ADD32ri8:
411411 if (MI->getOperand(2).isImmediate()) {
412412 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
413413 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src,
414 MI->getOperand(2).getImmedValue());
414 MI->getOperand(2).getImm());
415415 }
416416 break;
417417 case X86::ADD16ri:
420420 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
421421 if (MI->getOperand(2).isImmediate())
422422 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
423 MI->getOperand(2).getImmedValue());
423 MI->getOperand(2).getImm());
424424 break;
425425 case X86::SHL16ri:
426426 if (DisableLEA16) return 0;
428428 case X86::SHL64ri: {
429429 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
430430 "Unknown shl instruction!");
431 unsigned ShAmt = MI->getOperand(2).getImmedValue();
431 unsigned ShAmt = MI->getOperand(2).getImm();
432432 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
433433 X86AddressMode AM;
434434 AM.Scale = 1 << ShAmt;
472472 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
473473 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
474474 }
475 unsigned Amt = MI->getOperand(3).getImmedValue();
475 unsigned Amt = MI->getOperand(3).getImm();
476476 unsigned A = MI->getOperand(0).getReg();
477477 unsigned B = MI->getOperand(1).getReg();
478478 unsigned C = MI->getOperand(2).getReg();
9898 }
9999
100100 void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
101 unsigned char value = MI->getOperand(Op).getImmedValue();
101 unsigned char value = MI->getOperand(Op).getImm();
102102 assert(value <= 7 && "Invalid ssecc argument!");
103103 switch (value) {
104104 case 0: O << "eq"; break;
131131 return;
132132 }
133133 case MachineOperand::MO_Immediate:
134 O << MO.getImmedValue();
134 O << MO.getImm();
135135 return;
136136 case MachineOperand::MO_MachineBasicBlock:
137137 printBasicBlockLabel(MO.getMachineBasicBlock());
194194 assert(isMem(MI, Op) && "Invalid memory reference!");
195195
196196 const MachineOperand &BaseReg = MI->getOperand(Op);
197 int ScaleVal = MI->getOperand(Op+1).getImmedValue();
197 int ScaleVal = MI->getOperand(Op+1).getImm();
198198 const MachineOperand &IndexReg = MI->getOperand(Op+2);
199199 const MachineOperand &DispSpec = MI->getOperand(Op+3);
200200
219219 O << " + ";
220220 printOp(DispSpec, "mem");
221221 } else {
222 int DispVal = DispSpec.getImmedValue();
222 int DispVal = DispSpec.getImm();
223223 if (DispVal || (!BaseReg.getReg() && !IndexReg.getReg())) {
224224 if (NeedPlus)
225225 if (DispVal > 0)