llvm.org GIT mirror llvm / 9a1c189
Add a separate ARM instruction format for Saturate instructions. (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110754 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
7 changed file(s) with 208 addition(s) and 181 deletion(s). Raw diff Collapse all Expand all
9797
9898 // Miscellaneous arithmetic instructions
9999 ArithMiscFrm = 12 << FormShift,
100 SatFrm = 13 << FormShift,
100101
101102 // Extend instructions
102 ExtFrm = 13 << FormShift,
103 ExtFrm = 14 << FormShift,
103104
104105 // VFP formats
105 VFPUnaryFrm = 14 << FormShift,
106 VFPBinaryFrm = 15 << FormShift,
107 VFPConv1Frm = 16 << FormShift,
108 VFPConv2Frm = 17 << FormShift,
109 VFPConv3Frm = 18 << FormShift,
110 VFPConv4Frm = 19 << FormShift,
111 VFPConv5Frm = 20 << FormShift,
112 VFPLdStFrm = 21 << FormShift,
113 VFPLdStMulFrm = 22 << FormShift,
114 VFPMiscFrm = 23 << FormShift,
106 VFPUnaryFrm = 15 << FormShift,
107 VFPBinaryFrm = 16 << FormShift,
108 VFPConv1Frm = 17 << FormShift,
109 VFPConv2Frm = 18 << FormShift,
110 VFPConv3Frm = 19 << FormShift,
111 VFPConv4Frm = 20 << FormShift,
112 VFPConv5Frm = 21 << FormShift,
113 VFPLdStFrm = 22 << FormShift,
114 VFPLdStMulFrm = 23 << FormShift,
115 VFPMiscFrm = 24 << FormShift,
115116
116117 // Thumb format
117 ThumbFrm = 24 << FormShift,
118 ThumbFrm = 25 << FormShift,
118119
119120 // Miscelleaneous format
120 MiscFrm = 25 << FormShift,
121 MiscFrm = 26 << FormShift,
121122
122123 // NEON formats
123 NGetLnFrm = 26 << FormShift,
124 NSetLnFrm = 27 << FormShift,
125 NDupFrm = 28 << FormShift,
126 NLdStFrm = 29 << FormShift,
127 N1RegModImmFrm= 30 << FormShift,
128 N2RegFrm = 31 << FormShift,
129 NVCVTFrm = 32 << FormShift,
130 NVDupLnFrm = 33 << FormShift,
131 N2RegVShLFrm = 34 << FormShift,
132 N2RegVShRFrm = 35 << FormShift,
133 N3RegFrm = 36 << FormShift,
134 N3RegVShFrm = 37 << FormShift,
135 NVExtFrm = 38 << FormShift,
136 NVMulSLFrm = 39 << FormShift,
137 NVTBLFrm = 40 << FormShift,
124 NGetLnFrm = 27 << FormShift,
125 NSetLnFrm = 28 << FormShift,
126 NDupFrm = 29 << FormShift,
127 NLdStFrm = 30 << FormShift,
128 N1RegModImmFrm= 31 << FormShift,
129 N2RegFrm = 32 << FormShift,
130 NVCVTFrm = 33 << FormShift,
131 NVDupLnFrm = 34 << FormShift,
132 N2RegVShLFrm = 35 << FormShift,
133 N2RegVShRFrm = 36 << FormShift,
134 N3RegFrm = 37 << FormShift,
135 N3RegVShFrm = 38 << FormShift,
136 NVExtFrm = 39 << FormShift,
137 NVMulSLFrm = 40 << FormShift,
138 NVTBLFrm = 41 << FormShift,
138139
139140 //===------------------------------------------------------------------===//
140141 // Misc flags.
123123
124124 void emitMiscArithInstruction(const MachineInstr &MI);
125125
126 void emitSaturateInstruction(const MachineInstr &MI);
127
126128 void emitBranchInstruction(const MachineInstr &MI);
127129
128130 void emitInlineJumpTable(unsigned JTIndex);
387389 break;
388390 case ARMII::ArithMiscFrm:
389391 emitMiscArithInstruction(MI);
392 break;
393 case ARMII::SatFrm:
394 emitSaturateInstruction(MI);
390395 break;
391396 case ARMII::BrFrm:
392397 emitBranchInstruction(MI);
12271232 emitWordLE(Binary);
12281233 }
12291234
1235 void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1236 const TargetInstrDesc &TID = MI.getDesc();
1237
1238 // Part of binary is determined by TableGen.
1239 unsigned Binary = getBinaryCodeForInstr(MI);
1240
1241 // Set the conditional execution predicate
1242 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1243
1244 // Encode Rd
1245 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1246
1247 // Encode saturate bit position.
1248 unsigned Pos = MI.getOperand(1).getImm();
1249 if (TID.Opcode == ARM::SSATlsl ||
1250 TID.Opcode == ARM::SSATasr ||
1251 TID.Opcode == ARM::SSAT16)
1252 Pos -= 1;
1253 assert((Pos < 16 || (Pos < 32 &&
1254 TID.Opcode != ARM::SSAT16 &&
1255 TID.Opcode != ARM::USAT16)) &&
1256 "saturate bit position out of range");
1257 Binary |= Pos << 16;
1258
1259 // Encode Rm
1260 Binary |= getMachineOpValue(MI, 2);
1261
1262 // Encode shift_imm.
1263 if (TID.getNumOperands() == 4) {
1264 unsigned ShiftAmt = MI.getOperand(3).getImm();
1265 if (ShiftAmt == 32 &&
1266 (TID.Opcode == ARM::SSATasr || TID.Opcode == ARM::USATasr))
1267 ShiftAmt = 0;
1268 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1269 Binary |= ShiftAmt << ARMII::ShiftShift;
1270 }
1271
1272 emitWordLE(Binary);
1273 }
1274
12301275 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
12311276 const TargetInstrDesc &TID = MI.getDesc();
12321277
3535 def LdStExFrm : Format<11>;
3636
3737 def ArithMiscFrm : Format<12>;
38 def ExtFrm : Format<13>;
39
40 def VFPUnaryFrm : Format<14>;
41 def VFPBinaryFrm : Format<15>;
42 def VFPConv1Frm : Format<16>;
43 def VFPConv2Frm : Format<17>;
44 def VFPConv3Frm : Format<18>;
45 def VFPConv4Frm : Format<19>;
46 def VFPConv5Frm : Format<20>;
47 def VFPLdStFrm : Format<21>;
48 def VFPLdStMulFrm : Format<22>;
49 def VFPMiscFrm : Format<23>;
50
51 def ThumbFrm : Format<24>;
52 def MiscFrm : Format<25>;
53
54 def NGetLnFrm : Format<26>;
55 def NSetLnFrm : Format<27>;
56 def NDupFrm : Format<28>;
57 def NLdStFrm : Format<29>;
58 def N1RegModImmFrm: Format<30>;
59 def N2RegFrm : Format<31>;
60 def NVCVTFrm : Format<32>;
61 def NVDupLnFrm : Format<33>;
62 def N2RegVShLFrm : Format<34>;
63 def N2RegVShRFrm : Format<35>;
64 def N3RegFrm : Format<36>;
65 def N3RegVShFrm : Format<37>;
66 def NVExtFrm : Format<38>;
67 def NVMulSLFrm : Format<39>;
68 def NVTBLFrm : Format<40>;
38 def SatFrm : Format<13>;
39 def ExtFrm : Format<14>;
40
41 def VFPUnaryFrm : Format<15>;
42 def VFPBinaryFrm : Format<16>;
43 def VFPConv1Frm : Format<17>;
44 def VFPConv2Frm : Format<18>;
45 def VFPConv3Frm : Format<19>;
46 def VFPConv4Frm : Format<20>;
47 def VFPConv5Frm : Format<21>;
48 def VFPLdStFrm : Format<22>;
49 def VFPLdStMulFrm : Format<23>;
50 def VFPMiscFrm : Format<24>;
51
52 def ThumbFrm : Format<25>;
53 def MiscFrm : Format<26>;
54
55 def NGetLnFrm : Format<27>;
56 def NSetLnFrm : Format<28>;
57 def NDupFrm : Format<29>;
58 def NLdStFrm : Format<30>;
59 def N1RegModImmFrm: Format<31>;
60 def N2RegFrm : Format<32>;
61 def NVCVTFrm : Format<33>;
62 def NVDupLnFrm : Format<34>;
63 def N2RegVShLFrm : Format<35>;
64 def N2RegVShRFrm : Format<36>;
65 def N3RegFrm : Format<37>;
66 def N3RegVShFrm : Format<38>;
67 def NVExtFrm : Format<39>;
68 def NVMulSLFrm : Format<40>;
69 def NVTBLFrm : Format<41>;
6970
7071 // Misc flags.
7172
18091809 // Signed/Unsigned saturate -- for disassembly only
18101810
18111811 def SSATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1812 DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
1812 SatFrm, NoItinerary,
1813 "ssat", "\t$dst, $bit_pos, $a, lsl $shamt",
18131814 [/* For disassembly only; pattern left blank */]> {
18141815 let Inst{27-21} = 0b0110101;
18151816 let Inst{6-4} = 0b001;
18161817 }
18171818
18181819 def SSATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1819 DPFrm, NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
1820 SatFrm, NoItinerary,
1821 "ssat", "\t$dst, $bit_pos, $a, asr $shamt",
18201822 [/* For disassembly only; pattern left blank */]> {
18211823 let Inst{27-21} = 0b0110101;
18221824 let Inst{6-4} = 0b101;
18231825 }
18241826
1825 def SSAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
1827 def SSAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), SatFrm,
18261828 NoItinerary, "ssat16", "\t$dst, $bit_pos, $a",
18271829 [/* For disassembly only; pattern left blank */]> {
18281830 let Inst{27-20} = 0b01101010;
18301832 }
18311833
18321834 def USATlsl : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1833 DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
1835 SatFrm, NoItinerary,
1836 "usat", "\t$dst, $bit_pos, $a, lsl $shamt",
18341837 [/* For disassembly only; pattern left blank */]> {
18351838 let Inst{27-21} = 0b0110111;
18361839 let Inst{6-4} = 0b001;
18371840 }
18381841
18391842 def USATasr : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a, i32imm:$shamt),
1840 DPFrm, NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt",
1843 SatFrm, NoItinerary,
1844 "usat", "\t$dst, $bit_pos, $a, asr $shamt",
18411845 [/* For disassembly only; pattern left blank */]> {
18421846 let Inst{27-21} = 0b0110111;
18431847 let Inst{6-4} = 0b101;
18441848 }
18451849
1846 def USAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), DPFrm,
1850 def USAT16 : AI<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), SatFrm,
18471851 NoItinerary, "usat16", "\t$dst, $bit_pos, $a",
18481852 [/* For disassembly only; pattern left blank */]> {
18491853 let Inst{27-20} = 0b01101110;
907907 return true;
908908 }
909909
910 static inline bool SaturateOpcode(unsigned Opcode) {
911 switch (Opcode) {
912 case ARM::SSATlsl: case ARM::SSATasr: case ARM::SSAT16:
913 case ARM::USATlsl: case ARM::USATasr: case ARM::USAT16:
914 return true;
915 default:
916 return false;
917 }
918 }
919
920 static inline unsigned decodeSaturatePos(unsigned Opcode, uint32_t insn) {
921 switch (Opcode) {
922 case ARM::SSATlsl:
923 case ARM::SSATasr:
924 return slice(insn, 20, 16) + 1;
925 case ARM::SSAT16:
926 return slice(insn, 19, 16) + 1;
927 case ARM::USATlsl:
928 case ARM::USATasr:
929 return slice(insn, 20, 16);
930 case ARM::USAT16:
931 return slice(insn, 19, 16);
932 default:
933 assert(0 && "Invalid opcode passed in");
934 return 0;
935 }
936 }
937
938910 // A major complication is the fact that some of the saturating add/subtract
939911 // operations have Rd Rm Rn, instead of the "normal" Rd Rn Rm.
940912 // They are QADD, QDADD, QDSUB, and QSUB.
959931 // Now disassemble the src operands.
960932 if (OpIdx >= NumOps)
961933 return false;
962
963 // SSAT/SSAT16/USAT/USAT16 has imm operand after Rd.
964 if (SaturateOpcode(Opcode)) {
965 MI.addOperand(MCOperand::CreateImm(decodeSaturatePos(Opcode, insn)));
966
967 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
968 decodeRm(insn))));
969
970 if (Opcode == ARM::SSAT16 || Opcode == ARM::USAT16) {
971 OpIdx += 2;
972 return true;
973 }
974
975 // For SSAT operand reg (Rm) has been disassembled above.
976 // Now disassemble the shift amount.
977
978 // Inst{11-7} encodes the imm5 shift amount.
979 unsigned ShAmt = slice(insn, 11, 7);
980
981 // A8.6.183. Possible ASR shift amount of 32...
982 if (Opcode == ARM::SSATasr && ShAmt == 0)
983 ShAmt = 32;
984
985 MI.addOperand(MCOperand::CreateImm(ShAmt));
986
987 OpIdx += 3;
988 return true;
989 }
990934
991935 // Special-case handling of BFC/BFI/SBFX/UBFX.
992936 if (Opcode == ARM::BFC || Opcode == ARM::BFI) {
15051449 ++OpIdx;
15061450 }
15071451
1452 return true;
1453 }
1454
1455 /// DisassembleSatFrm - Disassemble saturate instructions:
1456 /// SSAT, SSAT16, USAT, and USAT16.
1457 static bool DisassembleSatFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
1458 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1459
1460 const TargetInstrDesc &TID = ARMInsts[Opcode];
1461 NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands
1462
1463 // Disassemble register def.
1464 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1465 decodeRd(insn))));
1466
1467 unsigned Pos = slice(insn, 20, 16);
1468 if (Opcode == ARM::SSATlsl ||
1469 Opcode == ARM::SSATasr ||
1470 Opcode == ARM::SSAT16)
1471 Pos += 1;
1472 MI.addOperand(MCOperand::CreateImm(Pos));
1473
1474 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1475 decodeRm(insn))));
1476
1477 if (NumOpsAdded == 4) {
1478 // Inst{11-7} encodes the imm5 shift amount.
1479 unsigned ShAmt = slice(insn, 11, 7);
1480 // A8.6.183. Possible ASR shift amount of 32...
1481 if ((Opcode == ARM::SSATasr || Opcode == ARM::USATasr) && ShAmt == 0)
1482 ShAmt = 32;
1483 MI.addOperand(MCOperand::CreateImm(ShAmt));
1484 }
15081485 return true;
15091486 }
15101487
30843061 &DisassembleLdStMulFrm,
30853062 &DisassembleLdStExFrm,
30863063 &DisassembleArithMiscFrm,
3064 &DisassembleSatFrm,
30873065 &DisassembleExtFrm,
30883066 &DisassembleVFPUnaryFrm,
30893067 &DisassembleVFPBinaryFrm,
5353 ENTRY(ARM_FORMAT_LDSTMULFRM, 10) \
5454 ENTRY(ARM_FORMAT_LDSTEXFRM, 11) \
5555 ENTRY(ARM_FORMAT_ARITHMISCFRM, 12) \
56 ENTRY(ARM_FORMAT_EXTFRM, 13) \
57 ENTRY(ARM_FORMAT_VFPUNARYFRM, 14) \
58 ENTRY(ARM_FORMAT_VFPBINARYFRM, 15) \
59 ENTRY(ARM_FORMAT_VFPCONV1FRM, 16) \
60 ENTRY(ARM_FORMAT_VFPCONV2FRM, 17) \
61 ENTRY(ARM_FORMAT_VFPCONV3FRM, 18) \
62 ENTRY(ARM_FORMAT_VFPCONV4FRM, 19) \
63 ENTRY(ARM_FORMAT_VFPCONV5FRM, 20) \
64 ENTRY(ARM_FORMAT_VFPLDSTFRM, 21) \
65 ENTRY(ARM_FORMAT_VFPLDSTMULFRM, 22) \
66 ENTRY(ARM_FORMAT_VFPMISCFRM, 23) \
67 ENTRY(ARM_FORMAT_THUMBFRM, 24) \
68 ENTRY(ARM_FORMAT_NEONFRM, 25) \
69 ENTRY(ARM_FORMAT_NEONGETLNFRM, 26) \
70 ENTRY(ARM_FORMAT_NEONSETLNFRM, 27) \
71 ENTRY(ARM_FORMAT_NEONDUPFRM, 28) \
72 ENTRY(ARM_FORMAT_MISCFRM, 29) \
73 ENTRY(ARM_FORMAT_THUMBMISCFRM, 30) \
74 ENTRY(ARM_FORMAT_NLdSt, 31) \
75 ENTRY(ARM_FORMAT_N1RegModImm, 32) \
76 ENTRY(ARM_FORMAT_N2Reg, 33) \
77 ENTRY(ARM_FORMAT_NVCVT, 34) \
78 ENTRY(ARM_FORMAT_NVecDupLn, 35) \
79 ENTRY(ARM_FORMAT_N2RegVecShL, 36) \
80 ENTRY(ARM_FORMAT_N2RegVecShR, 37) \
81 ENTRY(ARM_FORMAT_N3Reg, 38) \
82 ENTRY(ARM_FORMAT_N3RegVecSh, 39) \
83 ENTRY(ARM_FORMAT_NVecExtract, 40) \
84 ENTRY(ARM_FORMAT_NVecMulScalar, 41) \
85 ENTRY(ARM_FORMAT_NVTBL, 42)
56 ENTRY(ARM_FORMAT_SATFRM, 13) \
57 ENTRY(ARM_FORMAT_EXTFRM, 14) \
58 ENTRY(ARM_FORMAT_VFPUNARYFRM, 15) \
59 ENTRY(ARM_FORMAT_VFPBINARYFRM, 16) \
60 ENTRY(ARM_FORMAT_VFPCONV1FRM, 17) \
61 ENTRY(ARM_FORMAT_VFPCONV2FRM, 18) \
62 ENTRY(ARM_FORMAT_VFPCONV3FRM, 19) \
63 ENTRY(ARM_FORMAT_VFPCONV4FRM, 20) \
64 ENTRY(ARM_FORMAT_VFPCONV5FRM, 21) \
65 ENTRY(ARM_FORMAT_VFPLDSTFRM, 22) \
66 ENTRY(ARM_FORMAT_VFPLDSTMULFRM, 23) \
67 ENTRY(ARM_FORMAT_VFPMISCFRM, 24) \
68 ENTRY(ARM_FORMAT_THUMBFRM, 25) \
69 ENTRY(ARM_FORMAT_MISCFRM, 26) \
70 ENTRY(ARM_FORMAT_NEONGETLNFRM, 27) \
71 ENTRY(ARM_FORMAT_NEONSETLNFRM, 28) \
72 ENTRY(ARM_FORMAT_NEONDUPFRM, 29) \
73 ENTRY(ARM_FORMAT_NLdSt, 30) \
74 ENTRY(ARM_FORMAT_N1RegModImm, 31) \
75 ENTRY(ARM_FORMAT_N2Reg, 32) \
76 ENTRY(ARM_FORMAT_NVCVT, 33) \
77 ENTRY(ARM_FORMAT_NVecDupLn, 34) \
78 ENTRY(ARM_FORMAT_N2RegVecShL, 35) \
79 ENTRY(ARM_FORMAT_N2RegVecShR, 36) \
80 ENTRY(ARM_FORMAT_N3Reg, 37) \
81 ENTRY(ARM_FORMAT_N3RegVecSh, 38) \
82 ENTRY(ARM_FORMAT_NVecExtract, 39) \
83 ENTRY(ARM_FORMAT_NVecMulScalar, 40) \
84 ENTRY(ARM_FORMAT_NVTBL, 41)
8685
8786 // ARM instruction format specifies the encoding used by the instruction.
8887 #define ENTRY(n, v) n = v,
4848 ENTRY(ARM_FORMAT_LDSTMULFRM, 10) \
4949 ENTRY(ARM_FORMAT_LDSTEXFRM, 11) \
5050 ENTRY(ARM_FORMAT_ARITHMISCFRM, 12) \
51 ENTRY(ARM_FORMAT_EXTFRM, 13) \
52 ENTRY(ARM_FORMAT_VFPUNARYFRM, 14) \
53 ENTRY(ARM_FORMAT_VFPBINARYFRM, 15) \
54 ENTRY(ARM_FORMAT_VFPCONV1FRM, 16) \
55 ENTRY(ARM_FORMAT_VFPCONV2FRM, 17) \
56 ENTRY(ARM_FORMAT_VFPCONV3FRM, 18) \
57 ENTRY(ARM_FORMAT_VFPCONV4FRM, 19) \
58 ENTRY(ARM_FORMAT_VFPCONV5FRM, 20) \
59 ENTRY(ARM_FORMAT_VFPLDSTFRM, 21) \
60 ENTRY(ARM_FORMAT_VFPLDSTMULFRM, 22) \
61 ENTRY(ARM_FORMAT_VFPMISCFRM, 23) \
62 ENTRY(ARM_FORMAT_THUMBFRM, 24) \
63 ENTRY(ARM_FORMAT_NEONFRM, 25) \
64 ENTRY(ARM_FORMAT_NEONGETLNFRM, 26) \
65 ENTRY(ARM_FORMAT_NEONSETLNFRM, 27) \
66 ENTRY(ARM_FORMAT_NEONDUPFRM, 28) \
67 ENTRY(ARM_FORMAT_MISCFRM, 29) \
68 ENTRY(ARM_FORMAT_THUMBMISCFRM, 30) \
69 ENTRY(ARM_FORMAT_NLdSt, 31) \
70 ENTRY(ARM_FORMAT_N1RegModImm, 32) \
71 ENTRY(ARM_FORMAT_N2Reg, 33) \
72 ENTRY(ARM_FORMAT_NVCVT, 34) \
73 ENTRY(ARM_FORMAT_NVecDupLn, 35) \
74 ENTRY(ARM_FORMAT_N2RegVecShL, 36) \
75 ENTRY(ARM_FORMAT_N2RegVecShR, 37) \
76 ENTRY(ARM_FORMAT_N3Reg, 38) \
77 ENTRY(ARM_FORMAT_N3RegVecSh, 39) \
78 ENTRY(ARM_FORMAT_NVecExtract, 40) \
79 ENTRY(ARM_FORMAT_NVecMulScalar, 41) \
80 ENTRY(ARM_FORMAT_NVTBL, 42)
51 ENTRY(ARM_FORMAT_SATFRM, 13) \
52 ENTRY(ARM_FORMAT_EXTFRM, 14) \
53 ENTRY(ARM_FORMAT_VFPUNARYFRM, 15) \
54 ENTRY(ARM_FORMAT_VFPBINARYFRM, 16) \
55 ENTRY(ARM_FORMAT_VFPCONV1FRM, 17) \
56 ENTRY(ARM_FORMAT_VFPCONV2FRM, 18) \
57 ENTRY(ARM_FORMAT_VFPCONV3FRM, 19) \
58 ENTRY(ARM_FORMAT_VFPCONV4FRM, 20) \
59 ENTRY(ARM_FORMAT_VFPCONV5FRM, 21) \
60 ENTRY(ARM_FORMAT_VFPLDSTFRM, 22) \
61 ENTRY(ARM_FORMAT_VFPLDSTMULFRM, 23) \
62 ENTRY(ARM_FORMAT_VFPMISCFRM, 24) \
63 ENTRY(ARM_FORMAT_THUMBFRM, 25) \
64 ENTRY(ARM_FORMAT_MISCFRM, 26) \
65 ENTRY(ARM_FORMAT_NEONGETLNFRM, 27) \
66 ENTRY(ARM_FORMAT_NEONSETLNFRM, 28) \
67 ENTRY(ARM_FORMAT_NEONDUPFRM, 29) \
68 ENTRY(ARM_FORMAT_NLdSt, 30) \
69 ENTRY(ARM_FORMAT_N1RegModImm, 31) \
70 ENTRY(ARM_FORMAT_N2Reg, 32) \
71 ENTRY(ARM_FORMAT_NVCVT, 33) \
72 ENTRY(ARM_FORMAT_NVecDupLn, 34) \
73 ENTRY(ARM_FORMAT_N2RegVecShL, 35) \
74 ENTRY(ARM_FORMAT_N2RegVecShR, 36) \
75 ENTRY(ARM_FORMAT_N3Reg, 37) \
76 ENTRY(ARM_FORMAT_N3RegVecSh, 38) \
77 ENTRY(ARM_FORMAT_NVecExtract, 39) \
78 ENTRY(ARM_FORMAT_NVecMulScalar, 40) \
79 ENTRY(ARM_FORMAT_NVTBL, 41)
8180
8281 // ARM instruction format specifies the encoding used by the instruction.
8382 #define ENTRY(n, v) n = v,