llvm.org GIT mirror llvm / 9a062b6
Eliminate constant-extender profitability checks from Hexagon isel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231992 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 5 years ago
7 changed file(s) with 239 addition(s) and 529 deletion(s). Raw diff Collapse all Expand all
5050
5151 // Keep a reference to HexagonTargetMachine.
5252 const HexagonTargetMachine& TM;
53 DenseMap GlobalAddressUseCountMap;
5453 public:
5554 explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine,
5655 CodeGenOpt::Level OptLevel)
118117 SDNode *SelectConstant(SDNode *N);
119118 SDNode *SelectConstantFP(SDNode *N);
120119 SDNode *SelectAdd(SDNode *N);
121 bool isConstExtProfitable(SDNode *N) const;
122120
123121 // XformMskToBitPosU5Imm - Returns the bit position which
124122 // the single bit 32 bit mask represents.
14261424 return false;
14271425 }
14281426
1429 bool HexagonDAGToDAGISel::isConstExtProfitable(SDNode *N) const {
1430 unsigned UseCount = 0;
1431 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1432 UseCount++;
1433 }
1434
1435 return (UseCount <= 1);
1436
1437 }
1438
1439 //===--------------------------------------------------------------------===//
1440 // Return 'true' if use count of the global address is below threshold.
1441 //===--------------------------------------------------------------------===//
1442 bool HexagonDAGToDAGISel::hasNumUsesBelowThresGA(SDNode *N) const {
1443 assert(N->getOpcode() == ISD::TargetGlobalAddress &&
1444 "Expecting a target global address");
1445
1446 // Always try to fold the address.
1447 if (TM.getOptLevel() == CodeGenOpt::Aggressive)
1448 return true;
1449
1450 GlobalAddressSDNode *GA = cast(N);
1451 DenseMap::const_iterator GI =
1452 GlobalAddressUseCountMap.find(GA->getGlobal());
1453
1454 if (GI == GlobalAddressUseCountMap.end())
1455 return false;
1456
1457 return GI->second <= MaxNumOfUsesForConstExtenders;
1458 }
1459
14601427 //===--------------------------------------------------------------------===//
14611428 // Return true if the non-GP-relative global address can be folded.
14621429 //===--------------------------------------------------------------------===//
329329 def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
330330 "$Rdd = combine(#$s8, #$S8)",
331331 [(set (i64 DoubleRegs:$Rdd),
332 (i64 (HexagonCOMBINE(i32 s8ExtPred:$s8), (i32 s8ImmPred:$S8))))]> {
332 (i64 (HexagonCOMBINE(i32 s32ImmPred:$s8), (i32 s8ImmPred:$S8))))]> {
333333 bits<5> Rdd;
334334 bits<8> s8;
335335 bits<8> S8;
414414
415415 defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel;
416416
417 def: Pat<(i32 (add I32:$Rs, s16ExtPred:$s16)),
417 def: Pat<(i32 (add I32:$Rs, s32ImmPred:$s16)),
418418 (i32 (A2_addi I32:$Rs, imm:$s16))>;
419419
420420 //===----------------------------------------------------------------------===//
428428 : ALU32_ri <(outs IntRegs:$Rd),
429429 (ins IntRegs:$Rs, s10Ext:$s10),
430430 "$Rd = "#mnemonic#"($Rs, #$s10)" ,
431 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10))]> {
431 [(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10))]> {
432432 bits<5> Rd;
433433 bits<5> Rs;
434434 bits<10> s10;
473473 let Inst{27-24} = 0b1111;
474474 }
475475
476 def: Pat<(sub s10ExtPred:$s10, IntRegs:$Rs),
476 def: Pat<(sub s32ImmPred:$s10, IntRegs:$Rs),
477477 (A2_subri imm:$s10, IntRegs:$Rs)>;
478478
479479 // Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
621621 isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
622622 isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in
623623 def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
624 [(set (i32 IntRegs:$Rd), s16ExtPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
624 [(set (i32 IntRegs:$Rd), s32ImmPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
625625 ImmRegRel, PredRel {
626626 bits<5> Rd;
627627 bits<16> s16;
689689 def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
690690 "$Rd = mux($Pu, $Rs, #$s8)">;
691691
692 def : Pat<(i32 (select I1:$Pu, s8ExtPred:$s8, I32:$Rs)),
693 (C2_muxri I1:$Pu, s8ExtPred:$s8, I32:$Rs)>;
694
695 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s8ExtPred:$s8)),
696 (C2_muxir I1:$Pu, I32:$Rs, s8ExtPred:$s8)>;
692 def : Pat<(i32 (select I1:$Pu, s32ImmPred:$s8, I32:$Rs)),
693 (C2_muxri I1:$Pu, s32ImmPred:$s8, I32:$Rs)>;
694
695 def : Pat<(i32 (select I1:$Pu, I32:$Rs, s32ImmPred:$s8)),
696 (C2_muxir I1:$Pu, I32:$Rs, s32ImmPred:$s8)>;
697697
698698 // C2_muxii: Scalar mux immediates.
699699 let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
702702 (ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
703703 "$Rd = mux($Pu, #$s8, #$S8)" ,
704704 [(set (i32 IntRegs:$Rd),
705 (i32 (select I1:$Pu, s8ExtPred:$s8, s8ImmPred:$S8)))] > {
705 (i32 (select I1:$Pu, s32ImmPred:$s8, s8ImmPred:$S8)))] > {
706706 bits<5> Rd;
707707 bits<2> Pu;
708708 bits<8> s8;
17791779 }
17801780
17811781 let AddedComplexity = 20 in {
1782 defm: Loadx_pat;
1783 defm: Loadx_pat;
1784 defm: Loadx_pat;
1785 defm: Loadx_pat;
1786 defm: Loadx_pat;
1787 defm: Loadx_pat;
1788
1789 defm: Loadx_pat;
1790 defm: Loadx_pat;
1791 defm: Loadx_pat;
1792 defm: Loadx_pat;
1793 defm: Loadx_pat;
1794 defm: Loadx_pat;
1795 defm: Loadx_pat;
1796 defm: Loadx_pat<zextloadi16, i32, s11_1ExtPred, L2_loadruh_io>;
1782 defm: Loadx_pat<load, i32, s30_2ImmPred, L2_loadri_io>;
1783 defm: Loadx_pat;
1784 defm: Loadx_pat;
1785 defm: Loadx_pat;
1786 defm: Loadx_pat;
1787 defm: Loadx_pat;
1788
1789 defm: Loadx_pat;
1790 defm: Loadx_pat;
1791 defm: Loadx_pat;
1792 defm: Loadx_pat;
1793 defm: Loadx_pat;
1794 defm: Loadx_pat;
1795 defm: Loadx_pat;
1796 defm: Loadx_pat;
17971797 // No sextloadi1.
17981798 }
17991799
27382738
27392739 let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in
27402740 def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
2741 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u8ExtPred:$u8))]>;
2741 [(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u32ImmPred:$u8))]>;
27422742
27432743 def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
27442744 [(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
27602760 def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
27612761 "$dst = mpyi($src1, #$src2)",
27622762 [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
2763 s9ExtPred:$src2))]>, ImmRegRel;
2763 s32ImmPred:$src2))]>, ImmRegRel;
27642764
27652765 let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
27662766 InputType = "imm" in
28112811 let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in {
28122812 def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
28132813 [(set (i32 IntRegs:$dst),
2814 (add (mul IntRegs:$src2, u8ExtPred:$src3),
2814 (add (mul IntRegs:$src2, u32ImmPred:$src3),
28152815 IntRegs:$src1))]>, ImmRegRel;
28162816
28172817 def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
28242824 let isExtentSigned = 1 in
28252825 def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
28262826 [(set (i32 IntRegs:$dst),
2827 (add (add (i32 IntRegs:$src2), s8_16ExtPred:$src3),
2827 (add (add (i32 IntRegs:$src2), s16_16ImmPred:$src3),
28282828 (i32 IntRegs:$src1)))]>, ImmRegRel;
28292829
28302830 def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
28562856 (MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
28572857
28582858 def : T_MType_acc_pat2 ;
2859 def : T_MType_acc_pat1 ;
2860
2861 def : T_MType_acc_pat1 naccii, add, sub, s8_16ExtPred>;
2859 def : T_MType_acc_pat1 macsin, mul, sub, u32ImmPred>;
2860
2861 def : T_MType_acc_pat1 ;
28622862 def : T_MType_acc_pat2 ;
28632863
28642864 //===----------------------------------------------------------------------===//
36093609 : PatFrag<(ops node:$val, node:$ptr), F.Fragment>;
36103610
36113611 let AddedComplexity = 20 in {
3612 defm: Storex_pat;
3613 defm: Storex_pat;
3614 defm: Storex_pat;
3615 defm: Storex_pat;
3616
3617 defm: Storex_pat, I32, s11_0ExtPred, S2_storerb_io>;
3618 defm: Storex_pat, I32, s11_1ExtPred, S2_storerh_io>;
3619 defm: Storex_pat, I32, s11_2ExtPred, S2_storeri_io>;
3620 defm: Storex_pat<SwapSt, I64, s11_3ExtPred, S2_storerd_io>;
3612 defm: Storex_pat<truncstorei8, I32, s32_0ImmPred, S2_storerb_io>;
3613 defm: Storex_pat;
3614 defm: Storex_pat;
3615 defm: Storex_pat;
3616
3617 defm: Storex_pat, I32, s32_0ImmPred, S2_storerb_io>;
3618 defm: Storex_pat, I32, s31_1ImmPred, S2_storerh_io>;
3619 defm: Storex_pat, I32, s30_2ImmPred, S2_storeri_io>;
3620 defm: Storex_pat, I64, s29_3ImmPred, S2_storerd_io>;
36213621 }
36223622
36233623 // Simple patterns should be tried with the least priority.
36323632 def: Storex_simple_pat, I64, S2_storerd_io>;
36333633
36343634 let AddedComplexity = 20 in {
3635 defm: Storexm_pat;
3636 defm: Storexm_pat;
3637 defm: Storexm_pat32, I64, s11_2ExtPred, LoReg, S2_storeri_io>;
3635 defm: Storexm_pat8, I64, s32_0ImmPred, LoReg, S2_storerb_io>;
3636 defm: Storexm_pat;
3637 defm: Storexm_pat;
36383638 }
36393639
36403640 def: Storexm_simple_pat;
44144414 // Patterns for loads of i1:
44154415 def: Pat<(i1 (load AddrFI:$fi)),
44164416 (C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>;
4417 def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s11_0ExtPred:$Off))),
4417 def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s32ImmPred:$Off))),
44184418 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
44194419 def: Pat<(i1 (load (i32 IntRegs:$Rs))),
44204420 (C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
44254425 def I32toI1: OutPatFrag<(ops node:$Rs),
44264426 (i1 (C2_tfrrp (i32 $Rs)))>;
44274427
4428 defm: Storexm_pat11_0ExtPred, I1toI32, S2_storerb_io>;
4428 defm: Storexm_pat32ImmPred, I1toI32, S2_storerb_io>;
44294429 def: Storexm_simple_pat;
44304430
44314431 //===----------------------------------------------------------------------===//
49164916 (C2_not PredRegs:$src1)>;
49174917
49184918 // Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
4919 def: Pat<(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s8ExtPred:$src3),
4920 (C2_muxii PredRegs:$src1, s8ExtPred:$src3, s8ImmPred:$src2)>;
4919 def: Pat<(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s32ImmPred:$src3),
4920 (C2_muxii PredRegs:$src1, s32ImmPred:$src3, s8ImmPred:$src2)>;
49214921
49224922 // Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
49234923 // => r0 = C2_muxir(p0, r1, #i)
4924 def: Pat<(select (not (i1 PredRegs:$src1)), s8ExtPred:$src2,
4924 def: Pat<(select (not (i1 PredRegs:$src1)), s32ImmPred:$src2,
49254925 (i32 IntRegs:$src3)),
4926 (C2_muxir PredRegs:$src1, IntRegs:$src3, s8ExtPred:$src2)>;
4926 (C2_muxir PredRegs:$src1, IntRegs:$src3, s32ImmPred:$src2)>;
49274927
49284928 // Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
49294929 // => r0 = C2_muxri (p0, #i, r1)
4930 def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s8ExtPred:$src3),
4931 (C2_muxri PredRegs:$src1, s8ExtPred:$src3, IntRegs:$src2)>;
4930 def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s32ImmPred:$src3),
4931 (C2_muxri PredRegs:$src1, s32ImmPred:$src3, IntRegs:$src2)>;
49324932
49334933 // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
49344934 def: Pat<(brcond (not (i1 PredRegs:$src1)), bb:$offset),
49934993
49944994 // rs <= rt -> !(rs > rt).
49954995 let AddedComplexity = 30 in
4996 def: Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
4997 (C2_not (C2_cmpgti IntRegs:$src1, s10ExtPred:$src2))>;
4996 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
4997 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
49984998
49994999 // rs <= rt -> !(rs > rt).
50005000 def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
50085008 // Hexagon_TODO: We should improve on this.
50095009 // rs != rt -> !(rs == rt).
50105010 let AddedComplexity = 30 in
5011 def: Pat<(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
5012 (C2_not (C2_cmpeqi IntRegs:$src1, s10ExtPred:$src2))>;
5011 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
5012 (C2_not (C2_cmpeqi IntRegs:$src1, s32ImmPred:$src2))>;
50135013
50145014 // Convert setne back to xor for hexagon since we compute w/ pred registers.
50155015 def: Pat<(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
50275027
50285028 // cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
50295029 let AddedComplexity = 30 in
5030 def: Pat<(i1 (setge (i32 IntRegs:$src1), s8ExtPred:$src2)),
5031 (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2))>;
5030 def: Pat<(i1 (setge (i32 IntRegs:$src1), s32ImmPred:$src2)),
5031 (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
50325032
50335033 // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
50345034 // rss >= rtt -> !(rtt > rss).
50395039 // !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
50405040 // rs < rt -> !(rs >= rt).
50415041 let AddedComplexity = 30 in
5042 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
5043 (C2_not (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
5042 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
5043 (C2_not (C2_cmpgti IntRegs:$src1,
5044 (DEC_CONST_SIGNED s32ImmPred:$src2)))>;
50445045
50455046 // Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
50465047 def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)),
50475048 (C2_cmpeq IntRegs:$src1, IntRegs:$src1)>;
50485049
50495050 // Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
5050 def: Pat<(i1 (setuge (i32 IntRegs:$src1), u8ExtPred:$src2)),
5051 (C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u8ExtPred:$src2))>;
5051 def: Pat<(i1 (setuge (i32 IntRegs:$src1), u32ImmPred:$src2)),
5052 (C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u32ImmPred:$src2))>;
50525053
50535054 // Generate cmpgtu(Rs, #u9)
5054 def: Pat<(i1 (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)),
5055 (C2_cmpgtui IntRegs:$src1, u9ExtPred:$src2)>;
5055 def: Pat<(i1 (setugt (i32 IntRegs:$src1), u32ImmPred:$src2)),
5056 (C2_cmpgtui IntRegs:$src1, u32ImmPred:$src2)>;
50565057
50575058 // Map from Rs >= Rt -> !(Rt > Rs).
50585059 // rs >= rt -> !(rt > rs).
58035804 // ALU32/64/Vector +
58045805 //===----------------------------------------------------------------------===///
58055806
5806 include "HexagonInstrInfoVector.td"
5807 include "HexagonInstrInfoVector.td"
268268 def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
269269 def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
270270
271 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
272 (A4_rcmpeqi IntRegs:$Rs, s8ExtPred:$s8)>;
273 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s8ExtPred:$s8)))),
274 (A4_rcmpneqi IntRegs:$Rs, s8ExtPred:$s8)>;
271 def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
272 (A4_rcmpeqi IntRegs:$Rs, s32ImmPred:$s8)>;
273 def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
274 (A4_rcmpneqi IntRegs:$Rs, s32ImmPred:$s8)>;
275275
276276 // Preserve the S2_tstbit_r generation
277277 def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
316316 // The complexity of the combines involving immediates should be greater
317317 // than the complexity of the combine with two registers.
318318 let AddedComplexity = 50 in {
319 def: Pat<(HexagonCOMBINE IntRegs:$r, s8ExtPred:$i),
320 (A4_combineri IntRegs:$r, s8ExtPred:$i)>;
321
322 def: Pat<(HexagonCOMBINE s8ExtPred:$i, IntRegs:$r),
323 (A4_combineir s8ExtPred:$i, IntRegs:$r)>;
319 def: Pat<(HexagonCOMBINE IntRegs:$r, s32ImmPred:$i),
320 (A4_combineri IntRegs:$r, s32ImmPred:$i)>;
321
322 def: Pat<(HexagonCOMBINE s32ImmPred:$i, IntRegs:$r),
323 (A4_combineir s32ImmPred:$i, IntRegs:$r)>;
324324 }
325325
326326 // A4_combineii: Set two small immediates.
342342 // The complexity of the combine with two immediates should be greater than
343343 // the complexity of a combine involving a register.
344344 let AddedComplexity = 75 in
345 def: Pat<(HexagonCOMBINE s8ImmPred:$s8, u6ExtPred:$u6),
345 def: Pat<(HexagonCOMBINE s8ImmPred:$s8, u32ImmPred:$u6),
346346 (A4_combineii imm:$s8, imm:$u6)>;
347347
348348 //===----------------------------------------------------------------------===//
374374 (VT (ValueMod (MI IntRegs:$Rs, 0)))>;
375375 }
376376
377 defm: Loadxm_pat;
378 defm: Loadxm_pat;
379 defm: Loadxm_pat;
380 defm: Loadxm_pat;
381 defm: Loadxm_pat;
382 defm: Loadxm_pat;
383 defm: Loadxm_pat;
384 defm: Loadxm_pat<sextloadi16, i64, Sext64, s11_1ExtPred, L2_loadrh_io>;
377 defm: Loadxm_pat<extloadi1, i64, Zext64, s32_0ImmPred, L2_loadrub_io>;
378 defm: Loadxm_pat;
379 defm: Loadxm_pat;
380 defm: Loadxm_pat;
381 defm: Loadxm_pat;
382 defm: Loadxm_pat;
383 defm: Loadxm_pat;
384 defm: Loadxm_pat;
385385
386386 // Map Rdd = anyext(Rs) -> Rdd = combine(#0, Rs).
387387 def: Pat<(i64 (anyext (i32 IntRegs:$src1))), (Zext64 IntRegs:$src1)>;
662662 (i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>;
663663
664664 let AddedComplexity = 100 in
665 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),
665 def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s30_2ImmPred:$offset)))),
666666 (i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
667 s11_2ExtPred:$offset)))>;
667 s30_2ImmPred:$offset)))>;
668668
669669 // anyext i32->i64
670670 def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
790790 PatFrag stOp> {
791791 def : Pat<(stOp (VT RC:$src4),
792792 (add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
793 u0AlwaysExtPred:$src3)),
794 (MI IntRegs:$src1, u2ImmPred:$src2, u0AlwaysExtPred:$src3, RC:$src4)>;
793 u32ImmPred:$src3)),
794 (MI IntRegs:$src1, u2ImmPred:$src2, u32ImmPred:$src3, RC:$src4)>;
795795
796796 def : Pat<(stOp (VT RC:$src4),
797797 (add (shl IntRegs:$src1, u2ImmPred:$src2),
11791179 // is not extendable. This could cause problems during removing the frame
11801180 // indices, since the offset with respect to R29/R30 may not fit in the
11811181 // u6 field.
1182 def: Storexm_add_pat8ExtPred, u6_0ImmPred, ToImmByte,
1182 def: Storexm_add_pat32ImmPred, u6_0ImmPred, ToImmByte,
11831183 S4_storeirb_io>;
1184 def: Storexm_add_pat8ExtPred, u6_1ImmPred, ToImmHalf,
1184 def: Storexm_add_pat32ImmPred, u6_1ImmPred, ToImmHalf,
11851185 S4_storeirh_io>;
1186 def: Storexm_add_pat8ExtPred, u6_2ImmPred, ToImmWord,
1186 def: Storexm_add_pat32ImmPred, u6_2ImmPred, ToImmWord,
11871187 S4_storeiri_io>;
11881188 }
11891189
1190 def: Storexm_simple_pat;
1191 def: Storexm_simple_pat;
1192 def: Storexm_simple_pat<store, s8ExtPred, ToImmWord, S4_storeiri_io>;
1190 def: Storexm_simple_pat<truncstorei8, s32ImmPred, ToImmByte, S4_storeirb_io>;
1191 def: Storexm_simple_pat;
1192 def: Storexm_simple_pat;
11931193
11941194 // memb(Rx++#s4:0:circ(Mu))=Rt
11951195 // memb(Rx++I:circ(Mu))=Rt
18441844
18451845 // PIC: Map from a block address computation to a PC-relative add
18461846 def: Pat<(Hexagongat_pcrel_ba tblockaddress:$src1),
1847 (C4_addipc u6ExtPred:$src1)>;
1847 (C4_addipc u32ImmPred:$src1)>;
18481848
18491849 // PIC: Map from the computation to generate a GOT pointer to a PC-relative add
18501850 def: Pat<(Hexagonpic_add texternalsym:$src1),
1851 (C4_addipc u6ExtPred:$src1)>;
1851 (C4_addipc u32ImmPred:$src1)>;
18521852
18531853 // PIC: Map from a jump table address computation to a PC-relative add
18541854 def: Pat<(Hexagongat_pcrel_jt tjumptable:$src1),
1855 (C4_addipc u6ExtPred:$src1)>;
1855 (C4_addipc u32ImmPred:$src1)>;
18561856
18571857 // PIC: Map from a GOT-relative symbol reference to a load
18581858 def: Pat<(Hexagonat_got (i32 IntRegs:$src1), tglobaladdr:$src2),
1859 (L2_loadri_io IntRegs:$src1, s11_2ExtPred:$src2)>;
1859 (L2_loadri_io IntRegs:$src1, s30_2ImmPred:$src2)>;
18601860
18611861 // PIC: Map from a static symbol reference to a PC-relative add
18621862 def: Pat<(Hexagongat_pcrel tglobaladdr:$src1),
1863 (C4_addipc u6ExtPred:$src1)>;
1863 (C4_addipc u32ImmPred:$src1)>;
18641864
18651865 //===----------------------------------------------------------------------===//
18661866 // CR -
19011901 (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
19021902 "$Rd = add($Rs, add($Ru, #$s6))" ,
19031903 [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
1904 (add (i32 IntRegs:$Ru), s6_16ExtPred:$s6)))],
1904 (add (i32 IntRegs:$Ru), s16_16ImmPred:$s6)))],
19051905 "", ALU64_tc_2_SLOT23> {
19061906 bits<5> Rd;
19071907 bits<5> Rs;
19421942 }
19431943
19441944 // Rd=add(Rs,sub(#s6,Ru))
1945 def: Pat<(add (i32 IntRegs:$src1), (sub s6_10ExtPred:$src2,
1945 def: Pat<(add (i32 IntRegs:$src1), (sub s32ImmPred:$src2,
19461946 (i32 IntRegs:$src3))),
1947 (S4_subaddi IntRegs:$src1, s6_10ExtPred:$src2, IntRegs:$src3)>;
1947 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
19481948
19491949 // Rd=sub(add(Rs,#s6),Ru)
1950 def: Pat<(sub (add (i32 IntRegs:$src1), s6_10ExtPred:$src2),
1950 def: Pat<(sub (add (i32 IntRegs:$src1), s32ImmPred:$src2),
19511951 (i32 IntRegs:$src3)),
1952 (S4_subaddi IntRegs:$src1, s6_10ExtPred:$src2, IntRegs:$src3)>;
1952 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
19531953
19541954 // Rd=add(sub(Rs,Ru),#s6)
19551955 def: Pat<(add (sub (i32 IntRegs:$src1), (i32 IntRegs:$src3)),
1956 (s6_10ExtPred:$src2)),
1957 (S4_subaddi IntRegs:$src1, s6_10ExtPred:$src2, IntRegs:$src3)>;
1956 (s32ImmPred:$src2)),
1957 (S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
19581958
19591959
19601960 // Add or subtract doublewords with carry.
21072107 (ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
21082108 "$Rx = or($Ru, and($_src_, #$s10))" ,
21092109 [(set (i32 IntRegs:$Rx),
2110 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s10ExtPred:$s10)))] ,
2110 (or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s32ImmPred:$s10)))] ,
21112111 "$_src_ = $Rx", ALU64_tc_2_SLOT23> {
21122112 bits<5> Rx;
21132113 bits<5> Ru;
22522252 (ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
22532253 "$Rx |= "#mnemonic#"($Rs, #$s10)",
22542254 [(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
2255 (OpNode (i32 IntRegs:$Rs), s10ExtPred:$s10)))],
2255 (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10)))],
22562256 "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
22572257 bits<5> Rx;
22582258 bits<5> Rs;
24142414 "$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
24152415 [(set (i32 IntRegs:$Rd),
24162416 (add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
2417 u6ExtPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
2417 u32ImmPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
24182418 bits<5> Rd;
24192419 bits<6> u6;
24202420 bits<5> Rs;
24392439 (ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
24402440 "$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
24412441 [(set (i32 IntRegs:$Rd),
2442 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u6ExtPred:$u6))],
2442 (add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u32ImmPred:$u6))],
24432443 "", ALU64_tc_3x_SLOT23>, ImmRegRel {
24442444 bits<5> Rd;
24452445 bits<6> u6;
24892489
24902490 let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
24912491 CextOpcode = "ADD_MPY", InputType = "imm" in
2492 def M4_mpyri_addr : T_AddMpy<0b1, u6ExtPred,
2492 def M4_mpyri_addr : T_AddMpy<0b1, u32ImmPred,
24932493 (ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
24942494
24952495 // Rx=add(Ru,mpyi(Rx,Rs))
26232623 : MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
26242624 "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
26252625 [(set (i32 IntRegs:$Rd),
2626 (Op (Sh I32:$Rx, u5ImmPred:$U5), u8ExtPred:$u8))],
2626 (Op (Sh I32:$Rx, u5ImmPred:$U5), u32ImmPred:$u8))],
26272627 "$Rd = $Rx", Itin> {
26282628
26292629 bits<5> Rd;
29582958 // mem[bh](Rs+#u6) += #U5
29592959 //===----------------------------------------------------------------------===//
29602960
2961 multiclass MemOpi_u5Pats ExtPred,
2961 multiclass MemOpi_u5Pats ImmPred,
29622962 InstHexagon MI, SDNode OpNode> {
29632963 let AddedComplexity = 180 in
29642964 def: Pat<(stOp (OpNode (ldOp IntRegs:$addr), u5ImmPred:$addend),
29662966 (MI IntRegs:$addr, 0, u5ImmPred:$addend)>;
29672967
29682968 let AddedComplexity = 190 in
2969 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ExtPred:$offset)),
2969 def: Pat<(stOp (OpNode (ldOp (add IntRegs:$base, ImmPred:$offset)),
29702970 u5ImmPred:$addend),
2971 (add IntRegs:$base, ExtPred:$offset)),
2972 (MI IntRegs:$base, ExtPred:$offset, u5ImmPred:$addend)>;
2973 }
2974
2975 multiclass MemOpi_u5ALUOp,
2971 (add IntRegs:$base, ImmPred:$offset)),
2972 (MI IntRegs:$base, ImmPred:$offset, u5ImmPred:$addend)>;
2973 }
2974
2975 multiclass MemOpi_u5ALUOp
29762976 InstHexagon addMI, InstHexagon subMI> {
2977 defm: MemOpi_u5Pats;
2978 defm: MemOpi_u5PatsExtPred, subMI, sub>;
2977 defm: MemOpi_u5PatsImmPred, addMI, add>;
2978 defm: MemOpi_u5Pats;
29792979 }
29802980
29812981 multiclass MemOpi_u5ExtType {
29822982 // Half Word
2983 defm: MemOpi_u5ALUOp 6_1ExtPred,
2983 defm: MemOpi_u5ALUOp 31_1ImmPred,
29842984 L4_iadd_memoph_io, L4_isub_memoph_io>;
29852985 // Byte
2986 defm: MemOpi_u5ALUOp 6ExtPred,
2986 defm: MemOpi_u5ALUOp 32ImmPred,
29872987 L4_iadd_memopb_io, L4_isub_memopb_io>;
29882988 }
29892989
29932993 defm: MemOpi_u5ExtType; // any extend
29942994
29952995 // Word
2996 defm: MemOpi_u5ALUOp 6_2ExtPred, L4_iadd_memopw_io,
2996 defm: MemOpi_u5ALUOp 30_2ImmPred, L4_iadd_memopw_io,
29972997 L4_isub_memopw_io>;
29982998 }
29992999
30043004 // mem[bh](Rs+#u6) += #m5
30053005 //===----------------------------------------------------------------------===//
30063006
3007 multiclass MemOpi_m5Pats extPred,
3007 multiclass MemOpi_m5Pats ImmPred,
30083008 PatLeaf immPred, SDNodeXForm xformFunc,
30093009 InstHexagon MI> {
30103010 let AddedComplexity = 190 in
30123012 (MI IntRegs:$addr, 0, (xformFunc immPred:$subend))>;
30133013
30143014 let AddedComplexity = 195 in
3015 def: Pat<(stOp (add (ldOp (add IntRegs:$base, extPred:$offset)),
3015 def: Pat<(stOp (add (ldOp (add IntRegs:$base, ImmPred:$offset)),
30163016 immPred:$subend),
3017 (add IntRegs:$base, extPred:$offset)),
3018 (MI IntRegs:$base, extPred:$offset, (xformFunc immPred:$subend))>;
3017 (add IntRegs:$base, ImmPred:$offset)),
3018 (MI IntRegs:$base, ImmPred:$offset, (xformFunc immPred:$subend))>;
30193019 }
30203020
30213021 multiclass MemOpi_m5ExtType {
30223022 // Half Word
3023 defm: MemOpi_m5Pats 6_1ExtPred, m5HImmPred,
3023 defm: MemOpi_m5Pats 31_1ImmPred, m5HImmPred,
30243024 MEMOPIMM_HALF, L4_isub_memoph_io>;
30253025 // Byte
3026 defm: MemOpi_m5Pats 6ExtPred, m5BImmPred,
3026 defm: MemOpi_m5Pats 32ImmPred, m5BImmPred,
30273027 MEMOPIMM_BYTE, L4_isub_memopb_io>;
30283028 }
30293029
30333033 defm: MemOpi_m5ExtType; // any extend
30343034
30353035 // Word
3036 defm: MemOpi_m5Pats 6_2ExtPred, m5ImmPred,
3036 defm: MemOpi_m5Pats 30_2ImmPred, m5ImmPred,
30373037 MEMOPIMM, L4_isub_memopw_io>;
30383038 }
30393039
30623062
30633063 multiclass MemOpi_bitExtType {
30643064 // Byte - clrbit
3065 defm: MemOpi_bitPats6ExtPred,
3065 defm: MemOpi_bitPats32ImmPred,
30663066 CLRMEMIMM_BYTE, L4_iand_memopb_io, and>;
30673067 // Byte - setbit
3068 defm: MemOpi_bitPats6ExtPred,
3068 defm: MemOpi_bitPats32ImmPred,
30693069 SETMEMIMM_BYTE, L4_ior_memopb_io, or>;
30703070 // Half Word - clrbit
3071 defm: MemOpi_bitPats6_1ExtPred,
3071 defm: MemOpi_bitPats31_1ImmPred,
30723072 CLRMEMIMM_SHORT, L4_iand_memoph_io, and>;
30733073 // Half Word - setbit
3074 defm: MemOpi_bitPats6_1ExtPred,
3074 defm: MemOpi_bitPats31_1ImmPred,
30753075 SETMEMIMM_SHORT, L4_ior_memoph_io, or>;
30763076 }
30773077
30843084
30853085 // memw(Rs+#0) = [clrbit|setbit](#U5)
30863086 // memw(Rs+#u6:2) = [clrbit|setbit](#U5)
3087 defm: MemOpi_bitPats6_2ExtPred, CLRMEMIMM,
3087 defm: MemOpi_bitPats30_2ImmPred, CLRMEMIMM,
30883088 L4_iand_memopw_io, and>;
3089 defm: MemOpi_bitPats6_2ExtPred, SETMEMIMM,
3089 defm: MemOpi_bitPats30_2ImmPred, SETMEMIMM,
30903090 L4_ior_memopw_io, or>;
30913091 }
30923092
31243124
31253125 multiclass MemOPr_ExtType {
31263126 // Half Word
3127 defm: MemOPr_ALUOp 6_1ExtPred,
3127 defm: MemOPr_ALUOp 31_1ImmPred,
31283128 L4_add_memoph_io, L4_sub_memoph_io,
31293129 L4_and_memoph_io, L4_or_memoph_io>;
31303130 // Byte
3131 defm: MemOPr_ALUOp 6ExtPred,
3131 defm: MemOPr_ALUOp 32ImmPred,
31323132 L4_add_memopb_io, L4_sub_memopb_io,
31333133 L4_and_memopb_io, L4_or_memopb_io>;
31343134 }
31403140 defm: MemOPr_ExtType; // sign extend
31413141 defm: MemOPr_ExtType; // any extend
31423142 // Word
3143 defm: MemOPr_ALUOp 6_2ExtPred, L4_add_memopw_io,
3143 defm: MemOPr_ALUOp 30_2ImmPred, L4_add_memopw_io,
31443144 L4_sub_memopw_io, L4_and_memopw_io, L4_or_memopw_io>;
31453145 }
31463146
31643164 def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
31653165 def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9Ext>;
31663166
3167 def : T_CMP_pat ;
3168 def : T_CMP_pat ltei, setle, s10ExtPred>;
3167 def : T_CMP_pat neqi, setne, s32ImmPred>;
3168 def : T_CMP_pat ;
31693169 def : T_CMP_pat ;
31703170
31713171 // rs <= rt -> !(rs > rt).
31723172 /*
3173 def: Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
3174 (C2_not (C2_cmpgti IntRegs:$src1, s10ExtPred:$src2))>;
3175 // (C4_cmpltei IntRegs:$src1, s10ExtPred:$src2)>;
3173 def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
3174 (C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
3175 // (C4_cmpltei IntRegs:$src1, s32ImmPred:$src2)>;
31763176 */
31773177 // Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
3178 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
3179 (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2))>;
3178 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
3179 (C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
31803180
31813181 // rs != rt -> !(rs == rt).
3182 def: Pat<(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
3183 (C4_cmpneqi IntRegs:$src1, s10ExtPred:$src2)>;
3182 def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
3183 (C4_cmpneqi IntRegs:$src1, s32ImmPred:$src2)>;
31843184
31853185 // SDNode for converting immediate C to C-1.
31863186 def DEC_CONST_BYTE : SDNodeXForm
33553355 //===----------------------------------------------------------------------===//
33563356 class T_StoreAbs
33573357 bits<2> MajOp, bit isHalf>
3358 : T_StoreAbsGP 0AlwaysExt, 1, isHalf>,
3358 : T_StoreAbsGP 32Imm, 1, isHalf>,
33593359 AddrModeRel {
33603360 string ImmOpStr = !cast(ImmOp);
33613361 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
33963396 let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1,
33973397 isNewValue = 1, opNewValue = 1 in
33983398 class T_StoreAbsGP_NV MajOp, bit isAbs>
3399 : NVInst_V4<(outs), (ins u0AlwaysExt:$addr, IntRegs:$src),
3399 : NVInst_V4<(outs), (ins u32Imm:$addr, IntRegs:$src),
34003400 mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src.new",
34013401 [], "", V2LDST_tc_st_SLOT0> {
34023402 bits<19> addr;
36263626
36273627 class T_LoadAbs
36283628 bits<3> MajOp>
3629 : T_LoadAbsGP 0AlwaysExt, 1>, AddrModeRel {
3629 : T_LoadAbsGP 32Imm, 1>, AddrModeRel {
36303630
36313631 string ImmOpStr = !cast(ImmOp);
36323632 let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
37863786 def: Pat<(i64 (cttz I64:$src1)), (Zext64 (S2_ct0p I64:$src1))>;
37873787
37883788 let AddedComplexity = 30 in {
3789 def: Storea_pat;
3790 def: Storea_pat;
3791 def: Storea_pat<store, I32, u0AlwaysExtPred, S2_storeriabs>;
3789 def: Storea_pat<truncstorei8, I32, u32ImmPred, S2_storerbabs>;
3790 def: Storea_pat;
3791 def: Storea_pat;
37923792 }
37933793
37943794 let AddedComplexity = 30 in {
3795 def: Loada_pat;
3796 def: Loada_pat;
3797 def: Loada_pat;
3798 def: Loada_pat;
3799 def: Loada_pat<zextloadi16, i32, u0AlwaysExtPred, L4_loadruh_abs>;
3795 def: Loada_pat<load, i32, u32ImmPred, L4_loadri_abs>;
3796 def: Loada_pat;
3797 def: Loada_pat;
3798 def: Loada_pat;
3799 def: Loada_pat;
38003800 }
38013801
38023802 // Indexed store word - global address.
138138 let Inst{20-16} = Rss;
139139 }
140140
141 defm: Loadx_pat;
142 defm: Loadx_pat;
143
144 defm: Storex_pat;
145 defm: Storex_pat_io>;
141 defm: Loadx_pat_io>;
142 defm: Loadx_pat;
143
144 defm: Storex_pat;
145 defm: Storex_pat;
146146 def: Storex_simple_pat;
147147 def: Storex_simple_pat;
148148
689689 def: T_RR_pat;
690690 def: T_RR_pat;
691691
692 def: T_II_pat;
693
694 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs),
695 (I32:$Rt))),
692 def: T_II_pat;
693
694 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs), (I32:$Rt))),
696695 (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
697696
698697 // Mux
699 def : T_QRI_pat;
700 def : T_QIR_pat;
701 def : T_QII_patImmPred>;
698 def : T_QRI_patImmPred>;
699 def : T_QIR_pat;
700 def : T_QII_pat;
702701
703702 // Shift halfword
704703 def : T_R_pat;
719718 def : T_RR_pat;
720719 def : T_RR_pat;
721720
722 def : T_RI_pat;
723 def : T_RI_pat;
724 def : T_RI_pat;
725
726 def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s8ExtPred:$src2)),
721 def : T_RI_pat;
722 def : T_RI_pat;
723 def : T_RI_pat;
724
725 def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s32ImmPred:$src2)),
727726 (i32 (C2_cmpgti (I32:$src1),
728 (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
729
730 def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u8ExtPred:$src2)),
727 (DEC_CONST_SIGNED s32ImmPred:$src2)))>;
728
729 def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u32ImmPred:$src2)),
731730 (i32 (C2_cmpgtui (I32:$src1),
732 (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
731 (DEC_CONST_UNSIGNED u32ImmPred:$src2)))>;
733732
734733 // The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0.
735734 def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), 0)),
233233 *********************************************************************/
234234
235235 // Combine Words Into Doublewords.
236 def: T_RI_pat;
237 def: T_IR_patPred>;
236 def: T_RI_patPred>;
237 def: T_IR_pat;
238238
239239 /********************************************************************
240240 * ALU32/PRED *
241241 *********************************************************************/
242242
243243 // Compare
244 def : T_RI_pat;
245 def : T_RI_pat;
246 def : T_RI_patlteui, int_hexagon_C4_cmplteui, u9ExtPred>;
244 def : T_RI_patneqi, int_hexagon_C4_cmpneqi, s32ImmPred>;
245 def : T_RI_pat;
246 def : T_RI_pat;
247247
248248 def: T_RR_pat;
249249 def: T_RR_pat;
6565 // Immediate predicates
6666 //
6767 def s32ImmPred : PatLeaf<(i32 imm), [{
68 // s32ImmPred predicate - True if the immediate fits in a 32-bit sign extended
69 // field.
7068 int64_t v = (int64_t)N->getSExtValue();
7169 return isInt<32>(v);
7270 }]>;
7371
74 def s32_24ImmPred : PatLeaf<(i32 imm), [{
75 // s32_24ImmPred predicate - True if the immediate fits in a 32-bit sign
76 // extended field that is a multiple of 0x1000000.
77 int64_t v = (int64_t)N->getSExtValue();
78 return isShiftedInt<32,24>(v);
79 }]>;
80
81 def s32_16s8ImmPred : PatLeaf<(i32 imm), [{
82 // s32_16s8ImmPred predicate - True if the immediate fits in a 32-bit sign
83 // extended field that is a multiple of 0x10000.
84 int64_t v = (int64_t)N->getSExtValue();
85 return isShiftedInt<24,16>(v);
72 def s32_0ImmPred : PatLeaf<(i32 imm), [{
73 int64_t v = (int64_t)N->getSExtValue();
74 return isInt<32>(v);
75 }]>;
76
77 def s31_1ImmPred : PatLeaf<(i32 imm), [{
78 int64_t v = (int64_t)N->getSExtValue();
79 return isShiftedInt<31,1>(v);
80 }]>;
81
82 def s30_2ImmPred : PatLeaf<(i32 imm), [{
83 int64_t v = (int64_t)N->getSExtValue();
84 return isShiftedInt<31,1>(v);
85 }]>;
86
87 def s29_3ImmPred : PatLeaf<(i32 imm), [{
88 int64_t v = (int64_t)N->getSExtValue();
89 return isShiftedInt<31,1>(v);
90 }]>;
91
92 def s22_10ImmPred : PatLeaf<(i32 imm), [{
93 int64_t v = (int64_t)N->getSExtValue();
94 return isShiftedInt<22,10>(v);
95 }]>;
96
97 def s8_24ImmPred : PatLeaf<(i32 imm), [{
98 int64_t v = (int64_t)N->getSExtValue();
99 return isShiftedInt<8,24>(v);
100 }]>;
101
102 def s16_16ImmPred : PatLeaf<(i32 imm), [{
103 int64_t v = (int64_t)N->getSExtValue();
104 return isShiftedInt<16,16>(v);
86105 }]>;
87106
88107 def s26_6ImmPred : PatLeaf<(i32 imm), [{
89 // s26_6ImmPred predicate - True if the immediate fits in a 32-bit
90 // sign extended field.
91108 int64_t v = (int64_t)N->getSExtValue();
92109 return isShiftedInt<26,6>(v);
93110 }]>;
94111
95
96112 def s16ImmPred : PatLeaf<(i32 imm), [{
97 // s16ImmPred predicate - True if the immediate fits in a 16-bit sign extended
98 // field.
99113 int64_t v = (int64_t)N->getSExtValue();
100114 return isInt<16>(v);
101115 }]>;
102116
103
104117 def s13ImmPred : PatLeaf<(i32 imm), [{
105 // s13ImmPred predicate - True if the immediate fits in a 13-bit sign extended
106 // field.
107118 int64_t v = (int64_t)N->getSExtValue();
108119 return isInt<13>(v);
109120 }]>;
110121
111
112122 def s12ImmPred : PatLeaf<(i32 imm), [{
113 // s12ImmPred predicate - True if the immediate fits in a 12-bit
114 // sign extended field.
115123 int64_t v = (int64_t)N->getSExtValue();
116124 return isInt<12>(v);
117125 }]>;
118126
119127 def s11_0ImmPred : PatLeaf<(i32 imm), [{
120 // s11_0ImmPred predicate - True if the immediate fits in a 11-bit
121 // sign extended field.
122128 int64_t v = (int64_t)N->getSExtValue();
123129 return isInt<11>(v);
124130 }]>;
125131
126
127132 def s11_1ImmPred : PatLeaf<(i32 imm), [{
128 // s11_1ImmPred predicate - True if the immediate fits in a 12-bit
129 // sign extended field and is a multiple of 2.
130133 int64_t v = (int64_t)N->getSExtValue();
131134 return isShiftedInt<11,1>(v);
132135 }]>;
133136
134
135137 def s11_2ImmPred : PatLeaf<(i32 imm), [{
136 // s11_2ImmPred predicate - True if the immediate fits in a 13-bit
137 // sign extended field and is a multiple of 4.
138138 int64_t v = (int64_t)N->getSExtValue();
139139 return isShiftedInt<11,2>(v);
140140 }]>;
141141
142
143142 def s11_3ImmPred : PatLeaf<(i32 imm), [{
144 // s11_3ImmPred predicate - True if the immediate fits in a 14-bit
145 // sign extended field and is a multiple of 8.
146143 int64_t v = (int64_t)N->getSExtValue();
147144 return isShiftedInt<11,3>(v);
148145 }]>;
149146
150
151147 def s10ImmPred : PatLeaf<(i32 imm), [{
152 // s10ImmPred predicate - True if the immediate fits in a 10-bit sign extended
153 // field.
154148 int64_t v = (int64_t)N->getSExtValue();
155149 return isInt<10>(v);
156150 }]>;
157151
158
159152 def s9ImmPred : PatLeaf<(i32 imm), [{
160 // s9ImmPred predicate - True if the immediate fits in a 9-bit sign extended
161 // field.
162153 int64_t v = (int64_t)N->getSExtValue();
163154 return isInt<9>(v);
164155 }]>;
165156
166157 def m9ImmPred : PatLeaf<(i32 imm), [{
167 // m9ImmPred predicate - True if the immediate fits in a 9-bit magnitude
168 // field. The range of m9 is -255 to 255.
169158 int64_t v = (int64_t)N->getSExtValue();
170159 return isInt<9>(v) && (v != -256);
171160 }]>;
172161
173162 def s8ImmPred : PatLeaf<(i32 imm), [{
174 // s8ImmPred predicate - True if the immediate fits in a 8-bit sign extended
175 // field.
176163 int64_t v = (int64_t)N->getSExtValue();
177164 return isInt<8>(v);
178165 }]>;
179166
180
181167 def s8Imm64Pred : PatLeaf<(i64 imm), [{
182 // s8ImmPred predicate - True if the immediate fits in a 8-bit sign extended
183 // field.
184168 int64_t v = (int64_t)N->getSExtValue();
185169 return isInt<8>(v);
186170 }]>;
187171
188
189172 def s6ImmPred : PatLeaf<(i32 imm), [{
190 // s6ImmPred predicate - True if the immediate fits in a 6-bit sign extended
191 // field.
192173 int64_t v = (int64_t)N->getSExtValue();
193174 return isInt<6>(v);
194175 }]>;
195176
196
197177 def s4_0ImmPred : PatLeaf<(i32 imm), [{
198 // s4_0ImmPred predicate - True if the immediate fits in a 4-bit sign extended
199 // field.
200178 int64_t v = (int64_t)N->getSExtValue();
201179 return isInt<4>(v);
202180 }]>;
203181
204
205182 def s4_1ImmPred : PatLeaf<(i32 imm), [{
206 // s4_1ImmPred predicate - True if the immediate fits in a 4-bit sign extended
207 // field of 2.
208183 int64_t v = (int64_t)N->getSExtValue();
209184 return isShiftedInt<4,1>(v);
210185 }]>;
211186
212
213187 def s4_2ImmPred : PatLeaf<(i32 imm), [{
214 // s4_2ImmPred predicate - True if the immediate fits in a 4-bit sign extended
215 // field that is a multiple of 4.
216188 int64_t v = (int64_t)N->getSExtValue();
217189 return isShiftedInt<4,2>(v);
218190 }]>;
219191
220
221192 def s4_3ImmPred : PatLeaf<(i32 imm), [{
222 // s4_3ImmPred predicate - True if the immediate fits in a 4-bit sign extended
223 // field that is a multiple of 8.
224193 int64_t v = (int64_t)N->getSExtValue();
225194 return isShiftedInt<4,3>(v);
226195 }]>;
232201 }]>;
233202
234203 def u32ImmPred : PatLeaf<(i32 imm), [{
235 // u32ImmPred predicate - True if the immediate fits in a 32-bit field.
236204 int64_t v = (int64_t)N->getSExtValue();
237205 return isUInt<32>(v);
238206 }]>;
239207
208 def u32_0ImmPred : PatLeaf<(i32 imm), [{
209 int64_t v = (int64_t)N->getSExtValue();
210 return isUInt<32>(v);
211 }]>;
212
213 def u31_1ImmPred : PatLeaf<(i32 imm), [{
214 int64_t v = (int64_t)N->getSExtValue();
215 return isShiftedUInt<31,1>(v);
216 }]>;
217
218 def u30_2ImmPred : PatLeaf<(i32 imm), [{
219 int64_t v = (int64_t)N->getSExtValue();
220 return isShiftedUInt<30,2>(v);
221 }]>;
222
223 def u29_3ImmPred : PatLeaf<(i32 imm), [{
224 int64_t v = (int64_t)N->getSExtValue();
225 return isShiftedUInt<29,3>(v);
226 }]>;
227
240228 def u26_6ImmPred : PatLeaf<(i32 imm), [{
241 // u26_6ImmPred - True if the immediate fits in a 32-bit field and
242 // is a multiple of 64.
243229 int64_t v = (int64_t)N->getSExtValue();
244230 return isShiftedUInt<26,6>(v);
245231 }]>;
246232
247233 def u16ImmPred : PatLeaf<(i32 imm), [{
248 // u16ImmPred predicate - True if the immediate fits in a 16-bit unsigned
249 // field.
250234 int64_t v = (int64_t)N->getSExtValue();
251235 return isUInt<16>(v);
252236 }]>;
253237
254238 def u16_s8ImmPred : PatLeaf<(i32 imm), [{
255 // u16_s8ImmPred predicate - True if the immediate fits in a 16-bit sign
256 // extended s8 field.
257239 int64_t v = (int64_t)N->getSExtValue();
258240 return isShiftedUInt<16,8>(v);
259241 }]>;
260242
261243 def u16_0ImmPred : PatLeaf<(i32 imm), [{
262 // True if the immediate fits in a 16-bit unsigned field.
263244 int64_t v = (int64_t)N->getSExtValue();
264245 return isUInt<16>(v);
265246 }]>;
266247
267248 def u11_3ImmPred : PatLeaf<(i32 imm), [{
268 // True if the immediate fits in a 14-bit unsigned field, and the lowest
269 // three bits are 0.
270249 int64_t v = (int64_t)N->getSExtValue();
271250 return isShiftedUInt<11,3>(v);
272251 }]>;
273252
274253 def u9ImmPred : PatLeaf<(i32 imm), [{
275 // u9ImmPred predicate - True if the immediate fits in a 9-bit unsigned
276 // field.
277254 int64_t v = (int64_t)N->getSExtValue();
278255 return isUInt<9>(v);
279256 }]>;
280257
281
282258 def u8ImmPred : PatLeaf<(i32 imm), [{
283 // u8ImmPred predicate - True if the immediate fits in a 8-bit unsigned
284 // field.
285259 int64_t v = (int64_t)N->getSExtValue();
286260 return isUInt<8>(v);
287261 }]>;
293267 }]>;
294268
295269 def u7ImmPred : PatLeaf<(i32 imm), [{
296 // u7ImmPred predicate - True if the immediate fits in a 7-bit unsigned
297 // field.
298270 int64_t v = (int64_t)N->getSExtValue();
299271 return isUInt<7>(v);
300272 }]>;
301273
302
303274 def u6ImmPred : PatLeaf<(i32 imm), [{
304 // u6ImmPred predicate - True if the immediate fits in a 6-bit unsigned
305 // field.
306275 int64_t v = (int64_t)N->getSExtValue();
307276 return isUInt<6>(v);
308277 }]>;
309278
310279 def u6_0ImmPred : PatLeaf<(i32 imm), [{
311 // u6_0ImmPred predicate - True if the immediate fits in a 6-bit unsigned
312 // field. Same as u6ImmPred.
313280 int64_t v = (int64_t)N->getSExtValue();
314281 return isUInt<6>(v);
315282 }]>;
316283
317284 def u6_1ImmPred : PatLeaf<(i32 imm), [{
318 // u6_1ImmPred predicate - True if the immediate fits in a 7-bit unsigned
319 // field that is 1 bit alinged - multiple of 2.
320285 int64_t v = (int64_t)N->getSExtValue();
321286 return isShiftedUInt<6,1>(v);
322287 }]>;
323288
324289 def u6_2ImmPred : PatLeaf<(i32 imm), [{
325 // u6_2ImmPred predicate - True if the immediate fits in a 8-bit unsigned
326 // field that is 2 bits alinged - multiple of 4.
327290 int64_t v = (int64_t)N->getSExtValue();
328291 return isShiftedUInt<6,2>(v);
329292 }]>;
330293
331294 def u6_3ImmPred : PatLeaf<(i32 imm), [{
332 // u6_3ImmPred predicate - True if the immediate fits in a 9-bit unsigned
333 // field that is 3 bits alinged - multiple of 8.
334295 int64_t v = (int64_t)N->getSExtValue();
335296 return isShiftedUInt<6,3>(v);
336297 }]>;
337298
338299 def u5ImmPred : PatLeaf<(i32 imm), [{
339 // u5ImmPred predicate - True if the immediate fits in a 5-bit unsigned
340 // field.
341300 int64_t v = (int64_t)N->getSExtValue();
342301 return isUInt<5>(v);
343302 }]>;
344303
345304 def u4ImmPred : PatLeaf<(i32 imm), [{
346 // u4ImmPred predicate - True if the immediate fits in a 4-bit unsigned
347 // field.
348305 int64_t v = (int64_t)N->getSExtValue();
349306 return isUInt<4>(v);
350307 }]>;
351308
352309 def u3ImmPred : PatLeaf<(i32 imm), [{
353 // u3ImmPred predicate - True if the immediate fits in a 3-bit unsigned
354 // field.
355310 int64_t v = (int64_t)N->getSExtValue();
356311 return isUInt<3>(v);
357312 }]>;
358313
359
360314 def u2ImmPred : PatLeaf<(i32 imm), [{
361 // u2ImmPred predicate - True if the immediate fits in a 2-bit unsigned
362 // field.
363315 int64_t v = (int64_t)N->getSExtValue();
364316 return isUInt<2>(v);
365317 }]>;
366318
367
368319 def u1ImmPred : PatLeaf<(i1 imm), [{
369 // u1ImmPred predicate - True if the immediate fits in a 1-bit unsigned
370 // field.
371320 int64_t v = (int64_t)N->getSExtValue();
372321 return isUInt<1>(v);
373322 }]>;
510459 def u6_3Ext : Operand;
511460 }
512461
513 let PrintMethod = "printImmOperand" in
514 def u0AlwaysExt : Operand;
515
516 // Predicates for constant extendable operands
517 def s16ExtPred : PatLeaf<(i32 imm), [{
518 int64_t v = (int64_t)N->getSExtValue();
519 if (isInt<16>(v))
520 return true;
521
522 // Return true if extending this immediate is profitable and the value
523 // can fit in a 32-bit signed field.
524 return isConstExtProfitable(Node) && isInt<32>(v);
525 }]>;
526
527 def s10ExtPred : PatLeaf<(i32 imm), [{
528 int64_t v = (int64_t)N->getSExtValue();
529 if (isInt<10>(v))
530 return true;
531
532 // Return true if extending this immediate is profitable and the value
533 // can fit in a 32-bit signed field.
534 return isConstExtProfitable(Node) && isInt<32>(v);
535 }]>;
536
537 def s9ExtPred : PatLeaf<(i32 imm), [{
538 int64_t v = (int64_t)N->getSExtValue();
539 if (isInt<9>(v))
540 return true;
541
542 // Return true if extending this immediate is profitable and the value
543 // can fit in a 32-bit unsigned field.
544 return isConstExtProfitable(Node) && isInt<32>(v);
545 }]>;
546
547 def s8ExtPred : PatLeaf<(i32 imm), [{
548 int64_t v = (int64_t)N->getSExtValue();
549 if (isInt<8>(v))
550 return true;
551
552 // Return true if extending this immediate is profitable and the value
553 // can fit in a 32-bit signed field.
554 return isConstExtProfitable(Node) && isInt<32>(v);
555 }]>;
556
557 def s8_16ExtPred : PatLeaf<(i32 imm), [{
558 int64_t v = (int64_t)N->getSExtValue();
559 if (isInt<8>(v))
560 return true;
561
562 // Return true if extending this immediate is profitable and the value
563 // can't fit in a 16-bit signed field. This is required to avoid
564 // unnecessary constant extenders.
565 return isConstExtProfitable(Node) && !isInt<16>(v);
566 }]>;
567
568 def s6ExtPred : PatLeaf<(i32 imm), [{
569 int64_t v = (int64_t)N->getSExtValue();
570 if (isInt<6>(v))
571 return true;
572
573 // Return true if extending this immediate is profitable and the value
574 // can fit in a 32-bit unsigned field.
575 return isConstExtProfitable(Node) && isInt<32>(v);
576 }]>;
577
578 def s6_16ExtPred : PatLeaf<(i32 imm), [{
579 int64_t v = (int64_t)N->getSExtValue();
580 if (isInt<6>(v))
581 return true;
582
583 // Return true if extending this immediate is profitable and the value
584 // can't fit in a 16-bit signed field. This is required to avoid
585 // unnecessary constant extenders.
586 return isConstExtProfitable(Node) && !isInt<16>(v);
587 }]>;
588
589 def s6_10ExtPred : PatLeaf<(i32 imm), [{
590 int64_t v = (int64_t)N->getSExtValue();
591 if (isInt<6>(v))
592 return true;
593
594 // Return true if extending this immediate is profitable and the value
595 // can't fit in a 10-bit signed field. This is required to avoid
596 // unnecessary constant extenders.
597 return isConstExtProfitable(Node) && !isInt<10>(v);
598 }]>;
599
600 def s11_0ExtPred : PatLeaf<(i32 imm), [{
601 int64_t v = (int64_t)N->getSExtValue();
602 if (isInt<11>(v))
603 return true;
604
605 // Return true if extending this immediate is profitable and the value
606 // can fit in a 32-bit signed field.
607 return isConstExtProfitable(Node) && isInt<32>(v);
608 }]>;
609
610 def s11_1ExtPred : PatLeaf<(i32 imm), [{
611 int64_t v = (int64_t)N->getSExtValue();
612 if (isInt<12>(v))
613 return isShiftedInt<11,1>(v);
614
615 // Return true if extending this immediate is profitable and the low 1 bit
616 // is zero (2-byte aligned).
617 return isConstExtProfitable(Node) && isInt<32>(v) && ((v % 2) == 0);
618 }]>;
619
620 def s11_2ExtPred : PatLeaf<(i32 imm), [{
621 int64_t v = (int64_t)N->getSExtValue();
622 if (isInt<13>(v))
623 return isShiftedInt<11,2>(v);
624
625 // Return true if extending this immediate is profitable and the low 2-bits
626 // are zero (4-byte aligned).
627 return isConstExtProfitable(Node) && isInt<32>(v) && ((v % 4) == 0);
628 }]>;
629
630 def s11_3ExtPred : PatLeaf<(i32 imm), [{
631 int64_t v = (int64_t)N->getSExtValue();
632 if (isInt<14>(v))
633 return isShiftedInt<11,3>(v);
634
635 // Return true if extending this immediate is profitable and the low 3-bits
636 // are zero (8-byte aligned).
637 return isConstExtProfitable(Node) && isInt<32>(v) && ((v % 8) == 0);
638 }]>;
639
640 def u0AlwaysExtPred : PatLeaf<(i32 imm), [{
641 // Predicate for an unsigned 32-bit value that always needs to be extended.
642 if (isConstExtProfitable(Node)) {
643 int64_t v = (int64_t)N->getSExtValue();
644 return isUInt<32>(v);
645 }
646 return false;
647 }]>;
648
649 def u6ExtPred : PatLeaf<(i32 imm), [{
650 int64_t v = (int64_t)N->getSExtValue();
651 if (isUInt<6>(v))
652 return true;
653
654 // Return true if extending this immediate is profitable and the value
655 // can fit in a 32-bit unsigned field.
656 return isConstExtProfitable(Node) && isUInt<32>(v);
657 }]>;
658
659 def u7ExtPred : PatLeaf<(i32 imm), [{
660 int64_t v = (int64_t)N->getSExtValue();
661 if (isUInt<7>(v))
662 return true;
663
664 // Return true if extending this immediate is profitable and the value
665 // can fit in a 32-bit unsigned field.
666 return isConstExtProfitable(Node) && isUInt<32>(v);
667 }]>;
668
669 def u8ExtPred : PatLeaf<(i32 imm), [{
670 int64_t v = (int64_t)N->getSExtValue();
671 if (isUInt<8>(v))
672 return true;
673
674 // Return true if extending this immediate is profitable and the value
675 // can fit in a 32-bit unsigned field.
676 return isConstExtProfitable(Node) && isUInt<32>(v);
677 }]>;
678
679 def u9ExtPred : PatLeaf<(i32 imm), [{
680 int64_t v = (int64_t)N->getSExtValue();
681 if (isUInt<9>(v))
682 return true;
683
684 // Return true if extending this immediate is profitable and the value
685 // can fit in a 32-bit unsigned field.
686 return isConstExtProfitable(Node) && isUInt<32>(v);
687 }]>;
688
689 def u6_1ExtPred : PatLeaf<(i32 imm), [{
690 int64_t v = (int64_t)N->getSExtValue();
691 if (isUInt<7>(v))
692 return isShiftedUInt<6,1>(v);
693
694 // Return true if extending this immediate is profitable and the value
695 // can fit in a 32-bit unsigned field.
696 return isConstExtProfitable(Node) && isUInt<32>(v) && ((v % 2) == 0);
697 }]>;
698
699 def u6_2ExtPred : PatLeaf<(i32 imm), [{
700 int64_t v = (int64_t)N->getSExtValue();
701 if (isUInt<8>(v))
702 return isShiftedUInt<6,2>(v);
703
704 // Return true if extending this immediate is profitable and the value
705 // can fit in a 32-bit unsigned field.
706 return isConstExtProfitable(Node) && isUInt<32>(v) && ((v % 4) == 0);
707 }]>;
708
709 def u6_3ExtPred : PatLeaf<(i32 imm), [{
710 int64_t v = (int64_t)N->getSExtValue();
711 if (isUInt<9>(v))
712 return isShiftedUInt<6,3>(v);
713
714 // Return true if extending this immediate is profitable and the value
715 // can fit in a 32-bit unsigned field.
716 return isConstExtProfitable(Node) && isUInt<32>(v) && ((v % 8) == 0);
717 }]>;
718
719462
720463 // This complex pattern exists only to create a machine instruction operand
721464 // of type "frame index". There doesn't seem to be a way to do that directly