llvm.org GIT mirror llvm / 9a0352f
Merging r343443: ------------------------------------------------------------------------ r343443 | ctopper | 2018-10-01 00:08:41 -0700 (Mon, 01 Oct 2018) | 9 lines [X86] Stop X86DomainReassignment from creating copies between GR8/GR16 physical registers and k-registers. We can only copy between a k-register and a GR32/GR64 register. This patch detects that the copy will be illegal and prevents the domain reassignment from happening for that closure. This probably isn't the best fix, and we should probably figure out how to handle this correctly. Fixes PR38803. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@344804 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
2 changed file(s) with 69 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
215215
216216 InstrCOPYReplacer(unsigned SrcOpcode, RegDomain DstDomain, unsigned DstOpcode)
217217 : InstrReplacer(SrcOpcode, DstOpcode), DstDomain(DstDomain) {}
218
219 bool isLegal(const MachineInstr *MI,
220 const TargetInstrInfo *TII) const override {
221 if (!InstrConverterBase::isLegal(MI, TII))
222 return false;
223
224 // Don't allow copies to/flow GR8/GR16 physical registers.
225 // FIXME: Is there some better way to support this?
226 unsigned DstReg = MI->getOperand(0).getReg();
227 if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
228 (X86::GR8RegClass.contains(DstReg) ||
229 X86::GR16RegClass.contains(DstReg)))
230 return false;
231 unsigned SrcReg = MI->getOperand(1).getReg();
232 if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
233 (X86::GR8RegClass.contains(SrcReg) ||
234 X86::GR16RegClass.contains(SrcReg)))
235 return false;
236
237 return true;
238 }
218239
219240 double getExtraCost(const MachineInstr *MI,
220241 MachineRegisterInfo *MRI) const override {
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mcpu=skylake-avx512 -mtriple=x86_64-unknown-unknown | FileCheck %s
2
3 @b = local_unnamed_addr global i32 0, align 4
4 @c = local_unnamed_addr global i32 0, align 4
5 @d = local_unnamed_addr global float 0.000000e+00, align 4
6
7 define float @_Z3fn2v() {
8 ; CHECK-LABEL: _Z3fn2v:
9 ; CHECK: # %bb.0: # %entry
10 ; CHECK-NEXT: pushq %rax
11 ; CHECK-NEXT: .cfi_def_cfa_offset 16
12 ; CHECK-NEXT: callq _Z1av
13 ; CHECK-NEXT: # kill: def $al killed $al def $eax
14 ; CHECK-NEXT: kmovd %eax, %k1
15 ; CHECK-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
16 ; CHECK-NEXT: vmovss %xmm0, %xmm0, %xmm0 {%k1} {z}
17 ; CHECK-NEXT: cmpl $0, {{.*}}(%rip)
18 ; CHECK-NEXT: je .LBB0_2
19 ; CHECK-NEXT: # %bb.1: # %if.then
20 ; CHECK-NEXT: vcvtsi2ssl {{.*}}(%rip), %xmm1, %xmm1
21 ; CHECK-NEXT: kmovd %eax, %k1
22 ; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
23 ; CHECK-NEXT: vmovss %xmm2, %xmm0, %xmm1 {%k1}
24 ; CHECK-NEXT: vmovss %xmm1, {{.*}}(%rip)
25 ; CHECK-NEXT: .LBB0_2: # %if.end
26 ; CHECK-NEXT: popq %rax
27 ; CHECK-NEXT: .cfi_def_cfa_offset 8
28 ; CHECK-NEXT: retq
29 entry:
30 %call = tail call zeroext i1 @_Z1av()
31 %cond = select i1 %call, float 7.500000e-01, float 0.000000e+00
32 %0 = load i32, i32* @c, align 4
33 %tobool2 = icmp eq i32 %0, 0
34 br i1 %tobool2, label %if.end, label %if.then
35
36 if.then: ; preds = %entry
37 %1 = load i32, i32* @b, align 4
38 %2 = sitofp i32 %1 to float
39 %conv5 = select i1 %call, float 0.000000e+00, float %2
40 store float %conv5, float* @d, align 4
41 br label %if.end
42
43 if.end: ; preds = %entry, %if.then
44 ret float %cond
45 }
46
47 declare zeroext i1 @_Z1av()