llvm.org GIT mirror llvm / 99e6d4e
Add another bit of the ARM target assembler to llvm-mc to parse registers with writeback, things like "sp!", etc. Also added some more stuff to the temporarily hacked methods ARMAsmParser::MatchRegisterName and ARMAsmParser::MatchInstruction to allow more parser testing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83477 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Enderby 11 years ago
1 changed file(s) with 17 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
9999
100100 struct {
101101 unsigned RegNum;
102 bool Writeback;
102103 } Reg;
103104
104105 // This is for all forms of ARM address expressions
145146 return Res;
146147 }
147148
148 static ARMOperand CreateReg(unsigned RegNum) {
149 static ARMOperand CreateReg(unsigned RegNum, bool Writeback) {
149150 ARMOperand Res;
150151 Res.Kind = Register;
151152 Res.Reg.RegNum = RegNum;
153 Res.Reg.Writeback = Writeback;
152154 return Res;
153155 }
154156
192194 RegNum = MatchRegisterName(Tok.getString());
193195 if (RegNum == 0)
194196 return true;
195
196 Op = ARMOperand::CreateReg(RegNum);
197197 getLexer().Lex(); // Eat identifier token.
198
199 bool Writeback = false;
200 const AsmToken &ExclaimTok = getLexer().getTok();
201 if (ExclaimTok.is(AsmToken::Exclaim)) {
202 Writeback = true;
203 getLexer().Lex(); // Eat exclaim token
204 }
205
206 Op = ARMOperand::CreateReg(RegNum, Writeback);
198207
199208 return false;
200209 }
395404 return 2;
396405 else if (Name == "r3")
397406 return 3;
407 else if (Name == "sp")
408 return 13;
398409 return 0;
399410 }
400411
405416 assert(Op0.Kind == ARMOperand::Token && "First operand not a Token");
406417 const StringRef &Mnemonic = Op0.getToken();
407418 if (Mnemonic == "add" ||
419 Mnemonic == "stmfd" ||
420 Mnemonic == "str" ||
421 Mnemonic == "ldmfd" ||
408422 Mnemonic == "ldr")
409423 return false;
410424