llvm.org GIT mirror llvm / 99cb989
Target RegisterInfo: devirtualize TargetFrameLowering Summary: The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can. This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here. Subscribers: sunfish, ted, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11093 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241921 91177308-0d34-0410-b5e6-96231b3b80d8 JF Bastien 5 years ago
9 changed file(s) with 62 addition(s) and 61 deletion(s). Raw diff Collapse all Expand all
8989
9090 BitVector
9191 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
92 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
92 const AArch64FrameLowering *TFI = getFrameLowering(MF);
9393
9494 // FIXME: avoid re-calculating this every time.
9595 BitVector Reserved(getNumRegs());
118118
119119 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
120120 unsigned Reg) const {
121 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
121 const AArch64FrameLowering *TFI = getFrameLowering(MF);
122122
123123 switch (Reg) {
124124 default:
197197 bool
198198 AArch64RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
199199 const MachineFrameInfo *MFI = MF.getFrameInfo();
200 const AArch64FrameLowering *TFI = getFrameLowering(MF);
200201 const Function *F = MF.getFunction();
201 unsigned StackAlign = MF.getTarget()
202 .getSubtargetImpl(*MF.getFunction())
203 ->getFrameLowering()
204 ->getStackAlignment();
202 unsigned StackAlign = TFI->getStackAlignment();
205203 bool requiresRealignment =
206204 ((MFI->getMaxAlignment() > StackAlign) ||
207205 F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
212210
213211 unsigned
214212 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
215 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
216
213 const AArch64FrameLowering *TFI = getFrameLowering(MF);
217214 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;
218215 }
219216
279276 // Note that the incoming offset is based on the SP value at function entry,
280277 // so it'll be negative.
281278 MachineFunction &MF = *MI->getParent()->getParent();
282 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
279 const AArch64FrameLowering *TFI = getFrameLowering(MF);
283280 MachineFrameInfo *MFI = MF.getFrameInfo();
284281
285282 // Estimate an offset from the frame pointer.
375372 MachineFunction &MF = *MBB.getParent();
376373 const AArch64InstrInfo *TII =
377374 MF.getSubtarget().getInstrInfo();
378 const AArch64FrameLowering *TFI = static_cast(
379 MF.getSubtarget().getFrameLowering());
375 const AArch64FrameLowering *TFI = getFrameLowering(MF);
380376
381377 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
382378 unsigned FrameReg;
414410
415411 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
416412 MachineFunction &MF) const {
417 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
413 const AArch64FrameLowering *TFI = getFrameLowering(MF);
418414
419415 switch (RC->getID()) {
420416 default:
126126 BitVector ARMBaseRegisterInfo::
127127 getReservedRegs(const MachineFunction &MF) const {
128128 const ARMSubtarget &STI = MF.getSubtarget();
129 const TargetFrameLowering *TFI = STI.getFrameLowering();
129 const ARMFrameLowering *TFI = getFrameLowering(MF);
130130
131131 // FIXME: avoid re-calculating this every time.
132132 BitVector Reserved(getNumRegs());
193193 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
194194 MachineFunction &MF) const {
195195 const ARMSubtarget &STI = MF.getSubtarget();
196 const TargetFrameLowering *TFI = STI.getFrameLowering();
196 const ARMFrameLowering *TFI = getFrameLowering(MF);
197197
198198 switch (RC->getID()) {
199199 default:
301301 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
302302 const MachineFrameInfo *MFI = MF.getFrameInfo();
303303 const ARMFunctionInfo *AFI = MF.getInfo();
304 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
304 const ARMFrameLowering *TFI = getFrameLowering(MF);
305305
306306 // When outgoing call frames are so large that we adjust the stack pointer
307307 // around the call, we can no longer use the stack pointer to reach the
332332 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
333333 const MachineRegisterInfo *MRI = &MF.getRegInfo();
334334 const ARMFunctionInfo *AFI = MF.getInfo();
335 const ARMFrameLowering *TFI = getFrameLowering(MF);
335336 // We can't realign the stack if:
336337 // 1. Dynamic stack realignment is explicitly disabled,
337338 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
346347 return false;
347348 // We may also need a base pointer if there are dynamic allocas or stack
348349 // pointer adjustments around calls.
349 if (MF.getSubtarget().getFrameLowering()->hasReservedCallFrame(MF))
350 if (TFI->hasReservedCallFrame(MF))
350351 return true;
351352 // A base pointer is required and allowed. Check that it isn't too late to
352353 // reserve it.
356357 bool ARMBaseRegisterInfo::
357358 needsStackRealignment(const MachineFunction &MF) const {
358359 const MachineFrameInfo *MFI = MF.getFrameInfo();
360 const ARMFrameLowering *TFI = getFrameLowering(MF);
359361 const Function *F = MF.getFunction();
360 unsigned StackAlign =
361 MF.getSubtarget().getFrameLowering()->getStackAlignment();
362 unsigned StackAlign = TFI->getStackAlignment();
362363 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
363364 F->hasFnAttribute(Attribute::StackAlignment));
364365
377378 unsigned
378379 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
379380 const ARMSubtarget &STI = MF.getSubtarget();
380 const TargetFrameLowering *TFI = STI.getFrameLowering();
381 const ARMFrameLowering *TFI = getFrameLowering(MF);
381382
382383 if (TFI->hasFP(MF))
383384 return getFramePointerReg(STI);
516517 // Note that the incoming offset is based on the SP value at function entry,
517518 // so it'll be negative.
518519 MachineFunction &MF = *MI->getParent()->getParent();
519 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
520 const ARMFrameLowering *TFI = getFrameLowering(MF);
520521 MachineFrameInfo *MFI = MF.getFrameInfo();
521522 ARMFunctionInfo *AFI = MF.getInfo();
522523
693694 MachineFunction &MF = *MBB.getParent();
694695 const ARMBaseInstrInfo &TII =
695696 *static_cast(MF.getSubtarget().getInstrInfo());
696 const ARMFrameLowering *TFI = static_cast(
697 MF.getSubtarget().getFrameLowering());
697 const ARMFrameLowering *TFI = getFrameLowering(MF);
698698 ARMFunctionInfo *AFI = MF.getInfo();
699699 assert(!AFI->isThumb1OnlyFunction() &&
700700 "This eliminateFrameIndex does not support Thumb1!");
220220
221221 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
222222 &MF) const {
223 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
223 const HexagonFrameLowering *TFI = getFrameLowering(MF);
224224 if (TFI->hasFP(MF))
225225 return Hexagon::R30;
226226 return Hexagon::R29;
239239
240240 bool
241241 HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
242 return MF.getSubtarget().getFrameLowering()->hasFP(MF);
242 const HexagonFrameLowering *TFI = getFrameLowering(MF);
243 return TFI->hasFP(MF);
243244 }
244245
245246
3636
3737 const MCPhysReg*
3838 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
39 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
39 const MSP430FrameLowering *TFI = getFrameLowering(*MF);
4040 const Function* F = MF->getFunction();
4141 static const MCPhysReg CalleeSavedRegs[] = {
4242 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
7272
7373 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
7474 BitVector Reserved(getNumRegs());
75 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
75 const MSP430FrameLowering *TFI = getFrameLowering(MF);
7676
7777 // Mark 4 special registers with subregisters as reserved.
7878 Reserved.set(MSP430::PCB);
108108 MachineInstr &MI = *II;
109109 MachineBasicBlock &MBB = *MI.getParent();
110110 MachineFunction &MF = *MBB.getParent();
111 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
111 const MSP430FrameLowering *TFI = getFrameLowering(MF);
112112 DebugLoc dl = MI.getDebugLoc();
113113 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
114114
155155 }
156156
157157 unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
158 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
159
158 const MSP430FrameLowering *TFI = getFrameLowering(MF);
160159 return TFI->hasFP(MF) ? MSP430::FP : MSP430::SP;
161160 }
164164 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
165165 BitVector Reserved(getNumRegs());
166166 const PPCSubtarget &Subtarget = MF.getSubtarget();
167 const PPCFrameLowering *PPCFI =
168 static_cast(Subtarget.getFrameLowering());
167 const PPCFrameLowering *TFI = getFrameLowering(MF);
169168
170169 // The ZERO register is not really a register, but the representation of r0
171170 // when used in instructions that treat r0 as the constant 0.
208207 Reserved.set(PPC::X1);
209208 Reserved.set(PPC::X13);
210209
211 if (PPCFI->needsFP(MF))
210 if (TFI->needsFP(MF))
212211 Reserved.set(PPC::X31);
213212
214213 if (hasBasePointer(MF))
229228 }
230229 }
231230
232 if (PPCFI->needsFP(MF))
231 if (TFI->needsFP(MF))
233232 Reserved.set(PPC::R31);
234233
235234 if (hasBasePointer(MF)) {
255254
256255 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
257256 MachineFunction &MF) const {
258 const PPCSubtarget &Subtarget = MF.getSubtarget();
259 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
257 const PPCFrameLowering *TFI = getFrameLowering(MF);
260258 const unsigned DefaultSafety = 1;
261259
262260 switch (RC->getID()) {
340338 unsigned FrameSize = MFI->getStackSize();
341339
342340 // Get stack alignments.
343 unsigned TargetAlign = Subtarget.getFrameLowering()->getStackAlignment();
341 const PPCFrameLowering *TFI = getFrameLowering(MF);
342 unsigned TargetAlign = TFI->getStackAlignment();
344343 unsigned MaxAlign = MFI->getMaxAlignment();
345344 assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
346345 "Maximum call-frame size not sufficiently aligned");
863862 }
864863
865864 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
866 const PPCSubtarget &Subtarget = MF.getSubtarget();
867 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
865 const PPCFrameLowering *TFI = getFrameLowering(MF);
868866
869867 if (!TM.isPPC64())
870868 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
907905 }
908906
909907 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
910 const PPCSubtarget &Subtarget = MF.getSubtarget();
908 const PPCFrameLowering *TFI = getFrameLowering(MF);
911909 const MachineFrameInfo *MFI = MF.getFrameInfo();
912910 const Function *F = MF.getFunction();
913 unsigned StackAlign = Subtarget.getFrameLowering()->getStackAlignment();
911 unsigned StackAlign = TFI->getStackAlignment();
914912 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
915913 F->hasFnAttribute(Attribute::StackAlignment));
916914
945943
946944 MachineBasicBlock &MBB = *MI->getParent();
947945 MachineFunction &MF = *MBB.getParent();
948 const PPCSubtarget &Subtarget = MF.getSubtarget();
949 const PPCFrameLowering *PPCFI =
950 static_cast(Subtarget.getFrameLowering());
951 unsigned StackEst =
952 PPCFI->determineFrameLayout(MF, false, true);
946 const PPCFrameLowering *TFI = getFrameLowering(MF);
947 unsigned StackEst = TFI->determineFrameLayout(MF, false, true);
953948
954949 // If we likely don't need a stack frame, then we probably don't need a
955950 // virtual base register either.
10331028 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
10341029 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));
10351030 }
1036
3535 BitVector
3636 SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
3737 BitVector Reserved(getNumRegs());
38 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
38 const SystemZFrameLowering *TFI = getFrameLowering(MF);
3939
4040 if (TFI->hasFP(MF)) {
4141 // R11D is the frame pointer. Reserve all aliases.
6363 MachineFunction &MF = *MBB.getParent();
6464 auto *TII =
6565 static_cast(MF.getSubtarget().getInstrInfo());
66 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
66 const SystemZFrameLowering *TFI = getFrameLowering(MF);
6767 DebugLoc DL = MI->getDebugLoc();
6868
6969 // Decompose the frame index into a base and offset.
134134
135135 unsigned
136136 SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
137 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
137 const SystemZFrameLowering *TFI = getFrameLowering(MF);
138138 return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
139139 }
201201 unsigned
202202 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
203203 MachineFunction &MF) const {
204 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
204 const X86FrameLowering *TFI = getFrameLowering(MF);
205205
206206 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
207207 switch (RC->getID()) {
342342
343343 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
344344 BitVector Reserved(getNumRegs());
345 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
345 const X86FrameLowering *TFI = getFrameLowering(MF);
346346
347347 // Set the stack-pointer register and its aliases as reserved.
348348 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
476476
477477 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
478478 const MachineFrameInfo *MFI = MF.getFrameInfo();
479 const X86FrameLowering *TFI = getFrameLowering(MF);
479480 const Function *F = MF.getFunction();
480 unsigned StackAlign =
481 MF.getSubtarget().getFrameLowering()->getStackAlignment();
481 unsigned StackAlign = TFI->getStackAlignment();
482482 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
483483 F->hasFnAttribute(Attribute::StackAlignment));
484484
502502 RegScavenger *RS) const {
503503 MachineInstr &MI = *II;
504504 MachineFunction &MF = *MI.getParent()->getParent();
505 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
505 const X86FrameLowering *TFI = getFrameLowering(MF);
506506 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
507507 unsigned BasePtr;
508508
528528 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
529529 int Offset;
530530 if (IsWinEH)
531 Offset = static_cast(TFI)
532 ->getFrameIndexOffsetFromSP(MF, FrameIndex);
531 Offset = TFI->getFrameIndexOffsetFromSP(MF, FrameIndex);
533532 else
534533 Offset = TFI->getFrameIndexOffset(MF, FrameIndex);
535534 FI.ChangeToImmediate(Offset);
583582 }
584583
585584 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
586 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
585 const X86FrameLowering *TFI = getFrameLowering(MF);
587586 return TFI->hasFP(MF) ? FramePtr : StackPtr;
588587 }
589588
221221 XCore::R8, XCore::R9,
222222 0
223223 };
224 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
224 const XCoreFrameLowering *TFI = getFrameLowering(*MF);
225225 if (TFI->hasFP(*MF))
226226 return CalleeSavedRegsFP;
227227 return CalleeSavedRegs;
229229
230230 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
231231 BitVector Reserved(getNumRegs());
232 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
232 const XCoreFrameLowering *TFI = getFrameLowering(MF);
233233
234234 Reserved.set(XCore::CP);
235235 Reserved.set(XCore::DP);
269269 const XCoreInstrInfo &TII =
270270 *static_cast(MF.getSubtarget().getInstrInfo());
271271
272 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
272 const XCoreFrameLowering *TFI = getFrameLowering(MF);
273273 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
274274 int StackSize = MF.getFrameInfo()->getStackSize();
275275
323323
324324
325325 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
326 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
326 const XCoreFrameLowering *TFI = getFrameLowering(MF);
327327
328328 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
329329 }
10691069
10701070 OS << "namespace llvm {\n\n";
10711071
1072 OS << "class " << TargetName << "FrameLowering;\n\n";
1073
10721074 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
10731075 << " explicit " << ClassName
10741076 << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
10951097 << "unsigned RegUnit) const override;\n"
10961098 << " ArrayRef getRegMaskNames() const override;\n"
10971099 << " ArrayRef getRegMasks() const override;\n"
1100 << " /// Devirtualized TargetFrameLowering.\n"
1101 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n"
1102 << " const MachineFunction &MF);\n"
10981103 << "};\n\n";
10991104
11001105 const auto &RegisterClasses = RegBank.getRegClasses();
14661471 << ");\n";
14671472 OS << "}\n\n";
14681473
1474 OS << "const " << TargetName << "FrameLowering *"
1475 << TargetName << "GenRegisterInfo::\n"
1476 << " getFrameLowering(const MachineFunction &MF) {\n"
1477 << " return static_cast(\n"
1478 << " MF.getSubtarget().getFrameLowering());\n"
1479 << "}\n\n";
1480
14691481 OS << "} // End llvm namespace\n";
14701482 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
14711483 }