llvm.org GIT mirror llvm / 99cb622
Use pointers to the MCAsmInfo and MCRegInfo. Someone may want to do something crazy, like replace these objects if they change or something. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 7 years ago
30 changed file(s) with 196 addition(s) and 200 deletion(s). Raw diff Collapse all Expand all
5151 const SourceMgr *SrcMgr;
5252
5353 /// The MCAsmInfo for this target.
54 const MCAsmInfo &MAI;
54 const MCAsmInfo *MAI;
5555
5656 /// The MCRegisterInfo for this target.
57 const MCRegisterInfo &MRI;
57 const MCRegisterInfo *MRI;
5858
5959 /// The MCObjectFileInfo for this target.
6060 const MCObjectFileInfo *MOFI;
163163 MCSymbol *CreateSymbol(StringRef Name);
164164
165165 public:
166 explicit MCContext(const MCAsmInfo &MAI, const MCRegisterInfo &MRI,
166 explicit MCContext(const MCAsmInfo *MAI, const MCRegisterInfo *MRI,
167167 const MCObjectFileInfo *MOFI, const SourceMgr *Mgr = 0,
168168 bool DoAutoReset = true);
169169 ~MCContext();
170170
171171 const SourceMgr *getSourceManager() const { return SrcMgr; }
172172
173 const MCAsmInfo &getAsmInfo() const { return MAI; }
174
175 const MCRegisterInfo &getRegisterInfo() const { return MRI; }
173 const MCAsmInfo *getAsmInfo() const { return MAI; }
174
175 const MCRegisterInfo *getRegisterInfo() const { return MRI; }
176176
177177 const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; }
178178
5050 if (!CachedMCSymbol) {
5151 const MachineFunction *MF = getParent();
5252 MCContext &Ctx = MF->getContext();
53 const char *Prefix = Ctx.getAsmInfo().getPrivateGlobalPrefix();
53 const char *Prefix = Ctx.getAsmInfo()->getPrivateGlobalPrefix();
5454 CachedMCSymbol = Ctx.GetOrCreateSymbol(Twine(Prefix) + "BB" +
5555 Twine(MF->getFunctionNumber()) +
5656 "_" + Twine(getNumber()));
252252 MachineModuleInfo::MachineModuleInfo(const MCAsmInfo &MAI,
253253 const MCRegisterInfo &MRI,
254254 const MCObjectFileInfo *MOFI)
255 : ImmutablePass(ID), Context(MAI, MRI, MOFI, 0, false) {
255 : ImmutablePass(ID), Context(&MAI, &MRI, MOFI, 0, false) {
256256 initializeMachineModuleInfoPass(*PassRegistry::getPassRegistry());
257257 }
258258
259259 MachineModuleInfo::MachineModuleInfo()
260 : ImmutablePass(ID),
261 Context(*(MCAsmInfo*)0, *(MCRegisterInfo*)0, (MCObjectFileInfo*)0) {
260 : ImmutablePass(ID), Context(0, 0, 0) {
262261 llvm_unreachable("This MachineModuleInfo constructor should never be called, "
263262 "MMI should always be explicitly constructed by "
264263 "LLVMTargetMachine");
3737 class MCAsmStreamer : public MCStreamer {
3838 protected:
3939 formatted_raw_ostream &OS;
40 const MCAsmInfo &MAI;
40 const MCAsmInfo *MAI;
4141 private:
4242 OwningPtr InstPrinter;
4343 OwningPtr Emitter;
311311 "Comment array not newline terminated");
312312 do {
313313 // Emit a line of comments.
314 OS.PadToColumn(MAI.getCommentColumn());
314 OS.PadToColumn(MAI->getCommentColumn());
315315 size_t Position = Comments.find('\n');
316 OS << MAI.getCommentString() << ' ' << Comments.substr(0, Position) << '\n';
316 OS << MAI->getCommentString() << ' ' << Comments.substr(0, Position) <<'\n';
317317
318318 Comments = Comments.substr(Position+1);
319319 } while (!Comments.empty());
331331 void MCAsmStreamer::ChangeSection(const MCSection *Section,
332332 const MCExpr *Subsection) {
333333 assert(Section && "Cannot switch to a null section!");
334 Section->PrintSwitchToSection(MAI, OS, Subsection);
334 Section->PrintSwitchToSection(*MAI, OS, Subsection);
335335 }
336336
337337 void MCAsmStreamer::EmitEHSymAttributes(const MCSymbol *Symbol,
353353 assert(Symbol->isUndefined() && "Cannot define a symbol twice!");
354354 MCStreamer::EmitLabel(Symbol);
355355
356 OS << *Symbol << MAI.getLabelSuffix();
356 OS << *Symbol << MAI->getLabelSuffix();
357357 EmitEOL();
358358 }
359359
361361 assert(Symbol->isUndefined() && "Cannot define a symbol twice!");
362362 MCStreamer::EmitDebugLabel(Symbol);
363363
364 OS << *Symbol << MAI.getDebugLabelSuffix();
364 OS << *Symbol << MAI->getDebugLabelSuffix();
365365 EmitEOL();
366366 }
367367
369369 switch (Flag) {
370370 case MCAF_SyntaxUnified: OS << "\t.syntax unified"; break;
371371 case MCAF_SubsectionsViaSymbols: OS << ".subsections_via_symbols"; break;
372 case MCAF_Code16: OS << '\t'<< MAI.getCode16Directive(); break;
373 case MCAF_Code32: OS << '\t'<< MAI.getCode32Directive(); break;
374 case MCAF_Code64: OS << '\t'<< MAI.getCode64Directive(); break;
372 case MCAF_Code16: OS << '\t'<< MAI->getCode16Directive();break;
373 case MCAF_Code32: OS << '\t'<< MAI->getCode32Directive();break;
374 case MCAF_Code64: OS << '\t'<< MAI->getCode64Directive();break;
375375 }
376376 EmitEOL();
377377 }
387387 }
388388
389389 void MCAsmStreamer::EmitDataRegion(MCDataRegionType Kind) {
390 MCContext &Ctx = getContext();
391 const MCAsmInfo &MAI = Ctx.getAsmInfo();
392 if (!MAI.doesSupportDataRegionDirectives())
390 if (!MAI->doesSupportDataRegionDirectives())
393391 return;
394392 switch (Kind) {
395393 case MCDR_DataRegion: OS << "\t.data_region"; break;
406404 // MCSymbols when they have spaces in them.
407405 OS << "\t.thumb_func";
408406 // Only Mach-O hasSubsectionsViaSymbols()
409 if (MAI.hasSubsectionsViaSymbols())
407 if (MAI->hasSubsectionsViaSymbols())
410408 OS << '\t' << *Func;
411409 EmitEOL();
412410 }
451449 case MCSA_ELF_TypeCommon: /// .type _foo, STT_COMMON # aka @common
452450 case MCSA_ELF_TypeNoType: /// .type _foo, STT_NOTYPE # aka @notype
453451 case MCSA_ELF_TypeGnuUniqueObject: /// .type _foo, @gnu_unique_object
454 assert(MAI.hasDotTypeDotSizeDirective() && "Symbol Attr not supported");
452 assert(MAI->hasDotTypeDotSizeDirective() && "Symbol Attr not supported");
455453 OS << "\t.type\t" << *Symbol << ','
456 << ((MAI.getCommentString()[0] != '@') ? '@' : '%');
454 << ((MAI->getCommentString()[0] != '@') ? '@' : '%');
457455 switch (Attribute) {
458456 default: llvm_unreachable("Unknown ELF .type");
459457 case MCSA_ELF_TypeFunction: OS << "function"; break;
467465 EmitEOL();
468466 return;
469467 case MCSA_Global: // .globl/.global
470 OS << MAI.getGlobalDirective();
468 OS << MAI->getGlobalDirective();
471469 FlagMap[Symbol] |= EHGlobal;
472470 break;
473471 case MCSA_Hidden: OS << "\t.hidden\t"; break;
489487 FlagMap[Symbol] |= EHWeakDefinition;
490488 break;
491489 // .weak_reference
492 case MCSA_WeakReference: OS << MAI.getWeakRefDirective(); break;
490 case MCSA_WeakReference: OS << MAI->getWeakRefDirective(); break;
493491 case MCSA_WeakDefAutoPrivate: OS << "\t.weak_def_can_be_hidden\t"; break;
494492 }
495493
528526 }
529527
530528 void MCAsmStreamer::EmitELFSize(MCSymbol *Symbol, const MCExpr *Value) {
531 assert(MAI.hasDotTypeDotSizeDirective());
529 assert(MAI->hasDotTypeDotSizeDirective());
532530 OS << "\t.size\t" << *Symbol << ", " << *Value << '\n';
533531 }
534532
536534 unsigned ByteAlignment) {
537535 OS << "\t.comm\t" << *Symbol << ',' << Size;
538536 if (ByteAlignment != 0) {
539 if (MAI.getCOMMDirectiveAlignmentIsInBytes())
537 if (MAI->getCOMMDirectiveAlignmentIsInBytes())
540538 OS << ',' << ByteAlignment;
541539 else
542540 OS << ',' << Log2_32(ByteAlignment);
552550 unsigned ByteAlign) {
553551 OS << "\t.lcomm\t" << *Symbol << ',' << Size;
554552 if (ByteAlign > 1) {
555 switch (MAI.getLCOMMDirectiveAlignmentType()) {
553 switch (MAI->getLCOMMDirectiveAlignmentType()) {
556554 case LCOMM::NoAlignment:
557555 llvm_unreachable("alignment not supported on .lcomm!");
558556 case LCOMM::ByteAlignment:
643641 if (Data.empty()) return;
644642
645643 if (Data.size() == 1) {
646 OS << MAI.getData8bitsDirective(AddrSpace);
644 OS << MAI->getData8bitsDirective(AddrSpace);
647645 OS << (unsigned)(unsigned char)Data[0];
648646 EmitEOL();
649647 return;
651649
652650 // If the data ends with 0 and the target supports .asciz, use it, otherwise
653651 // use .ascii
654 if (MAI.getAscizDirective() && Data.back() == 0) {
655 OS << MAI.getAscizDirective();
652 if (MAI->getAscizDirective() && Data.back() == 0) {
653 OS << MAI->getAscizDirective();
656654 Data = Data.substr(0, Data.size()-1);
657655 } else {
658 OS << MAI.getAsciiDirective();
656 OS << MAI->getAsciiDirective();
659657 }
660658
661659 OS << ' ';
675673 const char *Directive = 0;
676674 switch (Size) {
677675 default: break;
678 case 1: Directive = MAI.getData8bitsDirective(AddrSpace); break;
679 case 2: Directive = MAI.getData16bitsDirective(AddrSpace); break;
680 case 4: Directive = MAI.getData32bitsDirective(AddrSpace); break;
676 case 1: Directive = MAI->getData8bitsDirective(AddrSpace); break;
677 case 2: Directive = MAI->getData16bitsDirective(AddrSpace); break;
678 case 4: Directive = MAI->getData32bitsDirective(AddrSpace); break;
681679 case 8:
682 Directive = MAI.getData64bitsDirective(AddrSpace);
680 Directive = MAI->getData64bitsDirective(AddrSpace);
683681 // If the target doesn't support 64-bit data, emit as two 32-bit halves.
684682 if (Directive) break;
685683 int64_t IntValue;
686684 if (!Value->EvaluateAsAbsolute(IntValue))
687685 report_fatal_error("Don't know how to emit this value.");
688 if (getContext().getAsmInfo().isLittleEndian()) {
686 if (MAI->isLittleEndian()) {
689687 EmitIntValue((uint32_t)(IntValue >> 0 ), 4, AddrSpace);
690688 EmitIntValue((uint32_t)(IntValue >> 32), 4, AddrSpace);
691689 } else {
706704 EmitULEB128IntValue(IntValue);
707705 return;
708706 }
709 assert(MAI.hasLEB128() && "Cannot print a .uleb");
707 assert(MAI->hasLEB128() && "Cannot print a .uleb");
710708 OS << ".uleb128 " << *Value;
711709 EmitEOL();
712710 }
717715 EmitSLEB128IntValue(IntValue);
718716 return;
719717 }
720 assert(MAI.hasLEB128() && "Cannot print a .sleb");
718 assert(MAI->hasLEB128() && "Cannot print a .sleb");
721719 OS << ".sleb128 " << *Value;
722720 EmitEOL();
723721 }
724722
725723 void MCAsmStreamer::EmitGPRel64Value(const MCExpr *Value) {
726 assert(MAI.getGPRel64Directive() != 0);
727 OS << MAI.getGPRel64Directive() << *Value;
724 assert(MAI->getGPRel64Directive() != 0);
725 OS << MAI->getGPRel64Directive() << *Value;
728726 EmitEOL();
729727 }
730728
731729 void MCAsmStreamer::EmitGPRel32Value(const MCExpr *Value) {
732 assert(MAI.getGPRel32Directive() != 0);
733 OS << MAI.getGPRel32Directive() << *Value;
730 assert(MAI->getGPRel32Directive() != 0);
731 OS << MAI->getGPRel32Directive() << *Value;
734732 EmitEOL();
735733 }
736734
742740 if (NumBytes == 0) return;
743741
744742 if (AddrSpace == 0)
745 if (const char *ZeroDirective = MAI.getZeroDirective()) {
743 if (const char *ZeroDirective = MAI->getZeroDirective()) {
746744 OS << ZeroDirective << NumBytes;
747745 if (FillValue != 0)
748746 OS << ',' << (int)FillValue;
762760 if (isPowerOf2_32(ByteAlignment)) {
763761 switch (ValueSize) {
764762 default: llvm_unreachable("Invalid size for machine code value!");
765 case 1: OS << MAI.getAlignDirective(); break;
763 case 1: OS << MAI->getAlignDirective(); break;
766764 // FIXME: use MAI for this!
767765 case 2: OS << ".p2alignw "; break;
768766 case 4: OS << ".p2alignl "; break;
769767 case 8: llvm_unreachable("Unsupported alignment size!");
770768 }
771769
772 if (MAI.getAlignmentIsInBytes())
770 if (MAI->getAlignmentIsInBytes())
773771 OS << ByteAlignment;
774772 else
775773 OS << Log2_32(ByteAlignment);
805803 void MCAsmStreamer::EmitCodeAlignment(unsigned ByteAlignment,
806804 unsigned MaxBytesToEmit) {
807805 // Emit with a text fill value.
808 EmitValueToAlignment(ByteAlignment, MAI.getTextAlignFillValue(),
806 EmitValueToAlignment(ByteAlignment, MAI->getTextAlignFillValue(),
809807 1, MaxBytesToEmit);
810808 }
811809
819817
820818
821819 void MCAsmStreamer::EmitFileDirective(StringRef Filename) {
822 assert(MAI.hasSingleParameterDotFile());
820 assert(MAI->hasSingleParameterDotFile());
823821 OS << "\t.file\t";
824822 PrintQuotedString(Filename, OS);
825823 EmitEOL();
885883 OS << "discriminator " << Discriminator;
886884
887885 if (IsVerboseAsm) {
888 OS.PadToColumn(MAI.getCommentColumn());
889 OS << MAI.getCommentString() << ' ' << FileName << ':'
886 OS.PadToColumn(MAI->getCommentColumn());
887 OS << MAI->getCommentString() << ' ' << FileName << ':'
890888 << Line << ':' << Column;
891889 }
892890 EmitEOL();
935933 }
936934
937935 void MCAsmStreamer::EmitRegisterName(int64_t Register) {
938 if (InstPrinter && !MAI.useDwarfRegNumForCFI()) {
939 const MCRegisterInfo &MRI = getContext().getRegisterInfo();
940 unsigned LLVMRegister = MRI.getLLVMRegNum(Register, true);
936 if (InstPrinter && !MAI->useDwarfRegNumForCFI()) {
937 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
938 unsigned LLVMRegister = MRI->getLLVMRegNum(Register, true);
941939 InstPrinter->printRegName(OS, LLVMRegister);
942940 } else {
943941 OS << Register;
12751273 unsigned Bit = (Code[i] >> j) & 1;
12761274
12771275 unsigned FixupBit;
1278 if (getContext().getAsmInfo().isLittleEndian())
1276 if (MAI->isLittleEndian())
12791277 FixupBit = i * 8 + j;
12801278 else
12811279 FixupBit = i * 8 + (7-j);
13751373
13761374 // Show the MCInst if enabled.
13771375 if (ShowInst) {
1378 Inst.dump_pretty(GetCommentOS(), &MAI, InstPrinter.get(), "\n ");
1376 Inst.dump_pretty(GetCommentOS(), MAI, InstPrinter.get(), "\n ");
13791377 GetCommentOS() << "\n";
13801378 }
13811379
13831381 if (InstPrinter)
13841382 InstPrinter->printInst(&Inst, OS, "");
13851383 else
1386 Inst.print(OS, &MAI);
1384 Inst.print(OS, MAI);
13871385 EmitEOL();
13881386 }
13891387
3131 typedef StringMap COFFUniqueMapTy;
3232
3333
34 MCContext::MCContext(const MCAsmInfo &mai, const MCRegisterInfo &mri,
34 MCContext::MCContext(const MCAsmInfo *mai, const MCRegisterInfo *mri,
3535 const MCObjectFileInfo *mofi, const SourceMgr *mgr,
3636 bool DoAutoReset) :
3737 SrcMgr(mgr), MAI(mai), MRI(mri), MOFI(mofi),
129129 // Determine whether this is an assembler temporary or normal label, if used.
130130 bool isTemporary = false;
131131 if (AllowTemporaryLabels)
132 isTemporary = Name.startswith(MAI.getPrivateGlobalPrefix());
132 isTemporary = Name.startswith(MAI->getPrivateGlobalPrefix());
133133
134134 StringMapEntry *NameEntry = &UsedNames.GetOrCreateValue(Name);
135135 if (NameEntry->getValue()) {
159159 MCSymbol *MCContext::CreateTempSymbol() {
160160 SmallString<128> NameSV;
161161 raw_svector_ostream(NameSV)
162 << MAI.getPrivateGlobalPrefix() << "tmp" << NextUniqueID++;
162 << MAI->getPrivateGlobalPrefix() << "tmp" << NextUniqueID++;
163163 return CreateSymbol(NameSV);
164164 }
165165
178178 }
179179
180180 MCSymbol *MCContext::CreateDirectionalLocalSymbol(int64_t LocalLabelVal) {
181 return GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix()) +
181 return GetOrCreateSymbol(Twine(MAI->getPrivateGlobalPrefix()) +
182182 Twine(LocalLabelVal) +
183183 "\2" +
184184 Twine(NextInstance(LocalLabelVal)));
185185 }
186186 MCSymbol *MCContext::GetDirectionalLocalSymbol(int64_t LocalLabelVal,
187187 int bORf) {
188 return GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix()) +
188 return GetOrCreateSymbol(Twine(MAI->getPrivateGlobalPrefix()) +
189189 Twine(LocalLabelVal) +
190190 "\2" +
191191 Twine(GetInstance(LocalLabelVal) + bORf));
6666 return 0;
6767
6868 // Set up the MCContext for creating symbols and MCExpr's.
69 MCContext *Ctx = new MCContext(*MAI, *MRI, 0);
69 MCContext *Ctx = new MCContext(MAI, MRI, 0);
7070 if (!Ctx)
7171 return 0;
7272
4646 #define DWARF2_LINE_RANGE 14
4747
4848 static inline uint64_t ScaleAddrDelta(MCContext &Context, uint64_t AddrDelta) {
49 unsigned MinInsnLength = Context.getAsmInfo().getMinInstAlignment();
49 unsigned MinInsnLength = Context.getAsmInfo()->getMinInstAlignment();
5050 if (MinInsnLength == 1)
5151 return AddrDelta;
5252 if (AddrDelta % MinInsnLength != 0) {
175175 // At this point we want to emit/create the sequence to encode the delta in
176176 // line numbers and the increment of the address from the previous Label
177177 // and the current Label.
178 const MCAsmInfo &asmInfo = MCOS->getContext().getAsmInfo();
178 const MCAsmInfo *asmInfo = MCOS->getContext().getAsmInfo();
179179 MCOS->EmitDwarfAdvanceLineAddr(LineDelta, LastLabel, Label,
180 asmInfo.getPointerSize());
180 asmInfo->getPointerSize());
181181
182182 LastLine = it->getLine();
183183 LastLabel = Label;
203203 // Switch back the dwarf line section.
204204 MCOS->SwitchSection(context.getObjectFileInfo()->getDwarfLineSection());
205205
206 const MCAsmInfo &asmInfo = MCOS->getContext().getAsmInfo();
206 const MCAsmInfo *asmInfo = MCOS->getContext().getAsmInfo();
207207 MCOS->EmitDwarfAdvanceLineAddr(INT64_MAX, LastLabel, SectionEnd,
208 asmInfo.getPointerSize());
208 asmInfo->getPointerSize());
209209 }
210210
211211 //
270270 (4 + 2 + 4)), 4, 0);
271271
272272 // Parameters of the state machine, are next.
273 MCOS->EmitIntValue(context.getAsmInfo().getMinInstAlignment(), 1);
273 MCOS->EmitIntValue(context.getAsmInfo()->getMinInstAlignment(), 1);
274274 MCOS->EmitIntValue(DWARF2_LINE_DEFAULT_IS_STMT, 1);
275275 MCOS->EmitIntValue(DWARF2_LINE_BASE, 1);
276276 MCOS->EmitIntValue(DWARF2_LINE_RANGE, 1);
331331 EmitDwarfLineTable(MCOS, Sec, Line, CUID);
332332 }
333333
334 if (MCOS->getContext().getAsmInfo().getLinkerRequiresNonEmptyDwarfLines()
334 if (MCOS->getContext().getAsmInfo()->getLinkerRequiresNonEmptyDwarfLines()
335335 && MCLineSectionOrder.begin() == MCLineSectionOrder.end()) {
336336 // The darwin9 linker has a bug (see PR8715). For for 32-bit architectures
337337 // it requires:
519519
520520 // Figure the padding after the header before the table of address and size
521521 // pairs who's values are PointerSize'ed.
522 const MCAsmInfo &asmInfo = context.getAsmInfo();
523 int AddrSize = asmInfo.getPointerSize();
522 const MCAsmInfo *asmInfo = context.getAsmInfo();
523 int AddrSize = asmInfo->getPointerSize();
524524 int Pad = 2 * AddrSize - (Length & (2 * AddrSize - 1));
525525 if (Pad == 2 * AddrSize)
526526 Pad = 0;
600600 MCOS->EmitIntValue(0, 4);
601601 }
602602
603 const MCAsmInfo &asmInfo = context.getAsmInfo();
604 int AddrSize = asmInfo.getPointerSize();
603 const MCAsmInfo *asmInfo = context.getAsmInfo();
604 int AddrSize = asmInfo->getPointerSize();
605605 // The 1 byte size of an address.
606606 MCOS->EmitIntValue(AddrSize, 1);
607607
728728 void MCGenDwarfInfo::Emit(MCStreamer *MCOS, const MCSymbol *LineSectionSymbol) {
729729 // Create the dwarf sections in this order (.debug_line already created).
730730 MCContext &context = MCOS->getContext();
731 const MCAsmInfo &AsmInfo = context.getAsmInfo();
731 const MCAsmInfo *AsmInfo = context.getAsmInfo();
732732 bool CreateDwarfSectionSymbols =
733 AsmInfo.doesDwarfUseRelocationsAcrossSections();
733 AsmInfo->doesDwarfUseRelocationsAcrossSections();
734734 if (!CreateDwarfSectionSymbols)
735735 LineSectionSymbol = NULL;
736736 MCSymbol *AbbrevSectionSymbol = NULL;
806806
807807 static int getDataAlignmentFactor(MCStreamer &streamer) {
808808 MCContext &context = streamer.getContext();
809 const MCAsmInfo &asmInfo = context.getAsmInfo();
810 int size = asmInfo.getCalleeSaveStackSlotSize();
811 if (asmInfo.isStackGrowthDirectionUp())
809 const MCAsmInfo *asmInfo = context.getAsmInfo();
810 int size = asmInfo->getCalleeSaveStackSlotSize();
811 if (asmInfo->isStackGrowthDirectionUp())
812812 return size;
813813 else
814814 return -size;
822822 default: llvm_unreachable("Unknown Encoding");
823823 case dwarf::DW_EH_PE_absptr:
824824 case dwarf::DW_EH_PE_signed:
825 return context.getAsmInfo().getPointerSize();
825 return context.getAsmInfo()->getPointerSize();
826826 case dwarf::DW_EH_PE_udata2:
827827 case dwarf::DW_EH_PE_sdata2:
828828 return 2;
838838 static void EmitSymbol(MCStreamer &streamer, const MCSymbol &symbol,
839839 unsigned symbolEncoding, const char *comment = 0) {
840840 MCContext &context = streamer.getContext();
841 const MCAsmInfo &asmInfo = context.getAsmInfo();
842 const MCExpr *v = asmInfo.getExprForFDESymbol(&symbol,
843 symbolEncoding,
844 streamer);
841 const MCAsmInfo *asmInfo = context.getAsmInfo();
842 const MCExpr *v = asmInfo->getExprForFDESymbol(&symbol,
843 symbolEncoding,
844 streamer);
845845 unsigned size = getSizeForEncoding(streamer, symbolEncoding);
846846 if (streamer.isVerboseAsm() && comment) streamer.AddComment(comment);
847847 streamer.EmitAbsValue(v, size);
850850 static void EmitPersonality(MCStreamer &streamer, const MCSymbol &symbol,
851851 unsigned symbolEncoding) {
852852 MCContext &context = streamer.getContext();
853 const MCAsmInfo &asmInfo = context.getAsmInfo();
854 const MCExpr *v = asmInfo.getExprForPersonalitySymbol(&symbol,
855 symbolEncoding,
856 streamer);
853 const MCAsmInfo *asmInfo = context.getAsmInfo();
854 const MCExpr *v = asmInfo->getExprForPersonalitySymbol(&symbol,
855 symbolEncoding,
856 streamer);
857857 unsigned size = getSizeForEncoding(streamer, symbolEncoding);
858858 streamer.EmitValue(v, size);
859859 }
11931193 bool IsSignalFrame,
11941194 unsigned lsdaEncoding) {
11951195 MCContext &context = streamer.getContext();
1196 const MCRegisterInfo &MRI = context.getRegisterInfo();
1196 const MCRegisterInfo *MRI = context.getRegisterInfo();
11971197 const MCObjectFileInfo *MOFI = context.getObjectFileInfo();
11981198 bool verboseAsm = streamer.isVerboseAsm();
11991199
12411241
12421242 // Code Alignment Factor
12431243 if (verboseAsm) streamer.AddComment("CIE Code Alignment Factor");
1244 streamer.EmitULEB128IntValue(context.getAsmInfo().getMinInstAlignment());
1244 streamer.EmitULEB128IntValue(context.getAsmInfo()->getMinInstAlignment());
12451245
12461246 // Data Alignment Factor
12471247 if (verboseAsm) streamer.AddComment("CIE Data Alignment Factor");
12491249
12501250 // Return Address Register
12511251 if (verboseAsm) streamer.AddComment("CIE Return Address Column");
1252 streamer.EmitULEB128IntValue(MRI.getDwarfRegNum(MRI.getRARegister(), true));
1252 streamer.EmitULEB128IntValue(MRI->getDwarfRegNum(MRI->getRARegister(), true));
12531253
12541254 // Augmentation Data Length (optional)
12551255
12891289
12901290 // Initial Instructions
12911291
1292 const MCAsmInfo &MAI = context.getAsmInfo();
1292 const MCAsmInfo *MAI = context.getAsmInfo();
12931293 const std::vector &Instructions =
1294 MAI.getInitialFrameState();
1294 MAI->getInitialFrameState();
12951295 EmitCFIInstructions(streamer, Instructions, NULL);
12961296
12971297 // Padding
1298 streamer.EmitValueToAlignment(IsEH
1299 ? 4 : context.getAsmInfo().getPointerSize());
1298 streamer.EmitValueToAlignment(IsEH ? 4 : MAI->getPointerSize());
13001299
13011300 streamer.EmitLabel(sectionEnd);
13021301 return *sectionStart;
13261325 streamer.EmitLabel(fdeStart);
13271326
13281327 // CIE Pointer
1329 const MCAsmInfo &asmInfo = context.getAsmInfo();
1328 const MCAsmInfo *asmInfo = context.getAsmInfo();
13301329 if (IsEH) {
13311330 const MCExpr *offset = MakeStartMinusEndExpr(streamer, cieStart, *fdeStart,
13321331 0);
13331332 if (verboseAsm) streamer.AddComment("FDE CIE Offset");
13341333 streamer.EmitAbsValue(offset, 4);
1335 } else if (!asmInfo.doesDwarfUseRelocationsAcrossSections()) {
1334 } else if (!asmInfo->doesDwarfUseRelocationsAcrossSections()) {
13361335 const MCExpr *offset = MakeStartMinusEndExpr(streamer, *SectionStart,
13371336 cieStart, 0);
13381337 streamer.EmitAbsValue(offset, 4);
14351434 if (Frame.CompactUnwindEncoding == 0) continue;
14361435 if (!SectionEmitted) {
14371436 Streamer.SwitchSection(MOFI->getCompactUnwindSection());
1438 Streamer.EmitValueToAlignment(Context.getAsmInfo().getPointerSize());
1437 Streamer.EmitValueToAlignment(Context.getAsmInfo()->getPointerSize());
14391438 SectionEmitted = true;
14401439 }
14411440 Emitter.EmitCompactUnwind(Streamer, Frame);
14711470 Streamer.EmitLabel(FDEEnd);
14721471 }
14731472
1474 Streamer.EmitValueToAlignment(Context.getAsmInfo().getPointerSize());
1473 Streamer.EmitValueToAlignment(Context.getAsmInfo()->getPointerSize());
14751474 if (FDEEnd)
14761475 Streamer.EmitLabel(FDEEnd);
14771476 }
13101310 case DK_DOUBLE:
13111311 return ParseDirectiveRealValue(APFloat::IEEEdouble);
13121312 case DK_ALIGN: {
1313 bool IsPow2 = !getContext().getAsmInfo().getAlignmentIsInBytes();
1313 bool IsPow2 = !getContext().getAsmInfo()->getAlignmentIsInBytes();
13141314 return ParseDirectiveAlign(IsPow2, /*ExprSize=*/1);
13151315 }
13161316 case DK_ALIGN32: {
1317 bool IsPow2 = !getContext().getAsmInfo().getAlignmentIsInBytes();
1317 bool IsPow2 = !getContext().getAsmInfo()->getAlignmentIsInBytes();
13181318 return ParseDirectiveAlign(IsPow2, /*ExprSize=*/4);
13191319 }
13201320 case DK_BALIGN:
27292729 if (getLexer().isNot(AsmToken::Integer)) {
27302730 if (getTargetParser().ParseRegister(RegNo, DirectiveLoc, DirectiveLoc))
27312731 return true;
2732 Register = getContext().getRegisterInfo().getDwarfRegNum(RegNo, true);
2732 Register = getContext().getRegisterInfo()->getDwarfRegNum(RegNo, true);
27332733 } else
27342734 return parseAbsoluteExpression(Register);
27352735
452452 bool COFFAsmParser::ParseSEHRegisterNumber(unsigned &RegNo) {
453453 SMLoc startLoc = getLexer().getLoc();
454454 if (getLexer().is(AsmToken::Percent)) {
455 const MCRegisterInfo &MRI = getContext().getRegisterInfo();
455 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
456456 SMLoc endLoc;
457457 unsigned LLVMRegNo;
458458 if (getParser().getTargetParser().ParseRegister(LLVMRegNo,startLoc,endLoc))
472472 return Error(startLoc, "expected non-volatile register");
473473 #endif
474474
475 int SEHRegNo = MRI.getSEHRegNum(LLVMRegNo);
475 int SEHRegNo = MRI->getSEHRegNum(LLVMRegNo);
476476 if (SEHRegNo < 0)
477477 return Error(startLoc,"register can't be represented in SEH unwind info");
478478 RegNo = SEHRegNo;
5757 }
5858
5959 const MCExpr *MCStreamer::ForceExpAbs(const MCExpr* Expr) {
60 if (Context.getAsmInfo().hasAggressiveSymbolFolding() ||
60 if (Context.getAsmInfo()->hasAggressiveSymbolFolding() ||
6161 isa(Expr))
6262 return Expr;
6363
9191 assert((isUIntN(8 * Size, Value) || isIntN(8 * Size, Value)) &&
9292 "Invalid size");
9393 char buf[8];
94 const bool isLittleEndian = Context.getAsmInfo().isLittleEndian();
94 const bool isLittleEndian = Context.getAsmInfo()->isLittleEndian();
9595 for (unsigned i = 0; i != Size; ++i) {
9696 unsigned index = isLittleEndian ? i : (Size - i - 1);
9797 buf[i] = uint8_t(Value >> (index * 8));
228228 Frame.Function = LastSymbol;
229229 // If the function is externally visible, we need to create a local
230230 // symbol to avoid relocations.
231 StringRef Prefix = getContext().getAsmInfo().getPrivateGlobalPrefix();
231 StringRef Prefix = getContext().getAsmInfo()->getPrivateGlobalPrefix();
232232 if (LastSymbol && LastSymbol->getName().startswith(Prefix)) {
233233 Frame.Begin = LastSymbol;
234234 } else {
5353 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
5454
5555 MachineModuleInfo &MMI = MF.getMMI();
56 const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
56 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
5757 bool NeedsFrameMoves = MMI.hasDebugInfo()
5858 || MF.getFunction()->needsUnwindTableEntry();
5959
9696 .addSym(SPLabel);
9797
9898 MachineLocation Dst(MachineLocation::VirtualFP);
99 unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
99 unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
100100 MMI.addFrameInst(
101101 MCCFIInstruction::createDefCfa(SPLabel, Reg, -NumInitialBytes));
102102 }
131131 MCSymbol *FPLabel = MMI.getContext().CreateTempSymbol();
132132 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
133133 .addSym(FPLabel);
134 unsigned Reg = MRI.getDwarfRegNum(AArch64::X29, true);
134 unsigned Reg = MRI->getDwarfRegNum(AArch64::X29, true);
135135 unsigned Offset = MFI->getObjectOffset(X29FrameIdx);
136136 MMI.addFrameInst(MCCFIInstruction::createDefCfa(FPLabel, Reg, Offset));
137137 }
164164 .addSym(CSLabel);
165165
166166 MachineLocation Dst(MachineLocation::VirtualFP);
167 unsigned Reg = MRI.getDwarfRegNum(AArch64::XSP, true);
167 unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
168168 unsigned Offset = NumResidualBytes + NumInitialBytes;
169169 MMI.addFrameInst(MCCFIInstruction::createDefCfa(CSLabel, Reg, -Offset));
170170 }
182182 for (std::vector::const_iterator I = CSI.begin(),
183183 E = CSI.end(); I != E; ++I) {
184184 unsigned Offset = MFI->getObjectOffset(I->getFrameIdx());
185 unsigned Reg = MRI.getDwarfRegNum(I->getReg(), true);
185 unsigned Reg = MRI->getDwarfRegNum(I->getReg(), true);
186186 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, Reg, Offset));
187187 }
188188 }
345345 const MCOperand &MO,
346346 SmallVectorImpl &Fixups) const {
347347 if (MO.isReg()) {
348 return Ctx.getRegisterInfo().getEncodingValue(MO.getReg());
348 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
349349 } else if (MO.isImm()) {
350350 return static_cast(MO.getImm());
351351 }
276276 MCAsmParserExtension::Initialize(_Parser);
277277
278278 // Cache the MCRegisterInfo.
279 MRI = &getContext().getRegisterInfo();
279 MRI = getContext().getRegisterInfo();
280280
281281 // Initialize the set of available features.
282282 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
78507850 /// parseDirectiveThumbFunc
78517851 /// ::= .thumbfunc symbol_name
78527852 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7853 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7854 bool isMachO = MAI.hasSubsectionsViaSymbols();
7853 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7854 bool isMachO = MAI->hasSubsectionsViaSymbols();
78557855 StringRef Name;
78567856 bool needFuncName = true;
78577857
379379 void ARMELFStreamer::FlushUnwindOpcodes(bool AllowCompactModel0) {
380380 // Emit the unwind opcode to restore $sp.
381381 if (UsedFP) {
382 const MCRegisterInfo &MRI = getContext().getRegisterInfo();
382 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
383383 int64_t LastRegSaveSPOffset = SPOffset - PendingOffset;
384384 UnwindOpAsm.EmitSPOffset(LastRegSaveSPOffset - FPOffset);
385 UnwindOpAsm.EmitSetSP(MRI.getEncodingValue(FPReg));
385 UnwindOpAsm.EmitSetSP(MRI->getEncodingValue(FPReg));
386386 } else {
387387 FlushPendingOffset();
388388 }
457457 // Collect the registers in the register list
458458 unsigned Count = 0;
459459 uint32_t Mask = 0;
460 const MCRegisterInfo &MRI = getContext().getRegisterInfo();
460 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
461461 for (size_t i = 0; i < RegList.size(); ++i) {
462 unsigned Reg = MRI.getEncodingValue(RegList[i]);
462 unsigned Reg = MRI->getEncodingValue(RegList[i]);
463463 assert(Reg < (IsVector ? 32U : 16U) && "Register out of range");
464464 unsigned Bit = (1u << Reg);
465465 if ((Mask & Bit) == 0) {
406406 SmallVectorImpl &Fixups) const {
407407 if (MO.isReg()) {
408408 unsigned Reg = MO.getReg();
409 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
409 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
410410
411411 // Q registers are encoded as 2x their register number.
412412 switch (Reg) {
435435 const MCOperand &MO = MI.getOperand(OpIdx);
436436 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
437437
438 Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
438 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
439439
440440 int32_t SImm = MO1.getImm();
441441 bool isAdd = true;
723723 // {2-0} = Rn
724724 const MCOperand &MO1 = MI.getOperand(OpIdx);
725725 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
726 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
727 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
726 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
727 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
728728 return (Rm << 3) | Rn;
729729 }
730730
740740 // If The first operand isn't a register, we have a label reference.
741741 const MCOperand &MO = MI.getOperand(OpIdx);
742742 if (!MO.isReg()) {
743 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
743 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
744744 Imm12 = 0;
745745 isAdd = false ; // 'U' bit is set as part of the fixup.
746746
820820 // If The first operand isn't a register, we have a label reference.
821821 const MCOperand &MO = MI.getOperand(OpIdx);
822822 if (!MO.isReg()) {
823 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
823 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
824824 Imm8 = 0;
825825 isAdd = false ; // 'U' bit is set as part of the fixup.
826826
856856 // {7-0} = imm8
857857 const MCOperand &MO = MI.getOperand(OpIdx);
858858 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
859 unsigned Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
859 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
860860 unsigned Imm8 = MO1.getImm();
861861 return (Reg << 8) | Imm8;
862862 }
939939 const MCOperand &MO = MI.getOperand(OpIdx);
940940 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
941941 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
942 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
943 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
942 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
943 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
944944 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
945945 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
946946 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
974974 // {12} isAdd
975975 // {11-0} imm12/Rm
976976 const MCOperand &MO = MI.getOperand(OpIdx);
977 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
977 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
978978 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
979979 Binary |= Rn << 14;
980980 return Binary;
997997 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
998998 Binary <<= 7; // Shift amount is bits [11:7]
999999 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1000 Binary |= CTX.getRegisterInfo().getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1000 Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
10011001 }
10021002 return Binary | (isAdd << 12) | (isReg << 13);
10031003 }
10101010 const MCOperand &MO = MI.getOperand(OpIdx);
10111011 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
10121012 bool isAdd = MO1.getImm() != 0;
1013 return CTX.getRegisterInfo().getEncodingValue(MO.getReg()) | (isAdd << 4);
1013 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
10141014 }
10151015
10161016 uint32_t ARMMCCodeEmitter::
10281028 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
10291029 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
10301030 if (!isImm)
1031 Imm8 = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1031 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
10321032 return Imm8 | (isAdd << 8) | (isImm << 9);
10331033 }
10341034
10461046
10471047 // If The first operand isn't a register, we have a label reference.
10481048 if (!MO.isReg()) {
1049 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
1049 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
10501050
10511051 assert(MO.isExpr() && "Unexpected machine operand type!");
10521052 const MCExpr *Expr = MO.getExpr();
10561056 ++MCNumCPRelocations;
10571057 return (Rn << 9) | (1 << 13);
10581058 }
1059 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1059 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
10601060 unsigned Imm = MO2.getImm();
10611061 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
10621062 bool isImm = MO1.getReg() == 0;
10631063 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
10641064 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
10651065 if (!isImm)
1066 Imm8 = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
1066 Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
10671067 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
10681068 }
10691069
10911091 // {2-0} = Rn
10921092 const MCOperand &MO = MI.getOperand(OpIdx);
10931093 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1094 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1094 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
10951095 unsigned Imm5 = MO1.getImm();
10961096 return ((Imm5 & 0x1f) << 3) | Rn;
10971097 }
11181118 // If The first operand isn't a register, we have a label reference.
11191119 const MCOperand &MO = MI.getOperand(OpIdx);
11201120 if (!MO.isReg()) {
1121 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
1121 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
11221122 Imm8 = 0;
11231123 isAdd = false; // 'U' bit is handled as part of the fixup.
11241124
11641164 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
11651165
11661166 // Encode Rm.
1167 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1167 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
11681168
11691169 // Encode the shift opcode.
11701170 unsigned SBits = 0;
11891189 // Encode the shift operation Rs.
11901190 // Encode Rs bit[11:8].
11911191 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1192 return Binary | (CTX.getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift);
1192 return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
11931193 }
11941194
11951195 unsigned ARMMCCodeEmitter::
12081208 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
12091209
12101210 // Encode Rm.
1211 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1211 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
12121212
12131213 // Encode the shift opcode.
12141214 unsigned SBits = 0;
12471247
12481248 // Encoded as [Rn, Rm, imm].
12491249 // FIXME: Needs fixup support.
1250 unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
1250 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
12511251 Value <<= 4;
1252 Value |= CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
1252 Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
12531253 Value <<= 2;
12541254 Value |= MO3.getImm();
12551255
12631263 const MCOperand &MO2 = MI.getOperand(OpNum+1);
12641264
12651265 // FIXME: Needs fixup support.
1266 unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
1266 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
12671267
12681268 // Even though the immediate is 8 bits long, we need 9 bits in order
12691269 // to represent the (inverse of the) sign bit.
13251325 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
13261326
13271327 // Encode Rm.
1328 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1328 unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
13291329
13301330 // Encode the shift opcode.
13311331 unsigned SBits = 0;
13811381
13821382 if (SPRRegs || DPRRegs) {
13831383 // VLDM/VSTM
1384 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
1384 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
13851385 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
13861386 Binary |= (RegNo & 0x1f) << 8;
13871387 if (SPRRegs)
13901390 Binary |= NumRegs * 2;
13911391 } else {
13921392 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1393 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(MI.getOperand(I).getReg());
1393 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
13941394 Binary |= 1 << RegNo;
13951395 }
13961396 }
14061406 const MCOperand &Reg = MI.getOperand(Op);
14071407 const MCOperand &Imm = MI.getOperand(Op + 1);
14081408
1409 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
1409 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
14101410 unsigned Align = 0;
14111411
14121412 switch (Imm.getImm()) {
14291429 const MCOperand &Reg = MI.getOperand(Op);
14301430 const MCOperand &Imm = MI.getOperand(Op + 1);
14311431
1432 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
1432 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
14331433 unsigned Align = 0;
14341434
14351435 switch (Imm.getImm()) {
14551455 const MCOperand &Reg = MI.getOperand(Op);
14561456 const MCOperand &Imm = MI.getOperand(Op + 1);
14571457
1458 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
1458 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
14591459 unsigned Align = 0;
14601460
14611461 switch (Imm.getImm()) {
14741474 SmallVectorImpl &Fixups) const {
14751475 const MCOperand &MO = MI.getOperand(Op);
14761476 if (MO.getReg() == 0) return 0x0D;
1477 return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
1477 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
14781478 }
14791479
14801480 unsigned ARMMCCodeEmitter::
4646
4747 /// NameNeedsEscaping - Return true if the identifier \p Str needs quotes
4848 /// for this assembler.
49 static bool NameNeedsEscaping(StringRef Str, const MCAsmInfo &MAI) {
49 static bool NameNeedsEscaping(StringRef Str, const MCAsmInfo *MAI) {
5050 assert(!Str.empty() && "Cannot create an empty MCSymbol");
5151
5252 // If the first character is a number and the target does not allow this, we
5353 // need quotes.
54 if (!MAI.doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9')
54 if (!MAI->doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9')
5555 return true;
5656
5757 // If any of the characters in the string is an unacceptable character, force
5858 // quotes.
59 bool AllowPeriod = MAI.doesAllowPeriodsInName();
60 bool AllowUTF8 = MAI.doesAllowUTF8();
59 bool AllowPeriod = MAI->doesAllowPeriodsInName();
60 bool AllowUTF8 = MAI->doesAllowUTF8();
6161 for (unsigned i = 0, e = Str.size(); i != e; ++i)
6262 if (!isAcceptableChar(Str[i], AllowPeriod, AllowUTF8))
6363 return true;
6767 /// appendMangledName - Add the specified string in mangled form if it uses
6868 /// any unusual characters.
6969 static void appendMangledName(SmallVectorImpl &OutName, StringRef Str,
70 const MCAsmInfo &MAI) {
70 const MCAsmInfo *MAI) {
7171 // The first character is not allowed to be a number unless the target
7272 // explicitly allows it.
73 if (!MAI.doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9') {
73 if (!MAI->doesAllowNameToStartWithDigit() && Str[0] >= '0' && Str[0] <= '9') {
7474 MangleLetter(OutName, Str[0]);
7575 Str = Str.substr(1);
7676 }
7777
78 bool AllowPeriod = MAI.doesAllowPeriodsInName();
79 bool AllowUTF8 = MAI.doesAllowUTF8();
78 bool AllowPeriod = MAI->doesAllowPeriodsInName();
79 bool AllowUTF8 = MAI->doesAllowUTF8();
8080 for (unsigned i = 0, e = Str.size(); i != e; ++i) {
8181 if (!isAcceptableChar(Str[i], AllowPeriod, AllowUTF8))
8282 MangleLetter(OutName, Str[i]);
109109 StringRef Name = GVName.toStringRef(TmpData);
110110 assert(!Name.empty() && "getNameWithPrefix requires non-empty name");
111111
112 const MCAsmInfo &MAI = Context.getAsmInfo();
112 const MCAsmInfo *MAI = Context.getAsmInfo();
113113
114114 // If the global name is not led with \1, add the appropriate prefixes.
115115 if (Name[0] == '\1') {
116116 Name = Name.substr(1);
117117 } else {
118118 if (PrefixTy == Mangler::Private) {
119 const char *Prefix = MAI.getPrivateGlobalPrefix();
119 const char *Prefix = MAI->getPrivateGlobalPrefix();
120120 OutName.append(Prefix, Prefix+strlen(Prefix));
121121 } else if (PrefixTy == Mangler::LinkerPrivate) {
122 const char *Prefix = MAI.getLinkerPrivateGlobalPrefix();
122 const char *Prefix = MAI->getLinkerPrivateGlobalPrefix();
123123 OutName.append(Prefix, Prefix+strlen(Prefix));
124124 }
125125
126 const char *Prefix = MAI.getGlobalPrefix();
126 const char *Prefix = MAI->getGlobalPrefix();
127127 if (Prefix[0] == 0)
128128 ; // Common noop, no prefix.
129129 else if (Prefix[1] == 0)
136136 if (!NameNeedsEscaping(Name, MAI) ||
137137 // If quotes are supported, they can be used unless the string contains
138138 // a quote or newline.
139 (MAI.doesAllowQuotesInName() &&
139 (MAI->doesAllowQuotesInName() &&
140140 Name.find_first_of("\n\"") == StringRef::npos)) {
141141 OutName.append(Name.begin(), Name.end());
142142 return;
144144
145145 // On systems that do not allow quoted names, we need to mangle most
146146 // strange characters.
147 if (!MAI.doesAllowQuotesInName())
147 if (!MAI->doesAllowQuotesInName())
148148 return appendMangledName(OutName, Name, MAI);
149149
150150 // Okay, the system allows quoted strings. We can quote most anything, the
206206
207207 // If we are supposed to add a microsoft-style suffix for stdcall/fastcall,
208208 // add it.
209 if (Context.getAsmInfo().hasMicrosoftFastStdCallMangling()) {
209 if (Context.getAsmInfo()->hasMicrosoftFastStdCallMangling()) {
210210 if (const Function *F = dyn_cast(GV)) {
211211 CallingConv::ID CC = F->getCallingConv();
212212
879879 }
880880
881881 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
882 return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo);
882 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
883883 }
884884
885885 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
379379 SmallVectorImpl &Fixups) const {
380380 if (MO.isReg()) {
381381 unsigned Reg = MO.getReg();
382 unsigned RegNo = Ctx.getRegisterInfo().getEncodingValue(Reg);
382 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
383383 return RegNo;
384384 } else if (MO.isImm()) {
385385 return static_cast(MO.getImm());
3939 if (StackSize == 0 && !MFI->adjustsStack()) return;
4040
4141 MachineModuleInfo &MMI = MF.getMMI();
42 const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
42 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
4343 MachineLocation DstML, SrcML;
4444
4545 // Adjust stack.
5555 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
5656 BuildMI(MBB, MBBI, dl,
5757 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
58 unsigned S1 = MRI.getDwarfRegNum(Mips::S1, true);
58 unsigned S1 = MRI->getDwarfRegNum(Mips::S1, true);
5959 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, S1, -8));
6060
61 unsigned S0 = MRI.getDwarfRegNum(Mips::S0, true);
61 unsigned S0 = MRI->getDwarfRegNum(Mips::S0, true);
6262 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, S0, -12));
6363
64 unsigned RA = MRI.getDwarfRegNum(Mips::RA, true);
64 unsigned RA = MRI->getDwarfRegNum(Mips::RA, true);
6565 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, RA, -4));
6666
6767 if (hasFP(MF))
284284 if (StackSize == 0 && !MFI->adjustsStack()) return;
285285
286286 MachineModuleInfo &MMI = MF.getMMI();
287 const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
287 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
288288 MachineLocation DstML, SrcML;
289289
290290 // Adjust stack.
320320 // one for each of the paired single precision registers.
321321 if (Mips::AFGR64RegClass.contains(Reg)) {
322322 unsigned Reg0 =
323 MRI.getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
323 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
324324 unsigned Reg1 =
325 MRI.getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true);
325 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true);
326326
327327 if (!STI.isLittle())
328328 std::swap(Reg0, Reg1);
334334 } else {
335335 // Reg is either in CPURegs or FGR32.
336336 MMI.addFrameInst(MCCFIInstruction::createOffset(
337 CSLabel, MRI.getDwarfRegNum(Reg, 1), Offset));
337 CSLabel, MRI->getDwarfRegNum(Reg, 1), Offset));
338338 }
339339 }
340340 }
357357 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2);
358358 for (int I = 0; I < 4; ++I) {
359359 int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
360 unsigned Reg = MRI.getDwarfRegNum(ehDataReg(I), true);
360 unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
361361 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel2, Reg, Offset));
362362 }
363363 }
372372 BuildMI(MBB, MBBI, dl,
373373 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
374374 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
375 SetFPLabel, MRI.getDwarfRegNum(FP, true)));
375 SetFPLabel, MRI->getDwarfRegNum(FP, true)));
376376 }
377377 }
378378
190190 // Return the thread-pointer register's encoding.
191191 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
192192 (MCFixupKind)PPC::fixup_ppc_tlsreg));
193 return CTX.getRegisterInfo().getEncodingValue(PPC::X13);
193 return CTX.getRegisterInfo()->getEncodingValue(PPC::X13);
194194 }
195195
196196 unsigned PPCMCCodeEmitter::
201201 MI.getOpcode() == PPC::MFOCRF ||
202202 MI.getOpcode() == PPC::MTCRF8) &&
203203 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
204 return 0x80 >> CTX.getRegisterInfo().getEncodingValue(MO.getReg());
204 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
205205 }
206206
207207
213213 // The GPR operand should come through here though.
214214 assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
215215 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
216 return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
216 return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
217217 }
218218
219219 assert(MO.isImm() &&
333333 *static_cast(MF.getTarget().getInstrInfo());
334334
335335 MachineModuleInfo &MMI = MF.getMMI();
336 const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
336 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
337337 DebugLoc dl;
338338 bool needsFrameMoves = MMI.hasDebugInfo() ||
339339 MF.getFunction()->needsUnwindTableEntry();
529529
530530 if (HasFP) {
531531 unsigned Reg = isPPC64 ? PPC::X31 : PPC::R31;
532 Reg = MRI.getDwarfRegNum(Reg, true);
532 Reg = MRI->getDwarfRegNum(Reg, true);
533533 MMI.addFrameInst(
534534 MCCFIInstruction::createOffset(FrameLabel, Reg, FPOffset));
535535 }
536536
537537 if (MustSaveLR) {
538538 unsigned Reg = isPPC64 ? PPC::LR8 : PPC::LR;
539 Reg = MRI.getDwarfRegNum(Reg, true);
539 Reg = MRI->getDwarfRegNum(Reg, true);
540540 MMI.addFrameInst(
541541 MCCFIInstruction::createOffset(FrameLabel, Reg, LROffset));
542542 }
564564
565565 unsigned Reg = HasFP ? (isPPC64 ? PPC::X31 : PPC::R31)
566566 : (isPPC64 ? PPC::X1 : PPC::R1);
567 Reg = MRI.getDwarfRegNum(Reg, true);
567 Reg = MRI->getDwarfRegNum(Reg, true);
568568 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(ReadyLabel, Reg));
569569 }
570570 }
596596 && Subtarget.isPPC64()
597597 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
598598 MMI.addFrameInst(MCCFIInstruction::createOffset(
599 Label, MRI.getDwarfRegNum(PPC::CR2, true), 8));
599 Label, MRI->getDwarfRegNum(PPC::CR2, true), 8));
600600 continue;
601601 }
602602
603603 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
604604 MMI.addFrameInst(MCCFIInstruction::createOffset(
605 Label, MRI.getDwarfRegNum(Reg, true), Offset));
605 Label, MRI->getDwarfRegNum(Reg, true), Offset));
606606 }
607607 }
608608 }
111111 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
112112 SmallVectorImpl &Fixups) const {
113113 if (MO.isReg())
114 return Ctx.getRegisterInfo().getEncodingValue(MO.getReg());
114 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
115115 if (MO.isImm())
116116 return static_cast(MO.getImm());
117117 llvm_unreachable("Unexpected operand type!");
296296 SystemZMachineFunctionInfo *ZFI = MF.getInfo();
297297 MachineBasicBlock::iterator MBBI = MBB.begin();
298298 MachineModuleInfo &MMI = MF.getMMI();
299 const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
299 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
300300 const std::vector &CSI = MFFrame->getCalleeSavedInfo();
301301 bool HasFP = hasFP(MF);
302302 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
321321 if (SystemZ::GR64BitRegClass.contains(Reg)) {
322322 int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
323323 MMI.addFrameInst(MCCFIInstruction::createOffset(
324 GPRSaveLabel, MRI.getDwarfRegNum(Reg, true), Offset));
324 GPRSaveLabel, MRI->getDwarfRegNum(Reg, true), Offset));
325325 }
326326 }
327327 }
350350 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
351351 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::PROLOG_LABEL))
352352 .addSym(SetFPLabel);
353 unsigned HardFP = MRI.getDwarfRegNum(SystemZ::R11D, true);
353 unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
354354 MMI.addFrameInst(
355355 MCCFIInstruction::createDefCfaRegister(SetFPLabel, HardFP));
356356
378378 // Add CFI for the this save.
379379 if (!FPRSaveLabel)
380380 FPRSaveLabel = MMI.getContext().CreateTempSymbol();
381 unsigned Reg = MRI.getDwarfRegNum(I->getReg(), true);
381 unsigned Reg = MRI->getDwarfRegNum(I->getReg(), true);
382382 int64_t Offset = getFrameIndexOffset(MF, I->getFrameIdx());
383383 MMI.addFrameInst(MCCFIInstruction::createOffset(
384384 FPRSaveLabel, Reg, SPOffsetFromCFA + Offset));
5252 }
5353
5454 unsigned GetX86RegNum(const MCOperand &MO) const {
55 return Ctx.getRegisterInfo().getEncodingValue(MO.getReg()) & 0x7;
55 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7;
5656 }
5757
5858 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
306306 unsigned FramePtr) const {
307307 MachineFrameInfo *MFI = MF.getFrameInfo();
308308 MachineModuleInfo &MMI = MF.getMMI();
309 const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
309 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
310310
311311 // Add callee saved registers to move list.
312312 const std::vector &CSI = MFI->getCalleeSavedInfo();
359359 if (HasFP && FramePtr == Reg)
360360 continue;
361361
362 unsigned DwarfReg = MRI.getDwarfRegNum(Reg, true);
362 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
363363 MMI.addFrameInst(MCCFIInstruction::createOffset(Label, DwarfReg, Offset));
364364 }
365365 }
387387 // FIXME: This is not pretty. MCContext has a ptr to MCObjectFileInfo and
388388 // MCObjectFileInfo needs a MCContext reference in order to initialize itself.
389389 OwningPtr MOFI(new MCObjectFileInfo());
390 MCContext Ctx(*MAI, *MRI, MOFI.get(), &SrcMgr);
390 MCContext Ctx(MAI.get(), MRI.get(), MOFI.get(), &SrcMgr);
391391 MOFI->InitMCObjectFileInfo(TripleName, RelocModel, CMModel, Ctx);
392392
393393 if (SaveTempLabels)
309309
310310 if (Symbolize) {
311311 MOFI.reset(new MCObjectFileInfo);
312 Ctx.reset(new MCContext(*AsmInfo.get(), *MRI.get(), MOFI.get()));
312 Ctx.reset(new MCContext(AsmInfo.get(), MRI.get(), MOFI.get()));
313313 OwningPtr RelInfo(
314314 TheTarget->createMCRelocationInfo(TripleName, *Ctx.get()));
315315 if (RelInfo) {
306306 passes.add(createVerifierPass());
307307
308308 // mark which symbols can not be internalized
309 MCContext Context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(),NULL);
309 MCContext Context(_target->getMCAsmInfo(), _target->getRegisterInfo(), NULL);
310310 Mangler mangler(Context, _target);
311311 std::vector mustPreserveList;
312312 SmallPtrSet asmUsed;
157157
158158 LTOModule::LTOModule(llvm::Module *m, llvm::TargetMachine *t)
159159 : _module(m), _target(t),
160 _context(*_target->getMCAsmInfo(), *_target->getRegisterInfo(), NULL),
160 _context(_target->getMCAsmInfo(), _target->getRegisterInfo(), NULL),
161161 _mangler(_context, t) {}
162162
163163 /// isBitcodeFile - Returns 'true' if the file (or memory contents) is LLVM