llvm.org GIT mirror llvm / 99ab6c6
TargetSchedModel interface. To be implemented... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163934 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 8 years ago
6 changed file(s) with 107 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 //===-- llvm/CodeGen/TargetSchedule.h - Sched Machine Model -----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines a wrapper around MCSchedModel that allows the interface to
10 // benefit from information currently only available in TargetInstrInfo.
11 // Ideally, the scheduling interface would be fully defined in the MC layter.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #ifndef LLVM_TARGET_TARGETSCHEDMODEL_H
16 #define LLVM_TARGET_TARGETSCHEDMODEL_H
17
18 #include "llvm/MC/MCSchedule.h"
19 #include "llvm/MC/MCInstrItineraries.h"
20
21 namespace llvm {
22
23 class TargetRegisterInfo;
24 class TargetSubtargetInfo;
25 class TargetInstrInfo;
26 class MachineInstr;
27
28 /// Provide an instruction scheduling machine model to CodeGen passes.
29 class TargetSchedModel {
30 // For efficiency, hold a copy of the statically defined MCSchedModel for this
31 // processor.
32 MCSchedModel SchedModel;
33 InstrItineraryData InstrItins;
34 const TargetSubtargetInfo *STI;
35 const TargetInstrInfo *TII;
36 public:
37 TargetSchedModel(): STI(0), TII(0) {}
38
39 void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
40 const TargetInstrInfo *tii);
41
42 const TargetInstrInfo *getInstrInfo() const { return TII; }
43
44 /// Return true if this machine model includes an instruction-level scheduling
45 /// model. This is more detailed than the course grain IssueWidth and default
46 /// latency properties, but separate from the per-cycle itinerary data.
47 bool hasInstrSchedModel() const {
48 return SchedModel.hasInstrSchedModel();
49 }
50
51 /// Return true if this machine model includes cycle-to-cycle itinerary
52 /// data. This models scheduling at each stage in the processor pipeline.
53 bool hasInstrItineraries() const {
54 return SchedModel.hasInstrItineraries();
55 }
56
57 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
58 };
59
60 } // namespace llvm
61
62 #endif
198198 MispredictPenalty(mp), ProcID(0), ProcResourceTable(0),
199199 SchedClassTable(0), InstrItineraries(ii) {}
200200
201 unsigned getProcessorID() const { return ProcID; }
202
201203 /// Does this machine model include instruction-level scheduling.
202204 bool hasInstrSchedModel() const {
203205 return SchedClassTable;
117117 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
118118 ///
119119 InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
120
121 /// Initialize an InstrItineraryData instance.
122 void initInstrItins(InstrItineraryData &InstrItins) const;
120123 };
121124
122125 } // End llvm namespace
101101 TargetInstrInfoImpl.cpp
102102 TargetLoweringObjectFileImpl.cpp
103103 TargetOptionsImpl.cpp
104 TargetSchedule.cpp
104105 TwoAddressInstructionPass.cpp
105106 UnreachableBlockElim.cpp
106107 VirtRegMap.cpp
0 //===-- llvm/Target/TargetSchedule.cpp - Sched Machine Model ----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a wrapper around MCSchedModel that allows the interface
10 // to benefit from information currently only available in TargetInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/CodeGen/TargetSchedule.h"
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/Target/TargetSubtargetInfo.h"
17 #include "llvm/Support/CommandLine.h"
18
19 using namespace llvm;
20
21 static cl::opt EnableSchedModel("schedmodel", cl::Hidden, cl::init(false),
22 cl::desc("Use TargetSchedModel for latency lookup"));
23
24 void TargetSchedModel::init(const MCSchedModel &sm,
25 const TargetSubtargetInfo *sti,
26 const TargetInstrInfo *tii) {
27 SchedModel = sm;
28 STI = sti;
29 TII = tii;
30 STI->initInstrItins(InstrItins);
31 }
100100 const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
101101 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
102102 }
103
104 /// Initialize an InstrItineraryData instance.
105 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
106 InstrItins =
107 InstrItineraryData(0, Stages, OperandCycles, ForwardingPaths);
108 }