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[ARM] GlobalISel: Lower more than 4 arguments This adds support for lowering more than 4 arguments (although still i32 only). It uses the handleAssignments / ValueHandler infrastructure extracted from the AArch64 backend in r288658. Differential Revision: https://reviews.llvm.org/D27195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290098 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 3 years ago
3 changed file(s) with 50 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
1818 #include "ARMISelLowering.h"
1919
2020 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
2122
2223 using namespace llvm;
2324
114115
115116 unsigned getStackAddress(uint64_t Size, int64_t Offset,
116117 MachinePointerInfo &MPO) override {
117 llvm_unreachable("Don't know how to get a stack address yet");
118 assert(Size == 4 && "Unsupported size");
119
120 auto &MFI = MIRBuilder.getMF().getFrameInfo();
121
122 int FI = MFI.CreateFixedObject(Size, Offset, true);
123 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
124
125 unsigned AddrReg =
126 MRI.createGenericVirtualRegister(LLT::pointer(MPO.getAddrSpace(), 32));
127 MIRBuilder.buildFrameIndex(AddrReg, FI);
128
129 return AddrReg;
130 }
131
132 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
133 MachinePointerInfo &MPO, CCValAssign &VA) override {
134 assert(Size == 4 && "Unsupported size");
135
136 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
137 MPO, MachineMemOperand::MOLoad, Size, /* Alignment */ 0);
138 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
118139 }
119140
120141 void assignValueToReg(unsigned ValVReg, unsigned PhysReg,
128149 MIRBuilder.getMBB().addLiveIn(PhysReg);
129150 MIRBuilder.buildCopy(ValVReg, PhysReg);
130151 }
131
132 void assignValueToAddress(unsigned ValVReg, unsigned Addr, uint64_t Size,
133 MachinePointerInfo &MPO, CCValAssign &VA) override {
134 llvm_unreachable("Don't know how to assign a value to an address yet");
135 }
136152 };
137153 } // End anonymous namespace
138154
142158 // Quick exit if there aren't any args
143159 if (F.arg_empty())
144160 return true;
145
146 // Stick to only 4 arguments for now
147 if (F.arg_size() > 4)
148 return false;
149161
150162 if (F.isVarArg())
151163 return false;
1818 %sum = add i32 %x, %y
1919 ret i32 %sum
2020 }
21
22 define i32 @test_many_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
23 ; CHECK-LABEL: name: test_many_args
24 ; CHECK: fixedStack:
25 ; CHECK-DAG: id: [[P4:[0-9]]]{{.*}}offset: 0{{.*}}size: 4
26 ; CHECK-DAG: id: [[P5:[0-9]]]{{.*}}offset: 4{{.*}}size: 4
27 ; CHECK: liveins: %r0, %r1, %r2, %r3
28 ; CHECK: [[VREGP2:%[0-9]+]]{{.*}} = COPY %r2
29 ; CHECK: [[FIP5:%[0-9]+]]{{.*}} = G_FRAME_INDEX %fixed-stack.[[P5]]
30 ; CHECK: [[VREGP5:%[0-9]+]]{{.*}} = G_LOAD [[FIP5]]
31 ; CHECK: [[SUM:%[0-9]+]]{{.*}} = G_ADD [[VREGP2]], [[VREGP5]]
32 ; CHECK: %r0 = COPY [[SUM]]
33 ; CHECK: BX_RET 14, _, implicit %r0
34 entry:
35 %sum = add i32 %p2, %p5
36 ret i32 %sum
37 }
1414 %sum = add i32 %x, %y
1515 ret i32 %sum
1616 }
17
18 define i32 @test_many_args(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
19 ; CHECK-LABEL: test_many_args:
20 ; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4
21 ; CHECK: ldr [[P5:r[0-9]+]], {{.*}}[[P5ADDR]]
22 ; CHECK: add r0, r2, [[P5]]
23 ; CHECK: bx lr
24 entry:
25 %sum = add i32 %p2, %p5
26 ret i32 %sum
27 }