llvm.org GIT mirror llvm / 994c727
Use IndexedMap for MachineRegisterInfo as well. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123106 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 9 years ago
3 changed file(s) with 34 addition(s) and 35 deletion(s). Raw diff Collapse all Expand all
5454 return storage_[toIndex_(n)];
5555 }
5656
57 void reserve(typename StorageT::size_type s) {
58 storage_.reserve(s);
59 }
60
5761 void clear() {
5862 storage_.clear();
5963 }
1515
1616 #include "llvm/Target/TargetRegisterInfo.h"
1717 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
1819 #include
1920
2021 namespace llvm {
2324 /// registers, including vreg register classes, use/def chains for registers,
2425 /// etc.
2526 class MachineRegisterInfo {
26 /// VRegInfo - Information we keep for each virtual register. The entries in
27 /// this vector are actually converted to vreg numbers by adding the
28 /// TargetRegisterInfo::FirstVirtualRegister delta to their index.
27 /// VRegInfo - Information we keep for each virtual register.
2928 ///
3029 /// Each element in this list contains the register class of the vreg and the
3130 /// start of the use/def list for the register.
32 std::vector > VRegInfo;
31 IndexedMap,
32 VirtReg2IndexFunctor> VRegInfo;
3333
3434 /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
3535 /// virtual registers. For each target register class, it keeps a list of
4343 /// register for allocation. For example, if the hint is <0, 1024>, it means
4444 /// the allocator should prefer the physical register allocated to the virtual
4545 /// register of the hint.
46 std::vector > RegAllocHints;
46 IndexedMap, VirtReg2IndexFunctor> RegAllocHints;
4747
4848 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
4949 /// physical registers.
158158 /// getRegUseDefListHead - Return the head pointer for the register use/def
159159 /// list for the specified virtual or physical register.
160160 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
161 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
161 if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo))
162162 return PhysRegUseDefLists[RegNo];
163 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
164163 return VRegInfo[RegNo].second;
165164 }
166165
167166 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
168 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
167 if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo))
169168 return PhysRegUseDefLists[RegNo];
170 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
171169 return VRegInfo[RegNo].second;
172170 }
173171
193191 /// getRegClass - Return the register class of the specified virtual register.
194192 ///
195193 const TargetRegisterClass *getRegClass(unsigned Reg) const {
196 Reg -= TargetRegisterInfo::FirstVirtualRegister;
197 assert(Reg < VRegInfo.size() && "Invalid vreg!");
198194 return VRegInfo[Reg].first;
199195 }
200196
235231 /// setRegAllocationHint - Specify a register allocation hint for the
236232 /// specified virtual register.
237233 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
238 Reg -= TargetRegisterInfo::FirstVirtualRegister;
239 assert(Reg < VRegInfo.size() && "Invalid vreg!");
240234 RegAllocHints[Reg].first = Type;
241235 RegAllocHints[Reg].second = PrefReg;
242236 }
245239 /// specified virtual register.
246240 std::pair
247241 getRegAllocationHint(unsigned Reg) const {
248 Reg -= TargetRegisterInfo::FirstVirtualRegister;
249 assert(Reg < VRegInfo.size() && "Invalid vreg!");
250242 return RegAllocHints[Reg];
251243 }
252244
2929
3030 MachineRegisterInfo::~MachineRegisterInfo() {
3131 #ifndef NDEBUG
32 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i)
33 assert(VRegInfo[i].second == 0 && "Vreg use list non-empty still?");
32 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
33 assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 &&
34 "Vreg use list non-empty still?");
3435 for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i)
3536 assert(!PhysRegUseDefLists[i] &&
3637 "PhysRegUseDefLists has entries after all instructions are deleted");
4344 ///
4445 void
4546 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
46 unsigned VR = Reg;
47 Reg -= TargetRegisterInfo::FirstVirtualRegister;
48 assert(Reg < VRegInfo.size() && "Invalid vreg!");
4947 const TargetRegisterClass *OldRC = VRegInfo[Reg].first;
5048 VRegInfo[Reg].first = RC;
5149
5250 // Remove from old register class's vregs list. This may be slow but
5351 // fortunately this operation is rarely needed.
5452 std::vector &VRegs = RegClass2VRegMap[OldRC->getID()];
55 std::vector::iterator I = std::find(VRegs.begin(), VRegs.end(), VR);
53 std::vector::iterator I =
54 std::find(VRegs.begin(), VRegs.end(), Reg);
5655 VRegs.erase(I);
5756
5857 // Add to new register class's vregs list.
59 RegClass2VRegMap[RC->getID()].push_back(VR);
58 RegClass2VRegMap[RC->getID()].push_back(Reg);
6059 }
6160
6261 const TargetRegisterClass *
7978 unsigned
8079 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
8180 assert(RegClass && "Cannot create register without RegClass!");
81
82 // New virtual register number.
83 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
84
8285 // Add a reg, but keep track of whether the vector reallocated or not.
83 void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
84 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
85 RegAllocHints.push_back(std::make_pair(0, 0));
86
87 if (!((&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)))
86 const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0);
87 void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg];
88 VRegInfo.grow(Reg);
89 VRegInfo[Reg].first = RegClass;
90 RegAllocHints.grow(Reg);
91
92 if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase)
8893 // The vector reallocated, handle this now.
8994 HandleVRegListReallocation();
90 unsigned VR = getLastVirtReg();
91 RegClass2VRegMap[RegClass->getID()].push_back(VR);
92 return VR;
95 RegClass2VRegMap[RegClass->getID()].push_back(Reg);
96 return Reg;
9397 }
9498
9599 /// HandleVRegListReallocation - We just added a virtual register to the
98102 void MachineRegisterInfo::HandleVRegListReallocation() {
99103 // The back pointers for the vreg lists point into the previous vector.
100104 // Update them to point to their correct slots.
101 for (unsigned i = 0, e = VRegInfo.size(); i != e; ++i) {
102 MachineOperand *List = VRegInfo[i].second;
105 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
106 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
107 MachineOperand *List = VRegInfo[Reg].second;
103108 if (!List) continue;
104109 // Update the back-pointer to be accurate once more.
105 List->Contents.Reg.Prev = &VRegInfo[i].second;
110 List->Contents.Reg.Prev = &VRegInfo[Reg].second;
106111 }
107112 }
108113
125130 /// register or null if none is found. This assumes that the code is in SSA
126131 /// form, so there should only be one definition.
127132 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
128 assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() &&
129 "Invalid vreg!");
130133 // Since we are in SSA form, we can use the first definition.
131134 if (!def_empty(Reg))
132135 return &*def_begin(Reg);