llvm.org GIT mirror llvm / 993a111
Fix a bunch of trivial cases of 'CHECK[^:]*$' in the tests. NFCI I looked into adding a warning / error for this to FileCheck, but there doesn't seem to be a good way to avoid it triggering on the instances of it in RUN lines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@244481 91177308-0d34-0410-b5e6-96231b3b80d8 Jonathan Roelofs 4 years ago
26 changed file(s) with 45 addition(s) and 45 deletion(s). Raw diff Collapse all Expand all
2323
2424 ; CHECK: store i64 2
2525 ; CHECK: load
26 ; CHECK; store i64 1
26 ; CHECK: store i64 1
2727
2828 store i64 2, i64* %ptr.64, align 8
2929 %r = load i64, i64* %either_ptr.64, align 8
1212 ; CHECK-NEXT: ldr [[BLOCKBASE:x[0-9]+]], {{\[}}[[ADDR]]]
1313 ; CHECK-NEXT: ldrb [[BLOCKVAL1:w[0-9]+]], {{\[}}[[BLOCKBASE]], w0, sxtw]
1414 ; CHECK-NEXT: ldrb [[BLOCKVAL2:w[0-9]+]], {{\[}}[[BLOCKBASE]], w1, sxtw]
15 ; CHECK-NEXT cmp [[BLOCKVAL1]], [[BLOCKVAL2]]
16 ; CHECK-NEXT b.ne
15 ; CHECK-NEXT: cmp [[BLOCKVAL1]], [[BLOCKVAL2]]
16 ; CHECK-NEXT: b.ne
1717 ; Next BB
1818 ; CHECK: add [[BLOCKBASE2:x[0-9]+]], [[BLOCKBASE]], w1, sxtw
1919 ; CHECK-NEXT: add [[BLOCKBASE1:x[0-9]+]], [[BLOCKBASE]], w0, sxtw
5858 %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
5959 ret i32 %cnt
6060 ; CHECK-LABEL: cnt32:
61 ; CHECK-NOT 16b
61 ; CHECK-NOT: 16b
6262 ; CHECK: ret
6363 }
6464
6666 %cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
6767 ret i64 %cnt
6868 ; CHECK-LABEL: cnt64:
69 ; CHECK-NOT 16b
69 ; CHECK-NOT: 16b
7070 ; CHECK: ret
7171 }
7272
6161 ; ...
6262 ; CHECK-NOT: add sp,
6363 ; CHECK: vpop {d6, d7, d8, d9}
64 ; CHECKL pop {r[[GLOBREG]], pc}
64 ; CHECK: pop {r[[GLOBREG]], pc}
6565
6666 ; iOS uses aligned NEON stores here, which is convenient since we
6767 ; want to make sure that works too.
33
44 declare void @bar(<4 x i32>)
55
6 ; CHECK-LABEL @foo
6 ; CHECK-LABEL: @foo
77 define void @foo(<4 x i32> %a) {
88 ; CHECK: st.param.v4.b32
99 tail call void @bar(<4 x i32> %a)
99 }
1010
1111 ; CHECK-LABEL: @main
12 ; CHECK-DAG li 4, 0
12 ; CHECK-DAG: li 4, 0
1313 ; CHECK-DAG: crxor 6, 6, 6
1414 ; CHECK: bl printf
1515
88 %shr2 = lshr i32 %mul, 5
99 ret i32 %shr2
1010
11 ; CHECK-LABEL @foo
11 ; CHECK-LABEL: @foo
1212 ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
1313 ; CHECK: blr
1414 }
2222 %or = or i32 %shr, %shl
2323 ret i32 %or
2424
25 ; CHECK-LABEL @test6
25 ; CHECK-LABEL: @test6
2626 ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
2727 ; CHECK: blr
2828 }
3333 %cond = select i1 %cmp, i32 %a, i32 %b
3434 ret i32 %cond
3535
36 ; CHECK-LABEL @min
36 ; CHECK-LABEL: @min
3737 ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32
3838 ; CHECK: blr
3939 }
88 %div = sdiv i32 %a, 8
99 ret i32 %div
1010
11 ; CHECK-LABEL @foo4
11 ; CHECK-LABEL: @foo4
1212 ; CHECK: srawi [[REG1:[0-9]+]], 3, 3
1313 ; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
1414 ; CHECK: extsw 3, [[REG2]]
2121 %div = sdiv i64 %a, 8
2222 ret i64 %div
2323
24 ; CHECK-LABEL @foo8
24 ; CHECK-LABEL: @foo8
2525 ; CHECK: sradi [[REG1:[0-9]+]], 3, 3
2626 ; CHECK: addze 3, [[REG1]]
2727 ; CHECK: blr
2828
29 ; CHECK-32-LABEL @foo8
29 ; CHECK-32-LABEL: @foo8
3030 ; CHECK-32-NOT: sradi
3131 ; CHECK-32: blr
3232 }
5757 ; CHECK: neg 3, [[REG2]]
5858 ; CHECK: blr
5959
60 ; CHECK-32-LABEL @foo8n
60 ; CHECK-32-LABEL: @foo8n
6161 ; CHECK-32-NOT: sradi
6262 ; CHECK-32: blr
6363 }
1313 %result = add <1 x i128> %x,
1414 ret <1 x i128> %result
1515 ; CHECK-LABEL: @increment_by_one
16 ; CHECK vadduqm 2, 2, 3
16 ; CHECK: vadduqm 2, 2, 3
1717 }
1818
1919 define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {
3636 %result = sub <1 x i128> %x,
3737 ret <1 x i128> %result
3838 ; CHECK-LABEL: @decrement_by_one
39 ; CHECK vsubuqm 2, 2, 3
39 ; CHECK: vsubuqm 2, 2, 3
4040 }
4141
4242 define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
4545 %result = sub <1 x i128> %x, %tmpvec2
4646 ret <1 x i128> %result
4747 ; CHECK-LABEL: @decrement_by_val
48 ; CHECK vsubuqm 2, 2, 3
48 ; CHECK: vsubuqm 2, 2, 3
4949 }
5050
5151 declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
1616 ; CHECK: .note.gc
1717 ; CHECK-NEXT: .align 8
1818 ; safe point count
19 ; CHECK .short 1
20 ; CHECK .long .Ltmp0
19 ; CHECK: .short 1
20 ; CHECK: .long .Ltmp0
2121 ; stack frame size (in words)
22 ; CHECK .short -1
22 ; CHECK: .short -1
2323 ; stack arity (arguments on the stack)
24 ; CHECK .short 0
24 ; CHECK: .short 0
2525 ; live root count
26 ; CHECK .short 0
26 ; CHECK: .short 0
2727
1010
1111 ; CHECK-LABEL: @_Dmain
1212 ; CHECK: load i8, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0)
13 ; CHECK ret
13 ; CHECK: ret
1414 define fastcc i32 @_Dmain(%"char[][]" %unnamed) {
1515 entry:
1616 %tmp = getelementptr [7 x i8], [7 x i8]* @.str, i32 0, i32 0 ; [#uses=1]
55
66 ; CHECK-LABEL: test1:
77 ; %arg lives in xmm0 and it shouldn't be redefined until it is used in the FMA.
8 ; CHECK-NOT {{.*}}, %xmm0
8 ; CHECK-NOT: {{.*}}, %xmm0
99 ; %addr lives in rdi.
1010 ; %addr2 lives in rsi.
1111 ; CHECK: vmovss (%rsi), [[ADDR2:%xmm[0-9]+]]
8282 ; CHECK-NOT: , [[CPY1]]
8383 ; CHECK: punpcklbw [[CPY2]], [[CPY2]]
8484 ; CHECK-NEXT: punpckhwd [[CPY2]], [[CPY2]]
85 ; CHECK-NEXT pslld $31, [[CPY2]]
85 ; CHECK-NEXT: pslld $31, [[CPY2]]
8686 ; Check that CPY1 is not redefined.
8787 ; CHECK-NOT: , [[CPY1]]
8888 ; CHECK: punpcklbw [[CPY1]], [[CPY1]]
8989 ; CHECK-NEXT: punpcklwd [[CPY1]], [[CPY1]]
90 ; CHECK-NEXT pslld $31, [[CPY1]]
90 ; CHECK-NEXT: pslld $31, [[CPY1]]
9191 define <16 x float> @foo(<16 x float> %x) {
9292 bb:
9393 %v3 = icmp slt <16 x i32> undef, zeroinitializer
112112 normal_return:
113113 ; CHECK-LABEL: %normal_return
114114 ; CHECK: cmoveq {{.*}}[[REGVAL2]]{{.*}}
115 ; CHECK retq
115 ; CHECK: retq
116116 %a1 = phi i64 addrspace(1)* [%val1.relocated, %left.relocs], [%val3.relocated, %right.relocs]
117117 %a2 = phi i64 addrspace(1)* [%val2.relocated_left, %left.relocs], [%val2.relocated_right, %right.relocs]
118118 %ret = select i1 %cond, i64 addrspace(1)* %a1, i64 addrspace(1)* %a2
5656 Check ObjC specific accelerators.
5757 CHECK: .apple_objc contents:
5858 CHECK: Name{{.*}}"TestInterface"
59 CHECK-NOT Name
59 CHECK-NOT: Name
6060 CHECK: {Atom[0]: [[READONLY]]}
6161 CHECK: {Atom[0]: [[ASSIGN]]}
6262 CHECK: {Atom[0]: [[SETASSIGN]]}
3636 //CHECK-V8: vqrdmlsh.f32 q3, q4, q5
3737 //CHECK-V8: ^
3838 //CHECK-V8: error: invalid operand for instruction
39 //CHECK-V8 vqrdmlsh.f64 d3, d5, d5
39 //CHECK-V8: vqrdmlsh.f64 d3, d5, d5
4040 //CHECK-V8: ^
4141
4242 vqrdmlah.s16 d0, d1, d2
5353 ifcc4 %eax, %ecx ## test
5454 ifcc4 %ecx, %eax ## test
5555
56 // CHECK-NOT movl
56 // CHECK-NOT: movl
5757 // CHECK: subl $1, %esp
5858 .set cc,0
5959 ifcc movl, %esp, %ebp
4343 ifcc4 %eax %ecx ## test
4444 ifcc4 %ecx, %eax ## test
4545
46 // CHECK-NOT movl
46 // CHECK-NOT: movl
4747 // CHECK: subl $1, %esp
4848 .set cc,0
4949 ifcc movl %esp, %ebp
99 ; Convert to setne int %X, 12
1010 %c = icmp ne i32 %A, 12 ; [#uses=1]
1111 ret i1 %c
12 ; CHECK-LABEL @test1(
12 ; CHECK-LABEL: @test1(
1313 ; CHECK: %c = icmp ne i32 %X, 12
1414 ; CHECK: ret i1 %c
1515 }
2020 ; Convert to setne int %X, %Y
2121 %c = icmp ne i32 %A, %B ; [#uses=1]
2222 ret i1 %c
23 ; CHECK-LABEL @test2(
23 ; CHECK-LABEL: @test2(
2424 ; CHECK: %c = icmp ne i32 %X, %Y
2525 ; CHECK: ret i1 %c
2626 }
162162 ; CHECK-LABEL: @test19(
163163 ; CHECK-NEXT: icmp eq i32 %x, 1
164164 ; CHECK-NEXT: zext i1 %{{.*}} to i32
165 ; CHECK-NEXT ret i32
165 ; CHECK-NEXT: ret i32
166166 }
167167
168168 define i32 @test20(i32 %x) {
1111 %D = and i39 %V, 274877906943
1212 %R = or i39 %B, %D
1313 ret i39 %R
14 ; CHECK-LABEL @test1
14 ; CHECK-LABEL: @test1
1515 ; CHECK-NEXT: and {{.*}}, -274877906944
1616 ; CHECK-NEXT: add
1717 ; CHECK-NEXT: ret
2929 %D = and i399 %V, 274877906943
3030 %R = or i399 %B, %D
3131 ret i399 %R
32 ; CHECK-LABEL @test2
32 ; CHECK-LABEL: @test2
3333 ; CHECK-NEXT: and {{.*}}, 18446742974197923840
3434 ; CHECK-NEXT: add
3535 ; CHECK-NEXT: ret
77
88 define i1 @cmp_no_range(i8*, i8*) {
99 ; CHECK-LABEL: @cmp_no_range
10 ; CHECK-NEXT %v1 = load i8, i8* %0
11 ; CHECK-NEXT %v2 = load i8, i8* %1
12 ; CHECK-NEXT %out = icmp eq i8 %v1, %v2
13 ; CHECK-NEXT ret i1 %out
10 ; CHECK-NEXT: %v1 = load i8, i8* %0
11 ; CHECK-NEXT: %v2 = load i8, i8* %1
12 ; CHECK-NEXT: %out = icmp eq i8 %v1, %v2
13 ; CHECK-NEXT: ret i1 %out
1414 %v1 = load i8, i8* %0
1515 %v2 = load i8, i8* %1
1616 %out = icmp eq i8 %v1, %v2
22 ; The two va_arg instructions depend on the memory/context, are therfore not
33 ; identical and the sub should not be optimized to 0 by reassociate.
44 ;
5 ; CHECK-LABEL @func(
5 ; CHECK-LABEL: @func(
66 ; ...
77 ; CHECK: %v0 = va_arg i8** %varargs, i32
88 ; CHECK: %v1 = va_arg i8** %varargs, i32
231231 ; CHECK: phi i8 addrspace(1)*
232232 ; CHECK-DAG: %outer-loop ]
233233 ; CHECK-DAG: [ %arg2.relocated, %inner-loop ]
234 ; CHECKL phi i8 addrspace(1)*
234 ; CHECK: phi i8 addrspace(1)*
235235 ; CHECK-DAG: %outer-loop ]
236236 ; CHECK-DAG: [ %arg1.relocated, %inner-loop ]
237237 ; CHECK: gc.statepoint
155155
156156 declare void @ctor(%struct.X*)
157157 define void @test10(%struct.X* noalias sret %agg.result, i1 zeroext %b) {
158 ; CHECK-LABEL @test10
158 ; CHECK-LABEL: @test10
159159 entry:
160160 %x = alloca %struct.X, align 8
161161 br i1 %b, label %if.then, label %if.end
116116 CHECK: DW_AT_location [DW_FORM_data4] (0x00000025)
117117 CHECK: DW_TAG_lexical_block [14] *
118118 CHECK: DW_AT_low_pc [DW_FORM_addr] (0x0000000100000f94)
119 CHECK DW_AT_high_pc [DW_FORM_addr] (0x0000000100000fa7)
119 CHECK: DW_AT_high_pc [DW_FORM_addr] (0x0000000100000fa7)
120120 CHECK: DW_TAG_inlined_subroutine [15]
121121 CHECK: DW_AT_abstract_origin [DW_FORM_ref4] (cu + 0x009a => {0x000001d4} "inc")
122122 CHECK: DW_AT_ranges [DW_FORM_data4] (0x00000000