llvm.org GIT mirror llvm / 991b6a2
Add custom conversion from v2u32 to v2f32 in 32-bit mode - As there's no 64-bit GPRs in 32-bit mode, a custom conversion from v2u32 to v2f32 is added to improve the efficiency of the code generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166545 91177308-0d34-0410-b5e6-96231b3b80d8 Michael Liao 7 years ago
3 changed file(s) with 35 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
949949
950950 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
951951 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
952 // As there is no 64-bit GPR available, we need build a special custom
953 // sequence to convert from v2i32 to v2f32.
954 if (!Subtarget->is64Bit())
955 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
952956
953957 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
954958 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1175111755 else
1175211756 Results.push_back(FIST);
1175311757 }
11758 return;
11759 }
11760 case ISD::UINT_TO_FP: {
11761 if (N->getOperand(0).getValueType() != MVT::v2i32 &&
11762 N->getValueType(0) != MVT::v2f32)
11763 return;
11764 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
11765 N->getOperand(0));
11766 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11767 MVT::f64);
11768 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
11769 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
11770 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
11771 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
11772 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
11773 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
1175411774 return;
1175511775 }
1175611776 case ISD::FP_ROUND: {
58815881 (VPMOVZXDQrm addr:$src)>;
58825882 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
58835883 (VPMOVZXDQrm addr:$src)>;
5884 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5885 (VPMOVZXDQrm addr:$src)>;
58845886 }
58855887
58865888 let Predicates = [UseSSE41] in {
59125914 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
59135915 (PMOVZXDQrm addr:$src)>;
59145916 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5917 (PMOVZXDQrm addr:$src)>;
5918 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
59155919 (PMOVZXDQrm addr:$src)>;
59165920 }
59175921
0 ; RUN: llc < %s -mtriple=i686-linux-pc -mcpu=corei7 | FileCheck %s
1
2 define <2 x float> @bar(<2 x i32> %in) {
3 %r = uitofp <2 x i32> %in to <2 x float>
4 ret <2 x float> %r
5 ; CHECK: bar
6 ; CHECK: or
7 ; CHECK: subpd
8 ; CHECK: cvtpd2ps
9 ; CHECK: ret
10 }