llvm.org GIT mirror llvm / 98ed117
[mips][FastISel] Handle calls with non legal types i8 and i16. Summary: Allow calls with non legal integer types based on i8 and i16 to be processed by mips fast-isel. Based on a patch by Reed Kotler. Test Plan: "Make check" test forthcoming. Test-suite passes at O0/O2 and with mips32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6770 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237121 91177308-0d34-0410-b5e6-96231b3b80d8 Vasileios Kalintiris 5 years ago
2 changed file(s) with 187 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
999999 }
10001000 }
10011001 }
1002 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32)) && VA.isMemLoc()) {
1002 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1003 (ArgVT == MVT::i8)) &&
1004 VA.isMemLoc()) {
10031005 switch (VA.getLocMemOffset()) {
10041006 case 0:
10051007 VA.convertToReg(Mips::A0);
44 ; RUN: -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \
55 ; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2
66
7 declare void @xb(i8)
8
9 define void @cxb() {
10 ; ALL-LABEL: cxb:
11
12 ; ALL: addiu $[[T0:[0-9]+]], $zero, 10
13
14 ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 24
15 ; 32R1: sra $4, $[[T1]], 24
16
17 ; 32R2: seb $4, $[[T0]]
18 call void @xb(i8 10)
19 ret void
20 }
21
22 declare void @xh(i16)
23
24 define void @cxh() {
25 ; ALL-LABEL: cxh:
26
27 ; ALL: addiu $[[T0:[0-9]+]], $zero, 10
28
29 ; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 16
30 ; 32R1: sra $4, $[[T1]], 16
31
32 ; 32R2: seh $4, $[[T0]]
33 call void @xh(i16 10)
34 ret void
35 }
36
737 declare void @xi(i32)
838
939 define void @cxi() {
1343 ; ALL-DAG: lw $25, %got(xi)(${{[0-9]+}})
1444 ; ALL: jalr $25
1545 call void @xi(i32 10)
46 ret void
47 }
48
49 declare void @xbb(i8, i8)
50
51 define void @cxbb() {
52 ; ALL-LABEL: cxbb:
53
54 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76
55 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101
56
57 ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 24
58 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 24
59 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24
60 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24
61
62 ; 32R2-DAG: seb $4, $[[T0]]
63 ; 32R2-DAG: seb $5, $[[T1]]
64 call void @xbb(i8 76, i8 101)
65 ret void
66 }
67
68 declare void @xhh(i16, i16)
69
70 define void @cxhh() {
71 ; ALL-LABEL: cxhh:
72
73 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76
74 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101
75
76 ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16
77 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 16
78 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16
79 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16
80
81 ; 32R2-DAG: seh $4, $[[T0]]
82 ; 32R2-DAG: seh $5, $[[T1]]
83 call void @xhh(i16 76, i16 101)
1684 ret void
1785 }
1886
2694 ; ALL-DAG: lw $25, %got(xii)(${{[0-9]+}})
2795 ; ALL: jalr $25
2896 call void @xii(i32 746, i32 892)
97 ret void
98 }
99
100 declare void @xccc(i8, i8, i8)
101
102 define void @cxccc() {
103 ; ALL-LABEL: cxccc:
104
105 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
106 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
107 ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
108
109 ; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 24
110 ; 32R1-DAG: sra $4, $[[T3]], 24
111 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24
112 ; 32R1-DAG: sra $5, $[[T4]], 24
113 ; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 24
114 ; 32R1-DAG: sra $6, $[[T5]], 24
115
116 ; 32R2-DAG: seb $4, $[[T0]]
117 ; 32R2-DAG: seb $5, $[[T1]]
118 ; 32R2-DAG: seb $6, $[[T2]]
119 call void @xccc(i8 88, i8 44, i8 11)
120 ret void
121 }
122
123 declare void @xhhh(i16, i16, i16)
124
125 define void @cxhhh() {
126 ; ALL-LABEL: cxhhh:
127
128 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
129 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
130 ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
131
132 ; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 16
133 ; 32R1-DAG: sra $4, $[[T3]], 16
134 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16
135 ; 32R1-DAG: sra $5, $[[T4]], 16
136 ; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 16
137 ; 32R1-DAG: sra $6, $[[T5]], 16
138
139 ; 32R2-DAG: seh $4, $[[T0]]
140 ; 32R2-DAG: seh $5, $[[T1]]
141 ; 32R2-DAG: seh $6, $[[T2]]
142 call void @xhhh(i16 88, i16 44, i16 11)
29143 ret void
30144 }
31145
40154 ; ALL-DAG: lw $25, %got(xiii)(${{[0-9]+}})
41155 ; ALL: jalr $25
42156 call void @xiii(i32 88, i32 44, i32 11)
157 ret void
158 }
159
160 declare void @xcccc(i8, i8, i8, i8)
161
162 define void @cxcccc() {
163 ; ALL-LABEL: cxcccc:
164
165 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
166 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
167 ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
168 ; ALL-DAG: addiu $[[T3:[0-9]+]], $zero, 33
169
170 ; FIXME: We should avoid the unnecessary spill/reload here.
171
172 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T0]], 24
173 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24
174 ; 32R1-DAG: sw $4, 16($sp)
175 ; 32R1-DAG: move $4, $[[T5]]
176 ; 32R1-DAG: sll $[[T6:[0-9]+]], $[[T1]], 24
177 ; 32R1-DAG: sra $5, $[[T6]], 24
178 ; 32R1-DAG: sll $[[T7:[0-9]+]], $[[T2]], 24
179 ; 32R1-DAG: sra $6, $[[T7]], 24
180 ; 32R1: lw $[[T8:[0-9]+]], 16($sp)
181 ; 32R1: sll $[[T9:[0-9]+]], $[[T8]], 24
182 ; 32R1: sra $7, $[[T9]], 24
183
184 ; 32R2-DAG: seb $[[T4:[0-9]+]], $[[T0]]
185 ; 32R2-DAG: sw $4, 16($sp)
186 ; 32R2-DAG: move $4, $[[T4]]
187 ; 32R2-DAG: seb $5, $[[T1]]
188 ; 32R2-DAG: seb $6, $[[T2]]
189 ; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp)
190 ; 32R2: seb $7, $[[T5]]
191 call void @xcccc(i8 88, i8 44, i8 11, i8 33)
192 ret void
193 }
194
195 declare void @xhhhh(i16, i16, i16, i16)
196
197 define void @cxhhhh() {
198 ; ALL-LABEL: cxhhhh:
199
200 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
201 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
202 ; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
203 ; ALL-DAG: addiu $[[T3:[0-9]+]], $zero, 33
204
205 ; FIXME: We should avoid the unnecessary spill/reload here.
206
207 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T0]], 16
208 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16
209 ; 32R1-DAG: sw $4, 16($sp)
210 ; 32R1-DAG: move $4, $[[T5]]
211 ; 32R1-DAG: sll $[[T6:[0-9]+]], $[[T1]], 16
212 ; 32R1-DAG: sra $5, $[[T6]], 16
213 ; 32R1-DAG: sll $[[T7:[0-9]+]], $[[T2]], 16
214 ; 32R1-DAG: sra $6, $[[T7]], 16
215 ; 32R1: lw $[[T8:[0-9]+]], 16($sp)
216 ; 32R1: sll $[[T9:[0-9]+]], $[[T8]], 16
217 ; 32R1: sra $7, $[[T9]], 16
218
219 ; 32R2-DAG: seh $[[T4:[0-9]+]], $[[T0]]
220 ; 32R2-DAG: sw $4, 16($sp)
221 ; 32R2-DAG: move $4, $[[T4]]
222 ; 32R2-DAG: seh $5, $[[T1]]
223 ; 32R2-DAG: seh $6, $[[T2]]
224 ; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp)
225 ; 32R2: seh $7, $[[T5]]
226 call void @xhhhh(i16 88, i16 44, i16 11, i16 33)
43227 ret void
44228 }
45229