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[PPC] Properly update register save area offsets The variables MinGPR/MinG8R were not updated properly when resetting the offsets, which in the included testcase lead to saving the CR register in the same location as R30. This fixes another issue reported in PR26519. Differential Revision: https://reviews.llvm.org/D33017 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303257 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 3 years ago
4 changed file(s) with 171 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
17641764 // Check whether the frame pointer register is allocated. If so, make sure it
17651765 // is spilled to the correct offset.
17661766 if (needsFP(MF)) {
1767 HasGPSaveArea = true;
1768
17691767 int FI = PFI->getFramePointerSaveIndex();
17701768 assert(FI && "No Frame Pointer Save Slot!");
1771
17721769 MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1770 // FP is R31/X31, so no need to update MinGPR/MinG8R.
1771 HasGPSaveArea = true;
17731772 }
17741773
17751774 if (PFI->usesPICBase()) {
1776 HasGPSaveArea = true;
1777
17781775 int FI = PFI->getPICBasePointerSaveIndex();
17791776 assert(FI && "No PIC Base Pointer Save Slot!");
1780
17811777 MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1778
1779 MinGPR = std::min(MinGPR, PPC::R30);
1780 HasGPSaveArea = true;
17821781 }
17831782
17841783 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
17851784 if (RegInfo->hasBasePointer(MF)) {
1786 HasGPSaveArea = true;
1787
17881785 int FI = PFI->getBasePointerSaveIndex();
17891786 assert(FI && "No Base Pointer Save Slot!");
1790
17911787 MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
1788
1789 unsigned BP = RegInfo->getBaseRegister(MF);
1790 if (PPC::G8RCRegClass.contains(BP)) {
1791 MinG8R = std::min(MinG8R, BP);
1792 HasG8SaveArea = true;
1793 } else if (PPC::GPRCRegClass.contains(BP)) {
1794 MinGPR = std::min(MinGPR, BP);
1795 HasGPSaveArea = true;
1796 }
17921797 }
17931798
17941799 // General register save area starts right below the Floating-point
0 ; RUN: llc -march=ppc64 -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC64
1 ; RUN: llc -march=ppc32 -ppc-always-use-base-pointer < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32
2 ; RUN: llc -march=ppc32 -ppc-always-use-base-pointer -relocation-model pic < %s | FileCheck %s --check-prefix CHECK --check-prefix PPC32PIC
3
4 ; CHECK-LABEL: fred:
5
6 ; Check for saving/restoring frame pointer (X31) and base pointer (X30)
7 ; on ppc64:
8 ; PPC64: std 31, -8(1)
9 ; PPC64: std 30, -16(1)
10 ; PPC64: ld 31, -8(1)
11 ; PPC64: ld 30, -16(1)
12
13 ; Check for saving/restoring frame pointer (R31) and base pointer (R30)
14 ; on ppc32:
15 ; PPC32: stwux 1, 1, 0
16 ; PPC32; addic 0, 0, -4
17 ; PPC32: stwx 31, 0, 0
18 ; PPC32: addic 0, 0, -4
19 ; PPC32: stwx 30, 0, 0
20 ; The restore sequence:
21 ; PPC32: lwz 31, 0(1)
22 ; PPC32: addic 30, 0, 8
23 ; PPC32: lwz 0, -4(31)
24 ; PPC32: lwz 30, -8(31)
25 ; PPC32: mr 1, 31
26 ; PPC32: mr 31, 0
27
28 ; Check for saving/restoring frame pointer (R31) and base pointer (R29)
29 ; on ppc32/pic. This is mostly the same as without pic, except that base
30 ; pointer is in R29.
31 ; PPC32PIC: stwux 1, 1, 0
32 ; PPC32PIC; addic 0, 0, -4
33 ; PPC32PIC: stwx 31, 0, 0
34 ; PPC32PIC: addic 0, 0, -8
35 ; PPC32PIC: stwx 29, 0, 0
36 ; The restore sequence:
37 ; PPC32PIC: lwz 31, 0(1)
38 ; PPC32PIC: addic 29, 0, 12
39 ; PPC32PIC: lwz 0, -4(31)
40 ; PPC32PIC: lwz 29, -12(31)
41 ; PPC32PIC: mr 1, 31
42 ; PPC32PIC: mr 31, 0
43
44
45 target datalayout = "E-m:e-p:32:32-i64:64-n32"
46 target triple = "powerpc-unknown-freebsd"
47
48 define i64 @fred() local_unnamed_addr #0 {
49 entry:
50 ret i64 0
51 }
52
53 attributes #0 = { norecurse readnone nounwind sspstrong "no-frame-pointer-elim"="true" "target-cpu"="ppc" }
0 ; RUN: llc -march=ppc32 -relocation-model pic < %s | FileCheck %s
1 ;
2 ; Make sure that the CR register is saved correctly on PPC32/SVR4.
3
4 ; CHECK-LABEL: fred:
5 ; CHECK: stwu 1, -32(1)
6 ; CHECK: stw 31, 28(1)
7 ; CHECK: mr 31, 1
8 ; CHECK: stw 30, 24(1)
9 ; CHECK: mfcr [[CR:[0-9]+]]
10 ; CHECK: stw [[CR]], 20(31)
11
12 target datalayout = "E-m:e-p:32:32-i64:64-n32"
13 target triple = "powerpc-unknown-freebsd"
14
15 ; Function Attrs: norecurse nounwind readnone sspstrong
16 define i64 @fred(double %a0) local_unnamed_addr #0 {
17 b1:
18 %v2 = fcmp olt double %a0, 0x43E0000000000000
19 br i1 %v2, label %b3, label %b7
20
21 b3: ; preds = %b1
22 %v4 = fcmp olt double %a0, 0xC3E0000000000000
23 %v5 = fptosi double %a0 to i64
24 %v6 = select i1 %v4, i64 -9223372036854775808, i64 %v5
25 br label %b14
26
27 b7: ; preds = %b1
28 %v8 = fcmp olt double %a0, 0x43F0000000000000
29 br i1 %v8, label %b9, label %b11
30
31 b9: ; preds = %b7
32 %v10 = fptoui double %a0 to i64
33 br label %b14
34
35 b11: ; preds = %b7
36 %v12 = fcmp ogt double %a0, 0.000000e+00
37 %v13 = sext i1 %v12 to i64
38 br label %b14
39
40 b14: ; preds = %b11, %b9, %b3
41 %v15 = phi i64 [ %v6, %b3 ], [ %v10, %b9 ], [ %v13, %b11 ]
42 ret i64 %v15
43 }
44
45 attributes #0 = { norecurse nounwind readnone sspstrong "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="ppc" }
0 ; RUN: llc -march=ppc32 -relocation-model pic < %s | FileCheck %s
1
2 ; CHECK-LABEL: fred
3 ; CHECK: stwux 1, 1, 0
4 ; Save R31..R29 via R0:
5 ; CHECK: addic 0, 0, -4
6 ; CHECK: stwx 31, 0, 0
7 ; CHECK: addic 0, 0, -4
8 ; CHECK: stwx 30, 0, 0
9 ; CHECK: addic 0, 0, -4
10 ; CHECK: stwx 29, 0, 0
11 ; Set R29 back to the value of R0 from before the updates:
12 ; CHECK: addic 29, 0, 12
13 ; Save CR through R12 using R29 as the stack pointer (aligned base pointer).
14 ; CHECK: mfcr 12
15 ; CHECK: stw 28, -16(29)
16 ; CHECK: stw 12, -20(29)
17
18 target datalayout = "E-m:e-p:32:32-i64:64-n32"
19 target triple = "powerpc-unknown-freebsd"
20
21 ; Function Attrs: norecurse readnone sspstrong
22 define i64 @fred(double %a0) local_unnamed_addr #0 {
23 b1:
24 %v2 = alloca i64, align 128
25 store i64 0, i64* %v2
26 %v3 = fcmp olt double %a0, 0x43E0000000000000
27 br i1 %v3, label %b4, label %b8
28
29 b4: ; preds = %b1
30 %v5 = fcmp olt double %a0, 0xC3E0000000000000
31 %v6 = fptosi double %a0 to i64
32 store i64 %v6, i64* %v2
33 %v7 = select i1 %v5, i64 -9223372036854775808, i64 %v6
34 br label %b15
35
36 b8: ; preds = %b1
37 %v9 = fcmp olt double %a0, 0x43F0000000000000
38 br i1 %v9, label %b10, label %b12
39
40 b10: ; preds = %b8
41 %v11 = fptoui double %a0 to i64
42 br label %b15
43
44 b12: ; preds = %b8
45 %v13 = fcmp ogt double %a0, 0.000000e+00
46 %v14 = sext i1 %v13 to i64
47 br label %b15
48
49 b15: ; preds = %b12, %b10, %b4
50 %v16 = phi i64 [ %v7, %b4 ], [ %v11, %b10 ], [ %v14, %b12 ]
51 %v17 = load i64, i64* %v2
52 %v18 = add i64 %v17, %v16
53 ret i64 %v18
54 }
55
56 attributes #0 = { norecurse readnone sspstrong "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="ppc" }