llvm.org GIT mirror llvm / 98ca4f2
Major calling convention code refactoring. Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 11 years ago
47 changed file(s) with 2222 addition(s) and 2339 deletion(s). Raw diff Collapse all Expand all
171171 return UsedRegs[Reg/32] & (1 << (Reg&31));
172172 }
173173
174 /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,
174 /// AnalyzeFormalArguments - Analyze an array of argument values,
175175 /// incorporating info about the formals into this state.
176 void AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn);
177
178 /// AnalyzeReturn - Analyze the returned values of an ISD::RET node,
176 void AnalyzeFormalArguments(const SmallVectorImpl &Ins,
177 CCAssignFn Fn);
178
179 /// AnalyzeReturn - Analyze the returned values of a return,
179180 /// incorporating info about the result values into this state.
180 void AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn);
181
182 /// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info
183 /// about the passed values into this state.
184 void AnalyzeCallOperands(CallSDNode *TheCall, CCAssignFn Fn);
181 void AnalyzeReturn(const SmallVectorImpl &Outs,
182 CCAssignFn Fn);
183
184 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
185 /// incorporating info about the passed values into this state.
186 void AnalyzeCallOperands(const SmallVectorImpl &Outs,
187 CCAssignFn Fn);
185188
186189 /// AnalyzeCallOperands - Same as above except it takes vectors of types
187190 /// and argument flags.
189192 SmallVectorImpl &Flags,
190193 CCAssignFn Fn);
191194
192 /// AnalyzeCallResult - Analyze the return values of an ISD::CALL node,
195 /// AnalyzeCallResult - Analyze the return values of a call,
193196 /// incorporating info about the passed values into this state.
194 void AnalyzeCallResult(CallSDNode *TheCall, CCAssignFn Fn);
197 void AnalyzeCallResult(const SmallVectorImpl &Ins,
198 CCAssignFn Fn);
195199
196200 /// AnalyzeCallResult - Same as above except it's specialized for calls which
197201 /// produce a single value.
318318 SDValue getExternalSymbol(const char *Sym, DebugLoc dl, MVT VT);
319319 SDValue getTargetExternalSymbol(const char *Sym, MVT VT,
320320 unsigned char TargetFlags = 0);
321 SDValue getArgFlags(ISD::ArgFlagsTy Flags);
322321 SDValue getValueType(MVT);
323322 SDValue getRegister(unsigned Reg, MVT VT);
324323 SDValue getDbgStopPoint(DebugLoc DL, SDValue Root,
459458 SDValue N1, SDValue N2, SDValue N3, SDValue N4,
460459 SDValue N5);
461460
461 /// getStackArgumentTokenFactor - Compute a TokenFactor to force all
462 /// the incoming stack arguments to be loaded from the stack. This is
463 /// used in tail call lowering to protect stack arguments from being
464 /// clobbered.
465 SDValue getStackArgumentTokenFactor(SDValue Chain);
466
462467 SDValue getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src,
463468 SDValue Size, unsigned Align, bool AlwaysInline,
464469 const Value *DstSV, uint64_t DstSVOff,
532537
533538 /// getMergeValues - Create a MERGE_VALUES node from the given operands.
534539 SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl);
535
536 /// getCall - Create a CALL node from the given information.
537 ///
538 SDValue getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs,
539 bool IsTailCall, bool isInreg, SDVTList VTs,
540 const SDValue *Operands, unsigned NumOperands,
541 unsigned NumFixedArgs);
542540
543541 /// getLoad - Loads are not normal binary operators: their result type is not
544542 /// determined by their operands, and they produce a value AND a token chain.
9696 AssertSext, AssertZext,
9797
9898 // Various leaf nodes.
99 BasicBlock, VALUETYPE, ARG_FLAGS, CONDCODE, Register,
99 BasicBlock, VALUETYPE, CONDCODE, Register,
100100 Constant, ConstantFP,
101101 GlobalAddress, GlobalTLSAddress, FrameIndex,
102102 JumpTable, ConstantPool, ExternalSymbol,
178178
179179 // UNDEF - An undefined node
180180 UNDEF,
181
182 /// FORMAL_ARGUMENTS(CHAIN, CC#, ISVARARG, FLAG0, ..., FLAGn) - This node
183 /// represents the formal arguments for a function. CC# is a Constant value
184 /// indicating the calling convention of the function, and ISVARARG is a
185 /// flag that indicates whether the function is varargs or not. This node
186 /// has one result value for each incoming argument, plus one for the output
187 /// chain. It must be custom legalized. See description of CALL node for
188 /// FLAG argument contents explanation.
189 ///
190 FORMAL_ARGUMENTS,
191
192 /// RV1, RV2...RVn, CHAIN = CALL(CHAIN, CALLEE,
193 /// ARG0, FLAG0, ARG1, FLAG1, ... ARGn, FLAGn)
194 /// This node represents a fully general function call, before the legalizer
195 /// runs. This has one result value for each argument / flag pair, plus
196 /// a chain result. It must be custom legalized. Flag argument indicates
197 /// misc. argument attributes. Currently:
198 /// Bit 0 - signness
199 /// Bit 1 - 'inreg' attribute
200 /// Bit 2 - 'sret' attribute
201 /// Bit 4 - 'byval' attribute
202 /// Bit 5 - 'nest' attribute
203 /// Bit 6-9 - alignment of byval structures
204 /// Bit 10-26 - size of byval structures
205 /// Bits 31:27 - argument ABI alignment in the first argument piece and
206 /// alignment '1' in other argument pieces.
207 ///
208 /// CALL nodes use the CallSDNode subclass of SDNode, which
209 /// additionally carries information about the calling convention,
210 /// whether the call is varargs, and if it's marked as a tail call.
211 ///
212 CALL,
213181
214182 // EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
215183 // a Constant, which is required to be operand #1) half of the integer or
513481 // compare, rather than as a combined SetCC node. The operands in order are
514482 // chain, cc, lhs, rhs, block to branch to if condition is true.
515483 BR_CC,
516
517 // RET - Return from function. The first operand is the chain,
518 // and any subsequent operands are pairs of return value and return value
519 // attributes (see CALL for description of attributes) for the function.
520 // This operation can have variable number of operands.
521 RET,
522484
523485 // INLINEASM - Represents an inline asm block. This node always has two
524486 // return values: a chain and a flag result. The inputs are as follows:
22332195 /// getRawBits - Represent the flags as a bunch of bits.
22342196 uint64_t getRawBits() const { return Flags; }
22352197 };
2198
2199 /// InputArg - This struct carries flags and type information about a
2200 /// single incoming (formal) argument or incoming (from the perspective
2201 /// of the caller) return value virtual register.
2202 ///
2203 struct InputArg {
2204 ArgFlagsTy Flags;
2205 MVT VT;
2206 bool Used;
2207
2208 InputArg() : VT(MVT::Other), Used(false) {}
2209 InputArg(ISD::ArgFlagsTy flags, MVT vt, bool used)
2210 : Flags(flags), VT(vt), Used(used) {
2211 assert(VT.isSimple() &&
2212 "InputArg value type must be Simple!");
2213 }
2214 };
2215
2216 /// OutputArg - This struct carries flags and a value for a
2217 /// single outgoing (actual) argument or outgoing (from the perspective
2218 /// of the caller) return value virtual register.
2219 ///
2220 struct OutputArg {
2221 ArgFlagsTy Flags;
2222 SDValue Val;
2223 bool IsFixed;
2224
2225 OutputArg() : IsFixed(false) {}
2226 OutputArg(ISD::ArgFlagsTy flags, SDValue val, bool isfixed)
2227 : Flags(flags), Val(val), IsFixed(isfixed) {
2228 assert(Val.getValueType().isSimple() &&
2229 "OutputArg value type must be Simple!");
2230 }
2231 };
22362232 }
2237
2238 /// ARG_FLAGSSDNode - Leaf node holding parameter flags.
2239 class ARG_FLAGSSDNode : public SDNode {
2240 ISD::ArgFlagsTy TheFlags;
2241 friend class SelectionDAG;
2242 explicit ARG_FLAGSSDNode(ISD::ArgFlagsTy Flags)
2243 : SDNode(ISD::ARG_FLAGS, DebugLoc::getUnknownLoc(),
2244 getSDVTList(MVT::Other)), TheFlags(Flags) {
2245 }
2246 public:
2247 ISD::ArgFlagsTy getArgFlags() const { return TheFlags; }
2248
2249 static bool classof(const ARG_FLAGSSDNode *) { return true; }
2250 static bool classof(const SDNode *N) {
2251 return N->getOpcode() == ISD::ARG_FLAGS;
2252 }
2253 };
2254
2255 /// CallSDNode - Node for calls -- ISD::CALL.
2256 class CallSDNode : public SDNode {
2257 unsigned CallingConv;
2258 bool IsVarArg;
2259 bool IsTailCall;
2260 unsigned NumFixedArgs;
2261 // We might eventually want a full-blown Attributes for the result; that
2262 // will expand the size of the representation. At the moment we only
2263 // need Inreg.
2264 bool Inreg;
2265 friend class SelectionDAG;
2266 CallSDNode(unsigned cc, DebugLoc dl, bool isvararg, bool istailcall,
2267 bool isinreg, SDVTList VTs, const SDValue *Operands,
2268 unsigned numOperands, unsigned numFixedArgs)
2269 : SDNode(ISD::CALL, dl, VTs, Operands, numOperands),
2270 CallingConv(cc), IsVarArg(isvararg), IsTailCall(istailcall),
2271 NumFixedArgs(numFixedArgs), Inreg(isinreg) {}
2272 public:
2273 unsigned getCallingConv() const { return CallingConv; }
2274 unsigned isVarArg() const { return IsVarArg; }
2275 unsigned isTailCall() const { return IsTailCall; }
2276 unsigned isInreg() const { return Inreg; }
2277
2278 /// Set this call to not be marked as a tail call. Normally setter
2279 /// methods in SDNodes are unsafe because it breaks the CSE map,
2280 /// but we don't include the tail call flag for calls so it's ok
2281 /// in this case.
2282 void setNotTailCall() { IsTailCall = false; }
2283
2284 SDValue getChain() const { return getOperand(0); }
2285 SDValue getCallee() const { return getOperand(1); }
2286
2287 unsigned getNumArgs() const { return (getNumOperands() - 2) / 2; }
2288 unsigned getNumFixedArgs() const {
2289 if (isVarArg())
2290 return NumFixedArgs;
2291 else
2292 return getNumArgs();
2293 }
2294 SDValue getArg(unsigned i) const { return getOperand(2+2*i); }
2295 SDValue getArgFlagsVal(unsigned i) const {
2296 return getOperand(3+2*i);
2297 }
2298 ISD::ArgFlagsTy getArgFlags(unsigned i) const {
2299 return cast(getArgFlagsVal(i).getNode())->getArgFlags();
2300 }
2301
2302 unsigned getNumRetVals() const { return getNumValues() - 1; }
2303 MVT getRetValType(unsigned i) const { return getValueType(i); }
2304
2305 static bool classof(const CallSDNode *) { return true; }
2306 static bool classof(const SDNode *N) {
2307 return N->getOpcode() == ISD::CALL;
2308 }
2309 };
23102233
23112234 /// VTSDNode - This class is used to represent MVT's, which are used
23122235 /// to parameterize some operations.
24902413 /// MostAlignedSDNode - The SDNode class with the greatest alignment
24912414 /// requirement.
24922415 ///
2493 typedef ARG_FLAGSSDNode MostAlignedSDNode;
2416 typedef GlobalAddressSDNode MostAlignedSDNode;
24942417
24952418 namespace ISD {
24962419 /// isNormalLoad - Returns true if the specified node is a non-extending
10901090 // the SelectionDAGLowering code knows how to lower these.
10911091 //
10921092
1093 /// LowerArguments - This hook must be implemented to indicate how we should
1094 /// lower the arguments for the specified function, into the specified DAG.
1095 virtual void
1096 LowerArguments(Function &F, SelectionDAG &DAG,
1097 SmallVectorImpl& ArgValues, DebugLoc dl);
1098
1099 /// LowerCallTo - This hook lowers an abstract call to a function into an
1093 /// LowerFormalArguments - This hook must be implemented to lower the
1094 /// incoming (formal) arguments, described by the Ins array, into the
1095 /// specified DAG. The implementation should fill in the InVals array
1096 /// with legal-type argument values, and return the resulting token
1097 /// chain value.
1098 ///
1099 virtual SDValue
1100 LowerFormalArguments(SDValue Chain,
1101 unsigned CallConv, bool isVarArg,
1102 const SmallVectorImpl &Ins,
1103 DebugLoc dl, SelectionDAG &DAG,
1104 SmallVectorImpl &InVals) {
1105 assert(0 && "Not Implemented");
1106 return SDValue(); // this is here to silence compiler errors
1107 }
1108
1109 /// LowerCallTo - This function lowers an abstract call to a function into an
11001110 /// actual call. This returns a pair of operands. The first element is the
11011111 /// return value for the function (if RetTy is not VoidTy). The second
1102 /// element is the outgoing token chain.
1112 /// element is the outgoing token chain. It calls LowerCall to do the actual
1113 /// lowering.
11031114 struct ArgListEntry {
11041115 SDValue Node;
11051116 const Type* Ty;
11151126 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
11161127 };
11171128 typedef std::vector ArgListTy;
1118 virtual std::pair
1129 std::pair
11191130 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
11201131 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1121 unsigned CallingConv, bool isTailCall, SDValue Callee,
1122 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl);
1132 unsigned CallConv, bool isTailCall, bool isReturnValueUsed,
1133 SDValue Callee, ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl);
1134
1135 /// LowerCall - This hook must be implemented to lower calls into the
1136 /// the specified DAG. The outgoing arguments to the call are described
1137 /// by the Outs array, and the values to be returned by the call are
1138 /// described by the Ins array. The implementation should fill in the
1139 /// InVals array with legal-type return values from the call, and return
1140 /// the resulting token chain value.
1141 ///
1142 /// The isTailCall flag here is normative. If it is true, the
1143 /// implementation must emit a tail call. The
1144 /// IsEligibleForTailCallOptimization hook should be used to catch
1145 /// cases that cannot be handled.
1146 ///
1147 virtual SDValue
1148 LowerCall(SDValue Chain, SDValue Callee,
1149 unsigned CallConv, bool isVarArg, bool isTailCall,
1150 const SmallVectorImpl &Outs,
1151 const SmallVectorImpl &Ins,
1152 DebugLoc dl, SelectionDAG &DAG,
1153 SmallVectorImpl &InVals) {
1154 assert(0 && "Not Implemented");
1155 return SDValue(); // this is here to silence compiler errors
1156 }
1157
1158 /// LowerReturn - This hook must be implemented to lower outgoing
1159 /// return values, described by the Outs array, into the specified
1160 /// DAG. The implementation should return the resulting token chain
1161 /// value.
1162 ///
1163 virtual SDValue
1164 LowerReturn(SDValue Chain, unsigned CallConv, bool isVarArg,
1165 const SmallVectorImpl &Outs,
1166 DebugLoc dl, SelectionDAG &DAG) {
1167 assert(0 && "Not Implemented");
1168 return SDValue(); // this is here to silence compiler errors
1169 }
11231170
11241171 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
11251172 /// memcpy. This can be used by targets to provide code sequences for cases
12151262
12161263 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
12171264 /// tail call optimization. Targets which want to do tail call optimization
1218 /// should override this function.
1219 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call,
1220 SDValue Ret,
1221 SelectionDAG &DAG) const {
1265 /// should override this function.
1266 virtual bool
1267 IsEligibleForTailCallOptimization(SDValue Callee,
1268 unsigned CalleeCC,
1269 bool isVarArg,
1270 const SmallVectorImpl &Ins,
1271 SelectionDAG& DAG) const {
1272 // Conservative default: no calls are eligible.
12221273 return false;
12231274 }
1224
1225 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly
1226 /// preceeds the RET node and whether the return uses the result of the node
1227 /// or is a void return. This function can be used by the target to determine
1228 /// eligiblity of tail call optimization.
1229 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret);
12301275
12311276 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
12321277 /// it exists. Skip a possible ISD::TokenFactor.
344344 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
345345 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
346346 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
347 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
348347 def trap : SDNode<"ISD::TRAP" , SDTNone,
349348 [SDNPHasChain, SDNPSideEffect]>;
350349
5656 UsedRegs[Reg/32] |= 1 << (Reg&31);
5757 }
5858
59 /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,
59 /// AnalyzeFormalArguments - Analyze an array of argument values,
6060 /// incorporating info about the formals into this state.
61 void CCState::AnalyzeFormalArguments(SDNode *TheArgs, CCAssignFn Fn) {
62 unsigned NumArgs = TheArgs->getNumValues()-1;
63
61 void
62 CCState::AnalyzeFormalArguments(const SmallVectorImpl &Ins,
63 CCAssignFn Fn) {
64 unsigned NumArgs = Ins.size();
65
6466 for (unsigned i = 0; i != NumArgs; ++i) {
65 MVT ArgVT = TheArgs->getValueType(i);
66 ISD::ArgFlagsTy ArgFlags =
67 cast(TheArgs->getOperand(3+i))->getArgFlags();
67 MVT ArgVT = Ins[i].VT;
68 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
6869 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
6970 #ifndef NDEBUG
7071 cerr << "Formal argument #" << i << " has unhandled type "
7576 }
7677 }
7778
78 /// AnalyzeReturn - Analyze the returned values of an ISD::RET node,
79 /// AnalyzeReturn - Analyze the returned values of a return,
7980 /// incorporating info about the result values into this state.
80 void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) {
81 void CCState::AnalyzeReturn(const SmallVectorImpl &Outs,
82 CCAssignFn Fn) {
8183 // Determine which register each value should be copied into.
82 for (unsigned i = 0, e = TheRet->getNumOperands() / 2; i != e; ++i) {
83 MVT VT = TheRet->getOperand(i*2+1).getValueType();
84 ISD::ArgFlagsTy ArgFlags =
85 cast(TheRet->getOperand(i*2+2))->getArgFlags();
84 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
85 MVT VT = Outs[i].Val.getValueType();
86 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
8687 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
8788 #ifndef NDEBUG
8889 cerr << "Return operand #" << i << " has unhandled type "
9495 }
9596
9697
97 /// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info
98 /// about the passed values into this state.
99 void CCState::AnalyzeCallOperands(CallSDNode *TheCall, CCAssignFn Fn) {
100 unsigned NumOps = TheCall->getNumArgs();
98 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
99 /// incorporating info about the passed values into this state.
100 void CCState::AnalyzeCallOperands(const SmallVectorImpl &Outs,
101 CCAssignFn Fn) {
102 unsigned NumOps = Outs.size();
101103 for (unsigned i = 0; i != NumOps; ++i) {
102 MVT ArgVT = TheCall->getArg(i).getValueType();
103 ISD::ArgFlagsTy ArgFlags = TheCall->getArgFlags(i);
104 MVT ArgVT = Outs[i].Val.getValueType();
105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
104106 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
105107 #ifndef NDEBUG
106108 cerr << "Call operand #" << i << " has unhandled type "
130132 }
131133 }
132134
133 /// AnalyzeCallResult - Analyze the return values of an ISD::CALL node,
135 /// AnalyzeCallResult - Analyze the return values of a call,
134136 /// incorporating info about the passed values into this state.
135 void CCState::AnalyzeCallResult(CallSDNode *TheCall, CCAssignFn Fn) {
136 for (unsigned i = 0, e = TheCall->getNumRetVals(); i != e; ++i) {
137 MVT VT = TheCall->getRetValType(i);
138 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
139 if (TheCall->isInreg())
140 Flags.setInReg();
137 void CCState::AnalyzeCallResult(const SmallVectorImpl &Ins,
138 CCAssignFn Fn) {
139 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
140 MVT VT = Ins[i].VT;
141 ISD::ArgFlagsTy Flags = Ins[i].Flags;
141142 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) {
142143 #ifndef NDEBUG
143144 cerr << "Call result #" << i << " has unhandled type "
822822 // special case should be done as part of making LegalizeDAG non-recursive.
823823 SimpleFinishLegalizing = false;
824824 break;
825 case ISD::CALL:
826 // FIXME: Legalization for calls requires custom-lowering the call before
827 // legalizing the operands! (I haven't looked into precisely why.)
828 SimpleFinishLegalizing = false;
829 break;
830825 case ISD::EXTRACT_ELEMENT:
831826 case ISD::FLT_ROUNDS_:
832827 case ISD::SADDO:
848843 case ISD::TRAMPOLINE:
849844 case ISD::FRAMEADDR:
850845 case ISD::RETURNADDR:
851 case ISD::FORMAL_ARGUMENTS:
852846 // These operations lie about being legal: when they claim to be legal,
853847 // they should actually be custom-lowered.
854848 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
886880 case ISD::BR_JT:
887881 case ISD::BR_CC:
888882 case ISD::BRCOND:
889 case ISD::RET:
890883 // Branches tweak the chain to include LastCALLSEQ_END
891884 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
892885 LastCALLSEQ_END);
950943 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
951944 #endif
952945 llvm_unreachable("Do not know how to legalize this operator!");
953 case ISD::CALL:
954 // The only option for this is to custom lower it.
955 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
956 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
957 // A call within a calling sequence must be legalized to something
958 // other than the normal CALLSEQ_END. Violating this gets Legalize
959 // into an infinite loop.
960 assert ((!IsLegalizingCall ||
961 Node->getOpcode() != ISD::CALL ||
962 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
963 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
964
965 // The number of incoming and outgoing values should match; unless the final
966 // outgoing value is a flag.
967 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
968 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
969 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
970 MVT::Flag)) &&
971 "Lowering call/formal_arguments produced unexpected # results!");
972
973 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
974 // remember that we legalized all of them, so it doesn't get relegalized.
975 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
976 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
977 continue;
978 Tmp1 = LegalizeOp(Tmp3.getValue(i));
979 if (Op.getResNo() == i)
980 Tmp2 = Tmp1;
981 AddLegalizedOperand(SDValue(Node, i), Tmp1);
982 }
983 return Tmp2;
946
984947 case ISD::BUILD_VECTOR:
985948 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
986949 default: llvm_unreachable("This action is not supported yet!");
19041867 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
19051868 std::pair CallInfo =
19061869 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1907 0, CallingConv::C, false, Callee, Args, DAG,
1870 0, CallingConv::C, false,
1871 /*isReturnValueUsed=*/true,
1872 Callee, Args, DAG,
19081873 Node->getDebugLoc());
19091874
19101875 // Legalize the call sequence, starting with the chain. This will advance
23102275 std::pair CallResult =
23112276 TLI.LowerCallTo(Node->getOperand(0), Type::VoidTy,
23122277 false, false, false, false, 0, CallingConv::C, false,
2278 /*isReturnValueUsed=*/true,
23132279 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
23142280 Args, DAG, dl);
23152281 Results.push_back(CallResult.second);
10181018 const Type *RetTy = RetVT.getTypeForMVT();
10191019 std::pair CallInfo =
10201020 TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
1021 false, 0, CallingConv::C, false, Callee, Args, DAG, dl);
1021 false, 0, CallingConv::C, false,
1022 /*isReturnValueUsed=*/true,
1023 Callee, Args, DAG, dl);
10221024 return CallInfo.first;
10231025 }
10241026
1919 // type i8 which must be promoted.
2020 //
2121 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
22 // or operations that happen to take a vector which are custom-lowered like
23 // ISD::CALL; the legalization for such operations never produces nodes
22 // or operations that happen to take a vector which are custom-lowered;
23 // the legalization for such operations never produces nodes
2424 // with illegal types, so it's okay to put off legalizing them until
2525 // SelectionDAG::Legalize runs.
2626 //
365365 case ISD::ExternalSymbol:
366366 llvm_unreachable("Should only be used on nodes with operands");
367367 default: break; // Normal nodes don't need extra info.
368 case ISD::ARG_FLAGS:
369 ID.AddInteger(cast(N)->getArgFlags().getRawBits());
370 break;
371368 case ISD::TargetConstant:
372369 case ISD::Constant:
373370 ID.AddPointer(cast(N)->getConstantIntValue());
427424 else
428425 ID.AddPointer(CP->getConstVal());
429426 ID.AddInteger(CP->getTargetFlags());
430 break;
431 }
432 case ISD::CALL: {
433 const CallSDNode *Call = cast(N);
434 ID.AddInteger(Call->getCallingConv());
435 ID.AddInteger(Call->isVarArg());
436427 break;
437428 }
438429 case ISD::LOAD: {
10971088 return SDValue(E, 0);
10981089 SDNode *N = NodeAllocator.Allocate();
10991090 new (N) BasicBlockSDNode(MBB);
1100 CSEMap.InsertNode(N, IP);
1101 AllNodes.push_back(N);
1102 return SDValue(N, 0);
1103 }
1104
1105 SDValue SelectionDAG::getArgFlags(ISD::ArgFlagsTy Flags) {
1106 FoldingSetNodeID ID;
1107 AddNodeIDNode(ID, ISD::ARG_FLAGS, getVTList(MVT::Other), 0, 0);
1108 ID.AddInteger(Flags.getRawBits());
1109 void *IP = 0;
1110 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
1111 return SDValue(E, 0);
1112 SDNode *N = NodeAllocator.Allocate();
1113 new (N) ARG_FLAGSSDNode(Flags);
11141091 CSEMap.InsertNode(N, IP);
11151092 AllNodes.push_back(N);
11161093 return SDValue(N, 0);
29942971 return getNode(Opcode, DL, VT, Ops, 5);
29952972 }
29962973
2974 /// getStackArgumentTokenFactor - Compute a TokenFactor to force all
2975 /// the incoming stack arguments to be loaded from the stack.
2976 SDValue SelectionDAG::getStackArgumentTokenFactor(SDValue Chain) {
2977 SmallVector ArgChains;
2978
2979 // Include the original chain at the beginning of the list. When this is
2980 // used by target LowerCall hooks, this helps legalize find the
2981 // CALLSEQ_BEGIN node.
2982 ArgChains.push_back(Chain);
2983
2984 // Add a chain value for each stack argument.
2985 for (SDNode::use_iterator U = getEntryNode().getNode()->use_begin(),
2986 UE = getEntryNode().getNode()->use_end(); U != UE; ++U)
2987 if (LoadSDNode *L = dyn_cast(*U))
2988 if (FrameIndexSDNode *FI = dyn_cast(L->getBasePtr()))
2989 if (FI->getIndex() < 0)
2990 ArgChains.push_back(SDValue(L, 1));
2991
2992 // Build a tokenfactor for all the chains.
2993 return getNode(ISD::TokenFactor, Chain.getDebugLoc(), MVT::Other,
2994 &ArgChains[0], ArgChains.size());
2995 }
2996
29972997 /// getMemsetValue - Vectorized representation of the memset value
29982998 /// operand.
29992999 static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG,
33853385 std::pair CallResult =
33863386 TLI.LowerCallTo(Chain, Type::VoidTy,
33873387 false, false, false, false, 0, CallingConv::C, false,
3388 /*isReturnValueUsed=*/false,
33883389 getExternalSymbol(TLI.getLibcallName(RTLIB::MEMCPY),
33893390 TLI.getPointerTy()),
33903391 Args, *this, dl);
34323433 std::pair CallResult =
34333434 TLI.LowerCallTo(Chain, Type::VoidTy,
34343435 false, false, false, false, 0, CallingConv::C, false,
3436 /*isReturnValueUsed=*/false,
34353437 getExternalSymbol(TLI.getLibcallName(RTLIB::MEMMOVE),
34363438 TLI.getPointerTy()),
34373439 Args, *this, dl);
34853487 std::pair CallResult =
34863488 TLI.LowerCallTo(Chain, Type::VoidTy,
34873489 false, false, false, false, 0, CallingConv::C, false,
3490 /*isReturnValueUsed=*/false,
34883491 getExternalSymbol(TLI.getLibcallName(RTLIB::MEMSET),
34893492 TLI.getPointerTy()),
34903493 Args, *this, dl);
36103613 new (N) MemIntrinsicSDNode(Opcode, dl, VTList, Ops, NumOps, MemVT,
36113614 srcValue, SVOff, Align, Vol, ReadMem, WriteMem);
36123615 }
3613 AllNodes.push_back(N);
3614 return SDValue(N, 0);
3615 }
3616
3617 SDValue
3618 SelectionDAG::getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs,
3619 bool IsTailCall, bool IsInreg, SDVTList VTs,
3620 const SDValue *Operands, unsigned NumOperands,
3621 unsigned NumFixedArgs) {
3622 // Do not include isTailCall in the folding set profile.
3623 FoldingSetNodeID ID;
3624 AddNodeIDNode(ID, ISD::CALL, VTs, Operands, NumOperands);
3625 ID.AddInteger(CallingConv);
3626 ID.AddInteger(IsVarArgs);
3627 void *IP = 0;
3628 if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) {
3629 // Instead of including isTailCall in the folding set, we just
3630 // set the flag of the existing node.
3631 if (!IsTailCall)
3632 cast(E)->setNotTailCall();
3633 return SDValue(E, 0);
3634 }
3635 SDNode *N = NodeAllocator.Allocate();
3636 new (N) CallSDNode(CallingConv, dl, IsVarArgs, IsTailCall, IsInreg,
3637 VTs, Operands, NumOperands, NumFixedArgs);
3638 CSEMap.InsertNode(N, IP);
36393616 AllNodes.push_back(N);
36403617 return SDValue(N, 0);
36413618 }
52055182 case ISD::AssertZext: return "AssertZext";
52065183
52075184 case ISD::BasicBlock: return "BasicBlock";
5208 case ISD::ARG_FLAGS: return "ArgFlags";
52095185 case ISD::VALUETYPE: return "ValueType";
52105186 case ISD::Register: return "Register";
52115187
52535229 case ISD::EH_LABEL: return "eh_label";
52545230 case ISD::DECLARE: return "declare";
52555231 case ISD::HANDLENODE: return "handlenode";
5256 case ISD::FORMAL_ARGUMENTS: return "formal_arguments";
5257 case ISD::CALL: return "call";
52585232
52595233 // Unary operators
52605234 case ISD::FABS: return "fabs";
53635337 case ISD::BR_JT: return "br_jt";
53645338 case ISD::BRCOND: return "brcond";
53655339 case ISD::BR_CC: return "br_cc";
5366 case ISD::RET: return "ret";
53675340 case ISD::CALLSEQ_START: return "callseq_start";
53685341 case ISD::CALLSEQ_END: return "callseq_end";
53695342
55655538 OS << "<" << M->MO.getValue() << ":" << M->MO.getOffset() << ">";
55665539 else
55675540 OS << "MO.getOffset() << ">";
5568 } else if (const ARG_FLAGSSDNode *N = dyn_cast(this)) {
5569 OS << N->getArgFlags().getArgFlagsString();
55705541 } else if (const VTSDNode *N = dyn_cast(this)) {
55715542 OS << ":" << N->getVT().getMVTString();
55725543 }
1515 #include "llvm/ADT/BitVector.h"
1616 #include "llvm/ADT/SmallSet.h"
1717 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/Constants.h"
1819 #include "llvm/Constants.h"
1920 #include "llvm/CallingConv.h"
2021 #include "llvm/DerivedTypes.h"
752753 PendingExports.clear();
753754 DAG.clear();
754755 CurDebugLoc = DebugLoc::getUnknownLoc();
756 HasTailCall = false;
755757 }
756758
757759 /// getRoot - Return the current virtual root of the Selection DAG,
933935
934936
935937 void SelectionDAGLowering::visitRet(ReturnInst &I) {
936 if (I.getNumOperands() == 0) {
937 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(),
938 MVT::Other, getControlRoot()));
939 return;
940 }
941
942 SmallVector NewValues;
943 NewValues.push_back(getControlRoot());
938 SDValue Chain = getControlRoot();
939 SmallVector Outs;
944940 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
945941 SmallVector ValueVTs;
946942 ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
987983 else if (F->paramHasAttr(0, Attribute::ZExt))
988984 Flags.setZExt();
989985
990 for (unsigned i = 0; i < NumParts; ++i) {
991 NewValues.push_back(Parts[i]);
992 NewValues.push_back(DAG.getArgFlags(Flags));
993 }
994 }
995 }
996 DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other,
997 &NewValues[0], NewValues.size()));
986 for (unsigned i = 0; i < NumParts; ++i)
987 Outs.push_back(ISD::OutputArg(Flags, Parts[i], /*isfixed=*/true));
988 }
989 }
990
991 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
992 unsigned CallConv = DAG.getMachineFunction().getFunction()->getCallingConv();
993 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
994 Outs, getCurDebugLoc(), DAG);
995 DAG.setRoot(Chain);
998996 }
999997
1000998 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
43454343 }
43464344 }
43474345
4346 /// Test if the given instruction is in a position to be optimized
4347 /// with a tail-call. This roughly means that it's in a block with
4348 /// a return and there's nothing that needs to be scheduled
4349 /// between it and the return.
4350 ///
4351 /// This function only tests target-independent requirements.
4352 /// For target-dependent requirements, a target should override
4353 /// TargetLowering::IsEligibleForTailCallOptimization.
4354 ///
4355 static bool
4356 isInTailCallPosition(const Instruction *I, Attributes RetAttr,
4357 const TargetLowering &TLI) {
4358 const BasicBlock *ExitBB = I->getParent();
4359 const TerminatorInst *Term = ExitBB->getTerminator();
4360 const ReturnInst *Ret = dyn_cast(Term);
4361 const Function *F = ExitBB->getParent();
4362
4363 // The block must end in a return statement or an unreachable.
4364 if (!Ret && !isa(Term)) return false;
4365
4366 // If I will have a chain, make sure no other instruction that will have a
4367 // chain interposes between I and the return.
4368 if (I->mayHaveSideEffects() || I->mayReadFromMemory() ||
4369 !I->isSafeToSpeculativelyExecute())
4370 for (BasicBlock::const_iterator BBI = prior(prior(ExitBB->end())); ;
4371 --BBI) {
4372 if (&*BBI == I)
4373 break;
4374 if (BBI->mayHaveSideEffects() || BBI->mayReadFromMemory() ||
4375 !BBI->isSafeToSpeculativelyExecute())
4376 return false;
4377 }
4378
4379 // If the block ends with a void return or unreachable, it doesn't matter
4380 // what the call's return type is.
4381 if (!Ret || Ret->getNumOperands() == 0) return true;
4382
4383 // Conservatively require the attributes of the call to match those of
4384 // the return.
4385 if (F->getAttributes().getRetAttributes() != RetAttr)
4386 return false;
4387
4388 // Otherwise, make sure the unmodified return value of I is the return value.
4389 for (const Instruction *U = dyn_cast(Ret->getOperand(0)); ;
4390 U = dyn_cast(U->getOperand(0))) {
4391 if (!U)
4392 return false;
4393 if (!U->hasOneUse())
4394 return false;
4395 if (U == I)
4396 break;
4397 // Check for a truly no-op truncate.
4398 if (isa(U) &&
4399 TLI.isTruncateFree(U->getOperand(0)->getType(), U->getType()))
4400 continue;
4401 // Check for a truly no-op bitcast.
4402 if (isa(U) &&
4403 (U->getOperand(0)->getType() == U->getType() ||
4404 (isa(U->getOperand(0)->getType()) &&
4405 isa(U->getType()))))
4406 continue;
4407 // Otherwise it's not a true no-op.
4408 return false;
4409 }
4410
4411 return true;
4412 }
43484413
43494414 void SelectionDAGLowering::LowerCallTo(CallSite CS, SDValue Callee,
4350 bool IsTailCall,
4415 bool isTailCall,
43514416 MachineBasicBlock *LandingPad) {
43524417 const PointerType *PT = cast(CS.getCalledValue()->getType());
43534418 const FunctionType *FTy = cast(PT->getElementType());
43574422 TargetLowering::ArgListTy Args;
43584423 TargetLowering::ArgListEntry Entry;
43594424 Args.reserve(CS.arg_size());
4425 unsigned j = 1;
43604426 for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4361 i != e; ++i) {
4427 i != e; ++i, ++j) {
43624428 SDValue ArgNode = getValue(*i);
43634429 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
43644430
43844450 getControlRoot(), BeginLabel));
43854451 }
43864452
4453 // Check if target-independent constraints permit a tail call here.
4454 // Target-dependent constraints are checked within TLI.LowerCallTo.
4455 if (isTailCall &&
4456 !isInTailCallPosition(CS.getInstruction(),
4457 CS.getAttributes().getRetAttributes(),
4458 TLI))
4459 isTailCall = false;
4460
43874461 std::pair Result =
43884462 TLI.LowerCallTo(getRoot(), CS.getType(),
43894463 CS.paramHasAttr(0, Attribute::SExt),
43904464 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
43914465 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
43924466 CS.getCallingConv(),
4393 IsTailCall && PerformTailCallOpt,
4467 isTailCall,
4468 !CS.getInstruction()->use_empty(),
43944469 Callee, Args, DAG, getCurDebugLoc());
4395 if (CS.getType() != Type::VoidTy)
4470 assert((isTailCall || CS.getType() == Type::VoidTy ||
4471 Result.first.getNode()) &&
4472 "Non-null value expected with non-void non-tail call!");
4473 assert((isTailCall || Result.second.getNode()) &&
4474 "Non-null chain expected with non-tail call!");
4475 assert((Result.second.getNode() || !Result.first.getNode()) &&
4476 "Null value expected with tail call!");
4477 if (Result.first.getNode())
43964478 setValue(CS.getInstruction(), Result.first);
4397 DAG.setRoot(Result.second);
4479 // As a special case, a null chain means that a tail call has
4480 // been emitted and the DAG root is already updated.
4481 if (Result.second.getNode())
4482 DAG.setRoot(Result.second);
4483 else
4484 HasTailCall = true;
43984485
43994486 if (LandingPad && MMI) {
44004487 // Insert a label at the end of the invoke call to mark the try range. This
44834570 else
44844571 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
44854572
4486 LowerCallTo(&I, Callee, I.isTailCall());
4573 // Check if we can potentially perform a tail call. More detailed
4574 // checking is be done within LowerCallTo, after more information
4575 // about the call is known.
4576 bool isTailCall = PerformTailCallOpt && I.isTailCall();
4577
4578 LowerCallTo(&I, Callee, isTailCall);
44874579 }
44884580
44894581
54305522 Entry.Ty = TLI.getTargetData()->getIntPtrType();
54315523 Args.push_back(Entry);
54325524
5525 bool isTailCall = PerformTailCallOpt &&
5526 isInTailCallPosition(&I, Attribute::None, TLI);
54335527 std::pair Result =
54345528 TLI.LowerCallTo(getRoot(), I.getType(), false, false, false, false,
5435 0, CallingConv::C, PerformTailCallOpt,
5529 0, CallingConv::C, isTailCall,
5530 /*isReturnValueUsed=*/true,
54365531 DAG.getExternalSymbol("malloc", IntPtr),
54375532 Args, DAG, getCurDebugLoc());
5438 setValue(&I, Result.first); // Pointers always fit in registers
5439 DAG.setRoot(Result.second);
5533 if (Result.first.getNode())
5534 setValue(&I, Result.first); // Pointers always fit in registers
5535 if (Result.second.getNode())
5536 DAG.setRoot(Result.second);
54405537 }
54415538
54425539 void SelectionDAGLowering::visitFree(FreeInst &I) {
54465543 Entry.Ty = TLI.getTargetData()->getIntPtrType();
54475544 Args.push_back(Entry);
54485545 MVT IntPtr = TLI.getPointerTy();
5546 bool isTailCall = PerformTailCallOpt &&
5547 isInTailCallPosition(&I, Attribute::None, TLI);
54495548 std::pair Result =
54505549 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, false, false,
5451 0, CallingConv::C, PerformTailCallOpt,
5550 0, CallingConv::C, isTailCall,
5551 /*isReturnValueUsed=*/true,
54525552 DAG.getExternalSymbol("free", IntPtr), Args, DAG,
54535553 getCurDebugLoc());
5454 DAG.setRoot(Result.second);
5554 if (Result.second.getNode())
5555 DAG.setRoot(Result.second);
54555556 }
54565557
54575558 void SelectionDAGLowering::visitVAStart(CallInst &I) {
54855586 DAG.getSrcValue(I.getOperand(2))));
54865587 }
54875588
5488 /// TargetLowering::LowerArguments - This is the default LowerArguments
5489 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
5490 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
5491 /// integrated into SDISel.
5492 void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
5493 SmallVectorImpl &ArgValues,
5494 DebugLoc dl) {
5495 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
5496 SmallVector Ops;
5497 Ops.push_back(DAG.getRoot());
5498 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
5499 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
5500
5501 // Add one result value for each formal argument.
5502 SmallVector RetVals;
5503 unsigned j = 1;
5504 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5505 I != E; ++I, ++j) {
5506 SmallVector ValueVTs;
5507 ComputeValueVTs(*this, I->getType(), ValueVTs);
5508 for (unsigned Value = 0, NumValues = ValueVTs.size();
5509 Value != NumValues; ++Value) {
5510 MVT VT = ValueVTs[Value];
5511 const Type *ArgTy = VT.getTypeForMVT();
5512 ISD::ArgFlagsTy Flags;
5513 unsigned OriginalAlignment =
5514 getTargetData()->getABITypeAlignment(ArgTy);
5515
5516 if (F.paramHasAttr(j, Attribute::ZExt))
5517 Flags.setZExt();
5518 if (F.paramHasAttr(j, Attribute::SExt))
5519 Flags.setSExt();
5520 if (F.paramHasAttr(j, Attribute::InReg))
5521 Flags.setInReg();
5522 if (F.paramHasAttr(j, Attribute::StructRet))
5523 Flags.setSRet();
5524 if (F.paramHasAttr(j, Attribute::ByVal)) {
5525 Flags.setByVal();
5526 const PointerType *Ty = cast(I->getType());
5527 const Type *ElementTy = Ty->getElementType();
5528 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5529 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5530 // For ByVal, alignment should be passed from FE. BE will guess if
5531 // this info is not there but there are cases it cannot get right.
5532 if (F.getParamAlignment(j))
5533 FrameAlign = F.getParamAlignment(j);
5534 Flags.setByValAlign(FrameAlign);
5535 Flags.setByValSize(FrameSize);
5536 }
5537 if (F.paramHasAttr(j, Attribute::Nest))
5538 Flags.setNest();
5539 Flags.setOrigAlign(OriginalAlignment);
5540
5541 MVT RegisterVT = getRegisterType(VT);
5542 unsigned NumRegs = getNumRegisters(VT);
5543 for (unsigned i = 0; i != NumRegs; ++i) {
5544 RetVals.push_back(RegisterVT);
5545 ISD::ArgFlagsTy MyFlags = Flags;
5546 if (NumRegs > 1 && i == 0)
5547 MyFlags.setSplit();
5548 // if it isn't first piece, alignment must be 1
5549 else if (i > 0)
5550 MyFlags.setOrigAlign(1);
5551 Ops.push_back(DAG.getArgFlags(MyFlags));
5552 }
5553 }
5554 }
5555
5556 RetVals.push_back(MVT::Other);
5557
5558 // Create the node.
5559 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, dl,
5560 DAG.getVTList(&RetVals[0], RetVals.size()),
5561 &Ops[0], Ops.size()).getNode();
5562
5563 // Prelower FORMAL_ARGUMENTS. This isn't required for functionality, but
5564 // allows exposing the loads that may be part of the argument access to the
5565 // first DAGCombiner pass.
5566 SDValue TmpRes = LowerOperation(SDValue(Result, 0), DAG);
5567
5568 // The number of results should match up, except that the lowered one may have
5569 // an extra flag result.
5570 assert((Result->getNumValues() == TmpRes.getNode()->getNumValues() ||
5571 (Result->getNumValues()+1 == TmpRes.getNode()->getNumValues() &&
5572 TmpRes.getValue(Result->getNumValues()).getValueType() == MVT::Flag))
5573 && "Lowering produced unexpected number of results!");
5574
5575 // The FORMAL_ARGUMENTS node itself is likely no longer needed.
5576 if (Result != TmpRes.getNode() && Result->use_empty()) {
5577 HandleSDNode Dummy(DAG.getRoot());
5578 DAG.RemoveDeadNode(Result);
5579 }
5580
5581 Result = TmpRes.getNode();
5582
5583 unsigned NumArgRegs = Result->getNumValues() - 1;
5584 DAG.setRoot(SDValue(Result, NumArgRegs));
5585
5586 // Set up the return result vector.
5587 unsigned i = 0;
5588 unsigned Idx = 1;
5589 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5590 ++I, ++Idx) {
5591 SmallVector ValueVTs;
5592 ComputeValueVTs(*this, I->getType(), ValueVTs);
5593 for (unsigned Value = 0, NumValues = ValueVTs.size();
5594 Value != NumValues; ++Value) {
5595 MVT VT = ValueVTs[Value];
5596 MVT PartVT = getRegisterType(VT);
5597
5598 unsigned NumParts = getNumRegisters(VT);
5599 SmallVector Parts(NumParts);
5600 for (unsigned j = 0; j != NumParts; ++j)
5601 Parts[j] = SDValue(Result, i++);
5602
5603 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5604 if (F.paramHasAttr(Idx, Attribute::SExt))
5605 AssertOp = ISD::AssertSext;
5606 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5607 AssertOp = ISD::AssertZext;
5608
5609 ArgValues.push_back(getCopyFromParts(DAG, dl, &Parts[0], NumParts,
5610 PartVT, VT, AssertOp));
5611 }
5612 }
5613 assert(i == NumArgRegs && "Argument register count mismatch!");
5614 }
5615
5616
56175589 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5618 /// implementation, which just inserts an ISD::CALL node, which is later custom
5619 /// lowered by the target to something concrete. FIXME: When all targets are
5620 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
5590 /// implementation, which just calls LowerCall.
5591 /// FIXME: When all targets are
5592 /// migrated to using LowerCall, this hook should be integrated into SDISel.
56215593 std::pair
56225594 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
56235595 bool RetSExt, bool RetZExt, bool isVarArg,
56245596 bool isInreg, unsigned NumFixedArgs,
5625 unsigned CallingConv, bool isTailCall,
5597 unsigned CallConv, bool isTailCall,
5598 bool isReturnValueUsed,
56265599 SDValue Callee,
56275600 ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) {
5601
56285602 assert((!isTailCall || PerformTailCallOpt) &&
56295603 "isTailCall set when tail-call optimizations are disabled!");
56305604
5631 SmallVector Ops;
5632 Ops.push_back(Chain); // Op#0 - Chain
5633 Ops.push_back(Callee);
5634
56355605 // Handle all of the outgoing arguments.
5606 SmallVector Outs;
56365607 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
56375608 SmallVector ValueVTs;
56385609 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
56835654
56845655 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, PartVT, ExtendKind);
56855656
5686 for (unsigned i = 0; i != NumParts; ++i) {
5657 for (unsigned j = 0; j != NumParts; ++j) {
56875658 // if it isn't first piece, alignment must be 1
5688 ISD::ArgFlagsTy MyFlags = Flags;
5689 if (NumParts > 1 && i == 0)
5690 MyFlags.setSplit();
5691 else if (i != 0)
5692 MyFlags.setOrigAlign(1);
5693
5694 Ops.push_back(Parts[i]);
5695 Ops.push_back(DAG.getArgFlags(MyFlags));
5696 }
5697 }
5698 }
5699
5700 // Figure out the result value types. We start by making a list of
5701 // the potentially illegal return value types.
5702 SmallVector LoweredRetTys;
5659 ISD::OutputArg MyFlags(Flags, Parts[j], i < NumFixedArgs);
5660 if (NumParts > 1 && j == 0)
5661 MyFlags.Flags.setSplit();
5662 else if (j != 0)
5663 MyFlags.Flags.setOrigAlign(1);
5664
5665 Outs.push_back(MyFlags);
5666 }
5667 }
5668 }
5669
5670 // Handle the incoming return values from the call.
5671 SmallVector Ins;
57035672 SmallVector RetTys;
57045673 ComputeValueVTs(*this, RetTy, RetTys);
5705
5706 // Then we translate that to a list of legal types.
57075674 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
57085675 MVT VT = RetTys[I];
57095676 MVT RegisterVT = getRegisterType(VT);
57105677 unsigned NumRegs = getNumRegisters(VT);
5711 for (unsigned i = 0; i != NumRegs; ++i)
5712 LoweredRetTys.push_back(RegisterVT);
5713 }
5714
5715 LoweredRetTys.push_back(MVT::Other); // Always has a chain.
5716
5717 // Create the CALL node.
5718 SDValue Res = DAG.getCall(CallingConv, dl,
5719 isVarArg, isTailCall, isInreg,
5720 DAG.getVTList(&LoweredRetTys[0],
5721 LoweredRetTys.size()),
5722 &Ops[0], Ops.size(), NumFixedArgs
5723 );
5724 Chain = Res.getValue(LoweredRetTys.size() - 1);
5725
5726 // Gather up the call result into a single value.
5727 if (RetTy != Type::VoidTy && !RetTys.empty()) {
5728 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5729
5730 if (RetSExt)
5731 AssertOp = ISD::AssertSext;
5732 else if (RetZExt)
5733 AssertOp = ISD::AssertZext;
5734
5735 SmallVector ReturnValues;
5736 unsigned RegNo = 0;
5737 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5738 MVT VT = RetTys[I];
5739 MVT RegisterVT = getRegisterType(VT);
5740 unsigned NumRegs = getNumRegisters(VT);
5741 unsigned RegNoEnd = NumRegs + RegNo;
5742 SmallVector Results;
5743 for (; RegNo != RegNoEnd; ++RegNo)
5744 Results.push_back(Res.getValue(RegNo));
5745 SDValue ReturnValue =
5746 getCopyFromParts(DAG, dl, &Results[0], NumRegs, RegisterVT, VT,
5747 AssertOp);
5748 ReturnValues.push_back(ReturnValue);
5749 }
5750 Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5751 DAG.getVTList(&RetTys[0], RetTys.size()),
5752 &ReturnValues[0], ReturnValues.size());
5753 }
5678 for (unsigned i = 0; i != NumRegs; ++i) {
5679 ISD::InputArg MyFlags;
5680 MyFlags.VT = RegisterVT;
5681 MyFlags.Used = isReturnValueUsed;
5682 if (RetSExt)
5683 MyFlags.Flags.setSExt();
5684 if (RetZExt)
5685 MyFlags.Flags.setZExt();
5686 if (isInreg)
5687 MyFlags.Flags.setInReg();
5688 Ins.push_back(MyFlags);
5689 }
5690 }
5691
5692 // Check if target-dependent constraints permit a tail call here.
5693 // Target-independent constraints should be checked by the caller.
5694 if (isTailCall &&
5695 !IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, Ins, DAG))
5696 isTailCall = false;
5697
5698 SmallVector InVals;
5699 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5700 Outs, Ins, dl, DAG, InVals);
5701 assert((!isTailCall || InVals.empty()) && "Tail call had return SDValues!");
5702
5703 // For a tail call, the return value is merely live-out and there aren't
5704 // any nodes in the DAG representing it. Return a special value to
5705 // indicate that a tail call has been emitted and no more Instructions
5706 // should be processed in the current block.
5707 if (isTailCall) {
5708 DAG.setRoot(Chain);
5709 return std::make_pair(SDValue(), SDValue());
5710 }
5711
5712 // Collect the legal value parts into potentially illegal values
5713 // that correspond to the original function's return values.
5714 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5715 if (RetSExt)
5716 AssertOp = ISD::AssertSext;
5717 else if (RetZExt)
5718 AssertOp = ISD::AssertZext;
5719 SmallVector ReturnValues;
5720 unsigned CurReg = 0;
5721 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5722 MVT VT = RetTys[I];
5723 MVT RegisterVT = getRegisterType(VT);
5724 unsigned NumRegs = getNumRegisters(VT);
5725
5726 SDValue ReturnValue =
5727 getCopyFromParts(DAG, dl, &InVals[CurReg], NumRegs, RegisterVT, VT,
5728 AssertOp);
5729 ReturnValues.push_back(ReturnValue);
5730 CurReg += NumRegs;
5731 }
5732
5733 // For a function returning void, there is no return value. We can't create
5734 // such a node, so we just return a null return value in that case. In
5735 // that case, nothing will actualy look at the value.
5736 if (ReturnValues.empty())
5737 return std::make_pair(SDValue(), Chain);
5738
5739 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5740 DAG.getVTList(&RetTys[0], RetTys.size()),
5741 &ReturnValues[0], ReturnValues.size());
57545742
57555743 return std::make_pair(Res, Chain);
57565744 }
57885776 LowerArguments(BasicBlock *LLVMBB) {
57895777 // If this is the entry block, emit arguments.
57905778 Function &F = *LLVMBB->getParent();
5791 SDValue OldRoot = SDL->DAG.getRoot();
5792 SmallVector Args;
5793 TLI.LowerArguments(F, SDL->DAG, Args, SDL->getCurDebugLoc());
5794
5795 unsigned a = 0;
5796 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
5797 AI != E; ++AI) {
5779 SelectionDAG &DAG = SDL->DAG;
5780 SDValue OldRoot = DAG.getRoot();
5781 DebugLoc dl = SDL->getCurDebugLoc();
5782 const TargetData *TD = TLI.getTargetData();
5783
5784 // Set up the incoming argument description vector.
5785 SmallVector Ins;
5786 unsigned Idx = 1;
5787 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
5788 I != E; ++I, ++Idx) {
57985789 SmallVector ValueVTs;
5799 ComputeValueVTs(TLI, AI->getType(), ValueVTs);
5790 ComputeValueVTs(TLI, I->getType(), ValueVTs);
5791 bool isArgValueUsed = !I->use_empty();
5792 for (unsigned Value = 0, NumValues = ValueVTs.size();
5793 Value != NumValues; ++Value) {
5794 MVT VT = ValueVTs[Value];
5795 const Type *ArgTy = VT.getTypeForMVT();
5796 ISD::ArgFlagsTy Flags;
5797 unsigned OriginalAlignment =
5798 TD->getABITypeAlignment(ArgTy);
5799
5800 if (F.paramHasAttr(Idx, Attribute::ZExt))
5801 Flags.setZExt();
5802 if (F.paramHasAttr(Idx, Attribute::SExt))
5803 Flags.setSExt();
5804 if (F.paramHasAttr(Idx, Attribute::InReg))
5805 Flags.setInReg();
5806 if (F.paramHasAttr(Idx, Attribute::StructRet))
5807 Flags.setSRet();
5808 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
5809 Flags.setByVal();
5810 const PointerType *Ty = cast(I->getType());
5811 const Type *ElementTy = Ty->getElementType();
5812 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
5813 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
5814 // For ByVal, alignment should be passed from FE. BE will guess if
5815 // this info is not there but there are cases it cannot get right.
5816 if (F.getParamAlignment(Idx))
5817 FrameAlign = F.getParamAlignment(Idx);
5818 Flags.setByValAlign(FrameAlign);
5819 Flags.setByValSize(FrameSize);
5820 }
5821 if (F.paramHasAttr(Idx, Attribute::Nest))
5822 Flags.setNest();
5823 Flags.setOrigAlign(OriginalAlignment);
5824
5825 MVT RegisterVT = TLI.getRegisterType(VT);
5826 unsigned NumRegs = TLI.getNumRegisters(VT);
5827 for (unsigned i = 0; i != NumRegs; ++i) {
5828 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
5829 if (NumRegs > 1 && i == 0)
5830 MyFlags.Flags.setSplit();
5831 // if it isn't first piece, alignment must be 1
5832 else if (i > 0)
5833 MyFlags.Flags.setOrigAlign(1);
5834 Ins.push_back(MyFlags);
5835 }
5836 }
5837 }
5838
5839 // Call the target to set up the argument values.
5840 SmallVector InVals;
5841 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
5842 F.isVarArg(), Ins,
5843 dl, DAG, InVals);
5844 DAG.setRoot(NewRoot);
5845
5846 // Set up the argument values.
5847 unsigned i = 0;
5848 Idx = 1;
5849 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
5850 ++I, ++Idx) {
5851 SmallVector ArgValues;
5852 SmallVector ValueVTs;
5853 ComputeValueVTs(TLI, I->getType(), ValueVTs);
58005854 unsigned NumValues = ValueVTs.size();
5801 if (!AI->use_empty()) {
5802 SDL->setValue(AI, SDL->DAG.getMergeValues(&Args[a], NumValues,
5803 SDL->getCurDebugLoc()));
5855 for (unsigned Value = 0; Value != NumValues; ++Value) {
5856 MVT VT = ValueVTs[Value];
5857 MVT PartVT = TLI.getRegisterType(VT);
5858 unsigned NumParts = TLI.getNumRegisters(VT);
5859
5860 if (!I->use_empty()) {
5861 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5862 if (F.paramHasAttr(Idx, Attribute::SExt))
5863 AssertOp = ISD::AssertSext;
5864 else if (F.paramHasAttr(Idx, Attribute::ZExt))
5865 AssertOp = ISD::AssertZext;
5866
5867 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], NumParts,
5868 PartVT, VT, AssertOp));
5869 }
5870 i += NumParts;
5871 }
5872 if (!I->use_empty()) {
5873 SDL->setValue(I, DAG.getMergeValues(&ArgValues[0], NumValues,
5874 SDL->getCurDebugLoc()));
58045875 // If this argument is live outside of the entry block, insert a copy from
58055876 // whereever we got it to the vreg that other BB's will reference it as.
5806 SDL->CopyToExportRegsIfNeeded(AI);
5807 }
5808 a += NumValues;
5809 }
5877 SDL->CopyToExportRegsIfNeeded(I);
5878 }
5879 }
5880 assert(i == InVals.size() && "Argument register count mismatch!");
58105881
58115882 // Finally, if the target has anything special to do, allow it to do so.
58125883 // FIXME: this should insert code into the DAG!
362362 /// GFI - Garbage collection metadata for the function.
363363 GCFunctionInfo *GFI;
364364
365 /// HasTailCall - This is set to true if a call in the current
366 /// block has been translated as a tail call. In this case,
367 /// no subsequent DAG nodes should be created.
368 ///
369 bool HasTailCall;
370
365371 LLVMContext *Context;
366372
367373 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
368374 FunctionLoweringInfo &funcinfo,
369375 CodeGenOpt::Level ol)
370376 : CurDebugLoc(DebugLoc::getUnknownLoc()),
371 TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
377 TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
378 HasTailCall(false),
372379 Context(dag.getContext()) {
373380 }
374381
365365 }
366366 }
367367
368 /// IsFixedFrameObjectWithPosOffset - Check if object is a fixed frame object and
369 /// whether object offset >= 0.
370 static bool
371 IsFixedFrameObjectWithPosOffset(MachineFrameInfo *MFI, SDValue Op) {
372 if (!isa(Op)) return false;
373
374 FrameIndexSDNode * FrameIdxNode = dyn_cast(Op);
375 int FrameIdx = FrameIdxNode->getIndex();
376 return MFI->isFixedObjectIndex(FrameIdx) &&
377 MFI->getObjectOffset(FrameIdx) >= 0;
378 }
379
380 /// IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could
381 /// possibly be overwritten when lowering the outgoing arguments in a tail
382 /// call. Currently the implementation of this call is very conservative and
383 /// assumes all arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with
384 /// virtual registers would be overwritten by direct lowering.
385 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDValue Op,
386 MachineFrameInfo *MFI) {
387 RegisterSDNode * OpReg = NULL;
388 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
389 (Op.getOpcode()== ISD::CopyFromReg &&
390 (OpReg = dyn_cast(Op.getOperand(1))) &&
391 (OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) ||
392 (Op.getOpcode() == ISD::LOAD &&
393 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(1))) ||
394 (Op.getOpcode() == ISD::MERGE_VALUES &&
395 Op.getOperand(Op.getResNo()).getOpcode() == ISD::LOAD &&
396 IsFixedFrameObjectWithPosOffset(MFI, Op.getOperand(Op.getResNo()).
397 getOperand(1))))
398 return true;
399 return false;
400 }
401
402 /// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
403 /// DAG and fixes their tailcall attribute operand.
404 static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
405 const TargetLowering& TLI) {
406 SDNode * Ret = NULL;
407 SDValue Terminator = DAG.getRoot();
408
409 // Find RET node.
410 if (Terminator.getOpcode() == ISD::RET) {
411 Ret = Terminator.getNode();
412 }
413
414 // Fix tail call attribute of CALL nodes.
415 for (SelectionDAG::allnodes_iterator BE = DAG.allnodes_begin(),
416 BI = DAG.allnodes_end(); BI != BE; ) {
417 --BI;
418 if (CallSDNode *TheCall = dyn_cast(BI)) {
419 SDValue OpRet(Ret, 0);
420 SDValue OpCall(BI, 0);
421 bool isMarkedTailCall = TheCall->isTailCall();
422 // If CALL node has tail call attribute set to true and the call is not
423 // eligible (no RET or the target rejects) the attribute is fixed to
424 // false. The TargetLowering::IsEligibleForTailCallOptimization function
425 // must correctly identify tail call optimizable calls.
426 if (!isMarkedTailCall) continue;
427 if (Ret==NULL ||
428 !TLI.IsEligibleForTailCallOptimization(TheCall, OpRet, DAG)) {
429 // Not eligible. Mark CALL node as non tail call. Note that we
430 // can modify the call node in place since calls are not CSE'd.
431 TheCall->setNotTailCall();
432 } else {
433 // Look for tail call clobbered arguments. Emit a series of
434 // copyto/copyfrom virtual register nodes to protect them.
435 SmallVector Ops;
436 SDValue Chain = TheCall->getChain(), InFlag;
437 Ops.push_back(Chain);
438 Ops.push_back(TheCall->getCallee());
439 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
440 SDValue Arg = TheCall->getArg(i);
441 bool isByVal = TheCall->getArgFlags(i).isByVal();
442 MachineFunction &MF = DAG.getMachineFunction();
443 MachineFrameInfo *MFI = MF.getFrameInfo();
444 if (!isByVal &&
445 IsPossiblyOverwrittenArgumentOfTailCall(Arg, MFI)) {
446 MVT VT = Arg.getValueType();
447 unsigned VReg = MF.getRegInfo().
448 createVirtualRegister(TLI.getRegClassFor(VT));
449 Chain = DAG.getCopyToReg(Chain, Arg.getDebugLoc(),
450 VReg, Arg, InFlag);
451 InFlag = Chain.getValue(1);
452 Arg = DAG.getCopyFromReg(Chain, Arg.getDebugLoc(),
453 VReg, VT, InFlag);
454 Chain = Arg.getValue(1);
455 InFlag = Arg.getValue(2);
456 }
457 Ops.push_back(Arg);
458 Ops.push_back(TheCall->getArgFlagsVal(i));
459 }
460 // Link in chain of CopyTo/CopyFromReg.
461 Ops[0] = Chain;
462 DAG.UpdateNodeOperands(OpCall, Ops.begin(), Ops.size());
463 }
464 }
465 }
466 }
467
468368 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
469369 BasicBlock::iterator Begin,
470370 BasicBlock::iterator End) {
471371 SDL->setCurrentBasicBlock(BB);
472372
473 // Lower all of the non-terminator instructions.
474 for (BasicBlock::iterator I = Begin; I != End; ++I)
373 // Lower all of the non-terminator instructions. If a call is emitted
374 // as a tail call, cease emitting nodes for this block.
375 for (BasicBlock::iterator I = Begin; I != End && !SDL->HasTailCall; ++I)
475376 if (!isa(I))
476377 SDL->visit(*I);
477378
478 // Ensure that all instructions which are used outside of their defining
479 // blocks are available as virtual registers. Invoke is handled elsewhere.
480 for (BasicBlock::iterator I = Begin; I != End; ++I)
481 if (!isa(I) && !isa(I))
482 SDL->CopyToExportRegsIfNeeded(I);
483
484 // Handle PHI nodes in successor blocks.
485 if (End == LLVMBB->end()) {
486 HandlePHINodesInSuccessorBlocks(LLVMBB);
487
488 // Lower the terminator after the copies are emitted.
489 SDL->visit(*LLVMBB->getTerminator());
379 if (!SDL->HasTailCall) {
380 // Ensure that all instructions which are used outside of their defining
381 // blocks are available as virtual registers. Invoke is handled elsewhere.
382 for (BasicBlock::iterator I = Begin; I != End; ++I)
383 if (!isa(I) && !isa(I))
384 SDL->CopyToExportRegsIfNeeded(I);
385
386 // Handle PHI nodes in successor blocks.
387 if (End == LLVMBB->end()) {
388 HandlePHINodesInSuccessorBlocks(LLVMBB);
389
390 // Lower the terminator after the copies are emitted.
391 SDL->visit(*LLVMBB->getTerminator());
392 }
490393 }
491394
492395 // Make sure the root of the DAG is up-to-date.
493396 CurDAG->setRoot(SDL->getControlRoot());
494
495 // Check whether calls in this block are real tail calls. Fix up CALL nodes
496 // with correct tailcall attribute so that the target can rely on the tailcall
497 // attribute indicating whether the call is really eligible for tail call
498 // optimization.
499 if (PerformTailCallOpt)
500 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI);
501397
502398 // Final step, emit the lowered DAG as machine code.
503399 CodeGenAndEmitDAG();
25832583 DAG.getConstant(magics.s-1, getShiftAmountTy()));
25842584 }
25852585 }
2586
2587 /// IgnoreHarmlessInstructions - Ignore instructions between a CALL and RET
2588 /// node that don't prevent tail call optimization.
2589 static SDValue IgnoreHarmlessInstructions(SDValue node) {
2590 // Found call return.
2591 if (node.getOpcode() == ISD::CALL) return node;
2592 // Ignore MERGE_VALUES. Will have at least one operand.
2593 if (node.getOpcode() == ISD::MERGE_VALUES)
2594 return IgnoreHarmlessInstructions(node.getOperand(0));
2595 // Ignore ANY_EXTEND node.
2596 if (node.getOpcode() == ISD::ANY_EXTEND)
2597 return IgnoreHarmlessInstructions(node.getOperand(0));
2598 if (node.getOpcode() == ISD::TRUNCATE)
2599 return IgnoreHarmlessInstructions(node.getOperand(0));
2600 // Any other node type.
2601 return node;
2602 }
2603
2604 bool TargetLowering::CheckTailCallReturnConstraints(CallSDNode *TheCall,
2605 SDValue Ret) {
2606 unsigned NumOps = Ret.getNumOperands();
2607 // ISD::CALL results:(value0, ..., valuen, chain)
2608 // ISD::RET operands:(chain, value0, flag0, ..., valuen, flagn)
2609 // Value return:
2610 // Check that operand of the RET node sources from the CALL node. The RET node
2611 // has at least two operands. Operand 0 holds the chain. Operand 1 holds the
2612 // value.
2613 // Also we need to check that there is no code in between the call and the
2614 // return. Hence we also check that the incomming chain to the return sources
2615 // from the outgoing chain of the call.
2616 if (NumOps > 1 &&
2617 IgnoreHarmlessInstructions(Ret.getOperand(1)) == SDValue(TheCall,0) &&
2618 Ret.getOperand(0) == SDValue(TheCall, TheCall->getNumValues()-1))
2619 return true;
2620 // void return: The RET node has the chain result value of the CALL node as
2621 // input.
2622 if (NumOps == 1 &&
2623 Ret.getOperand(0) == SDValue(TheCall, TheCall->getNumValues()-1))
2624 return true;
2625
2626 return false;
2627 }
294294 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
295295 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
296296
297 setOperationAction(ISD::RET, MVT::Other, Custom);
298297 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
299298 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
300299 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
530529
531530 //===----------------------------------------------------------------------===//
532531 // Calling Convention Implementation
533 //
534 // The lower operations present on calling convention works on this order:
535 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
536 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
537 // LowerRET (virt regs --> phys regs)
538 // LowerCALL (phys regs --> virt regs)
539 //
540532 //===----------------------------------------------------------------------===//
541533
542534 #include "ARMGenCallingConv.inc"
693685 }
694686 }
695687
696 /// LowerCallResult - Lower the result values of an ISD::CALL into the
697 /// appropriate copies out of appropriate physical registers. This assumes that
698 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
699 /// being lowered. The returns a SDNode with the same number of values as the
700 /// ISD::CALL.
701 SDNode *ARMTargetLowering::
702 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
703 unsigned CallingConv, SelectionDAG &DAG) {
704
705 DebugLoc dl = TheCall->getDebugLoc();
688 /// LowerCallResult - Lower the result values of a call into the
689 /// appropriate copies out of appropriate physical registers.
690 SDValue
691 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
692 unsigned CallConv, bool isVarArg,
693 const SmallVectorImpl &Ins,
694 DebugLoc dl, SelectionDAG &DAG,
695 SmallVectorImpl &InVals) {
696
706697 // Assign locations to each value returned by this call.
707698 SmallVector RVLocs;
708 bool isVarArg = TheCall->isVarArg();
709 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
699 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
710700 RVLocs, *DAG.getContext());
711 CCInfo.AnalyzeCallResult(TheCall,
712 CCAssignFnForNode(CallingConv, /* Return*/ true));
713
714 SmallVector ResultVals;
701 CCInfo.AnalyzeCallResult(Ins,
702 CCAssignFnForNode(CallConv, /* Return*/ true));
715703
716704 // Copy all of the result registers out of their specified physreg.
717705 for (unsigned i = 0; i != RVLocs.size(); ++i) {
763751 break;
764752 }
765753
766 ResultVals.push_back(Val);
767 }
768
769 // Merge everything together with a MERGE_VALUES node.
770 ResultVals.push_back(Chain);
771 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
772 &ResultVals[0], ResultVals.size()).getNode();
754 InVals.push_back(Val);
755 }
756
757 return Chain;
773758 }
774759
775760 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
789774
790775 /// LowerMemOpCallTo - Store the argument to the stack.
791776 SDValue
792 ARMTargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
793 const SDValue &StackPtr,
794 const CCValAssign &VA, SDValue Chain,
795 SDValue Arg, ISD::ArgFlagsTy Flags) {
796 DebugLoc dl = TheCall->getDebugLoc();
777 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
778 SDValue StackPtr, SDValue Arg,
779 DebugLoc dl, SelectionDAG &DAG,
780 const CCValAssign &VA,
781 ISD::ArgFlagsTy Flags) {
797782 unsigned LocMemOffset = VA.getLocMemOffset();
798783 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
799784 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
804789 PseudoSourceValue::getStack(), LocMemOffset);
805790 }
806791
807 void ARMTargetLowering::PassF64ArgInRegs(CallSDNode *TheCall, SelectionDAG &DAG,
792 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
808793 SDValue Chain, SDValue &Arg,
809794 RegsToPassVector &RegsToPass,
810795 CCValAssign &VA, CCValAssign &NextVA,
811796 SDValue &StackPtr,
812797 SmallVector &MemOpChains,
813798 ISD::ArgFlagsTy Flags) {
814 DebugLoc dl = TheCall->getDebugLoc();
815799
816800 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
817801 DAG.getVTList(MVT::i32, MVT::i32), Arg);
824808 if (StackPtr.getNode() == 0)
825809 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
826810
827 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, NextVA,
828 Chain, fmrrd.getValue(1), Flags));
829 }
830 }
831
832 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
811 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
812 dl, DAG, NextVA,
813 Flags));
814 }
815 }
816
817 /// LowerCall - Lowering a call into a callseq_start <-
833818 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
834819 /// nodes.
835 SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
836 CallSDNode *TheCall = cast(Op.getNode());
837 MVT RetVT = TheCall->getRetValType(0);
838 SDValue Chain = TheCall->getChain();
839 unsigned CC = TheCall->getCallingConv();
840 bool isVarArg = TheCall->isVarArg();
841 SDValue Callee = TheCall->getCallee();
842 DebugLoc dl = TheCall->getDebugLoc();
820 SDValue
821 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
822 unsigned CallConv, bool isVarArg,
823 bool isTailCall,
824 const SmallVectorImpl &Outs,
825 const SmallVectorImpl &Ins,
826 DebugLoc dl, SelectionDAG &DAG,
827 SmallVectorImpl &InVals) {
843828
844829 // Analyze operands of the call, assigning locations to each operand.
845830 SmallVector ArgLocs;
846 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
847 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC, /* Return*/ false));
831 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
832 *DAG.getContext());
833 CCInfo.AnalyzeCallOperands(Outs,
834 CCAssignFnForNode(CallConv, /* Return*/ false));
848835
849836 // Get a count of how many bytes are to be pushed on the stack.
850837 unsigned NumBytes = CCInfo.getNextStackOffset();
864851 i != e;
865852 ++i, ++realArgIdx) {
866853 CCValAssign &VA = ArgLocs[i];
867 SDValue Arg = TheCall->getArg(realArgIdx);
868 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(realArgIdx);
854 SDValue Arg = Outs[realArgIdx].Val;
855 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
869856
870857 // Promote the value if needed.
871858 switch (VA.getLocInfo()) {
893880 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
894881 DAG.getConstant(1, MVT::i32));
895882
896 PassF64ArgInRegs(TheCall, DAG, Chain, Op0, RegsToPass,
883 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
897884 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
898885
899886 VA = ArgLocs[++i]; // skip ahead to next loc
900887 if (VA.isRegLoc()) {
901 PassF64ArgInRegs(TheCall, DAG, Chain, Op1, RegsToPass,
888 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
902889 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
903890 } else {
904891 assert(VA.isMemLoc());
905892 if (StackPtr.getNode() == 0)
906893 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
907894
908 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
909 Chain, Op1, Flags));
895 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
896 dl, DAG, VA, Flags));
910897 }
911898 } else {
912 PassF64ArgInRegs(TheCall, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
899 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
913900 StackPtr, MemOpChains, Flags);
914901 }
915902 } else if (VA.isRegLoc()) {
919906 if (StackPtr.getNode() == 0)
920907 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
921908
922 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
923 Chain, Arg, Flags));
909 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
910 dl, DAG, VA, Flags));
924911 }
925912 }
926913
10231010
10241011 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
10251012 DAG.getIntPtrConstant(0, true), InFlag);
1026 if (RetVT != MVT::Other)
1013 if (!Ins.empty())
10271014 InFlag = Chain.getValue(1);
10281015
10291016 // Handle result values, copying them out of physregs into vregs that we
10301017 // return.
1031 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1032 Op.getResNo());
1033 }
1034
1035 SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
1036 // The chain is always operand #0
1037 SDValue Chain = Op.getOperand(0);
1038 DebugLoc dl = Op.getDebugLoc();
1018 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1019 dl, DAG, InVals);
1020 }
1021
1022 SDValue
1023 ARMTargetLowering::LowerReturn(SDValue Chain,
1024 unsigned CallConv, bool isVarArg,
1025 const SmallVectorImpl &Outs,
1026 DebugLoc dl, SelectionDAG &DAG) {
10391027
10401028 // CCValAssign - represent the assignment of the return value to a location.
10411029 SmallVector RVLocs;
1042 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1043 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
10441030
10451031 // CCState - Info about the registers and stack slots.
1046 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, *DAG.getContext());
1047
1048 // Analyze return values of ISD::RET.
1049 CCInfo.AnalyzeReturn(Op.getNode(), CCAssignFnForNode(CC, /* Return */ true));
1032 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1033 *DAG.getContext());
1034
1035 // Analyze outgoing return values.
1036 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true));
10501037
10511038 // If this is the first return lowered for this function, add
10521039 // the regs to the liveout set for the function.
10651052 CCValAssign &VA = RVLocs[i];
10661053 assert(VA.isRegLoc() && "Can only return in registers!");
10671054
1068 // ISD::RET => ret chain, (regnum1,val1), ...
1069 // So i*2+1 index only the regnums
1070 SDValue Arg = Op.getOperand(realRVLocIdx*2+1);
1055 SDValue Arg = Outs[realRVLocIdx].Val;
10711056
10721057 switch (VA.getLocInfo()) {
10731058 default: llvm_unreachable("Unknown loc info!");
11711156 // FIXME: is there useful debug info available here?
11721157 std::pair CallResult =
11731158 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
1174 0, CallingConv::C, false,
1159 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
11751160 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
11761161 return CallResult.first;
11771162 }
14191404 }
14201405
14211406 SDValue
1422 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1407 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1408 unsigned CallConv, bool isVarArg,
1409 const SmallVectorImpl
1410 &Ins,
1411 DebugLoc dl, SelectionDAG &DAG,
1412 SmallVectorImpl &InVals) {
1413
14231414 MachineFunction &MF = DAG.getMachineFunction();
14241415 MachineFrameInfo *MFI = MF.getFrameInfo();
14251416
1426 SDValue Root = Op.getOperand(0);
1427 DebugLoc dl = Op.getDebugLoc();
1428 bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0;
1429 unsigned CC = MF.getFunction()->getCallingConv();
14301417 ARMFunctionInfo *AFI = MF.getInfo();
14311418
14321419 // Assign locations to all of the incoming arguments.
14331420 SmallVector ArgLocs;
1434 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
1435 CCInfo.AnalyzeFormalArguments(Op.getNode(),
1436 CCAssignFnForNode(CC, /* Return*/ false));
1421 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1422 *DAG.getContext());
1423 CCInfo.AnalyzeFormalArguments(Ins,
1424 CCAssignFnForNode(CallConv, /* Return*/ false));
14371425
14381426 SmallVector ArgValues;
14391427
14521440
14531441 if (VA.getLocVT() == MVT::v2f64) {
14541442 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1455 Root, DAG, dl);
1443 Chain, DAG, dl);
14561444 VA = ArgLocs[++i]; // skip ahead to next loc
14571445 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1458 Root, DAG, dl);
1446 Chain, DAG, dl);
14591447 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
14601448 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
14611449 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
14621450 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
14631451 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
14641452 } else
1465 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Root, DAG, dl);
1453 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
14661454
14671455 } else {
14681456 TargetRegisterClass *RC;
14771465
14781466 assert((RegVT == MVT::i32 || RegVT == MVT::f32 ||
14791467 (FloatABIType == FloatABI::Hard && RegVT == MVT::f64)) &&
1480 "RegVT not supported by FORMAL_ARGUMENTS Lowering");
1468 "RegVT not supported by formal arguments Lowering");
14811469
14821470 // Transform the arguments in physical registers into virtual ones.
14831471 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1484 ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1472 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
14851473 }
14861474
14871475 // If this is an 8 or 16-bit value, it is really passed promoted
15051493 break;
15061494 }
15071495
1508 ArgValues.push_back(ArgValue);
1496 InVals.push_back(ArgValue);
15091497
15101498 } else { // VA.isRegLoc()
15111499
15181506
15191507 // Create load nodes to retrieve arguments from the stack.
15201508 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1521 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1509 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
15221510 }
15231511 }
15241512
15541542 RC = ARM::GPRRegisterClass;
15551543
15561544 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1557 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1545 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
15581546 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
15591547 MemOps.push_back(Store);
15601548 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
15611549 DAG.getConstant(4, getPointerTy()));
15621550 }
15631551 if (!MemOps.empty())
1564 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1565 &MemOps[0], MemOps.size());
1552 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1553 &MemOps[0], MemOps.size());
15661554 } else
15671555 // This will point to the next argument passed via stack.
15681556 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
15691557 }
15701558
1571 ArgValues.push_back(Root);
1572
1573 // Return the new list of results.
1574 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1575 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1559 return Chain;
15761560 }
15771561
15781562 /// isFloatingPointZero - Return true if this is +0.0.
23792363 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
23802364 LowerGlobalAddressELF(Op, DAG);
23812365 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2382 case ISD::CALL: return LowerCALL(Op, DAG);
2383 case ISD::RET: return LowerRET(Op, DAG);
23842366 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
23852367 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
23862368 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
23902372 case ISD::FP_TO_SINT:
23912373 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
23922374 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
2393 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
23942375 case ISD::RETURNADDR: break;
23952376 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
23962377 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
224224 void addQRTypeForNEON(MVT VT);
225225
226226 typedef SmallVector, 8> RegsToPassVector;
227 void PassF64ArgInRegs(CallSDNode *TheCall, SelectionDAG &DAG,
227 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
228228 SDValue Chain, SDValue &Arg,
229229 RegsToPassVector &RegsToPass,
230230 CCValAssign &VA, CCValAssign &NextVA,
235235 SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
236236
237237 CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return) const;
238 SDValue LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
239 const SDValue &StackPtr, const CCValAssign &VA,
240 SDValue Chain, SDValue Arg, ISD::ArgFlagsTy Flags);
241 SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
242 unsigned CallingConv, SelectionDAG &DAG);
243 SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
238 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
239 DebugLoc dl, SelectionDAG &DAG,
240 const CCValAssign &VA,
241 ISD::ArgFlagsTy Flags);
244242 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
245243 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
246 SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
247244 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
248245 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
249246 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
252249 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
253250 SelectionDAG &DAG);
254251 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
255 SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
256252 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
257253 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
258254
263259 bool AlwaysInline,
264260 const Value *DstSV, uint64_t DstSVOff,
265261 const Value *SrcSV, uint64_t SrcSVOff);
262 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
263 unsigned CallConv, bool isVarArg,
264 const SmallVectorImpl &Ins,
265 DebugLoc dl, SelectionDAG &DAG,
266 SmallVectorImpl &InVals);
267
268 virtual SDValue
269 LowerFormalArguments(SDValue Chain,
270 unsigned CallConv, bool isVarArg,
271 const SmallVectorImpl &Ins,
272 DebugLoc dl, SelectionDAG &DAG,
273 SmallVectorImpl &InVals);
274
275 virtual SDValue
276 LowerCall(SDValue Chain, SDValue Callee,
277 unsigned CallConv, bool isVarArg,
278 bool isTailCall,
279 const SmallVectorImpl &Outs,
280 const SmallVectorImpl &Ins,
281 DebugLoc dl, SelectionDAG &DAG,
282 SmallVectorImpl &InVals);
283
284 virtual SDValue
285 LowerReturn(SDValue Chain,
286 unsigned CallConv, bool isVarArg,
287 const SmallVectorImpl &Outs,
288 DebugLoc dl, SelectionDAG &DAG);
266289 };
267290 }
268291
165165 setOperationAction(ISD::VAARG, MVT::Other, Custom);
166166 setOperationAction(ISD::VAARG, MVT::i32, Custom);
167167
168 setOperationAction(ISD::RET, MVT::Other, Custom);
169
170168 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
171169 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
172170
245243
246244 #include "AlphaGenCallingConv.inc"
247245
248 SDValue AlphaTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
249 CallSDNode *TheCall = cast(Op.getNode());
250 SDValue Chain = TheCall->getChain();
251 SDValue Callee = TheCall->getCallee();
252 bool isVarArg = TheCall->isVarArg();
253 DebugLoc dl = Op.getDebugLoc();
254 MachineFunction &MF = DAG.getMachineFunction();
255 unsigned CC = MF.getFunction()->getCallingConv();
246 SDValue
247 AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
248 unsigned CallConv, bool isVarArg,
249 bool isTailCall,
250 const SmallVectorImpl &Outs,
251 const SmallVectorImpl &Ins,
252 DebugLoc dl, SelectionDAG &DAG,
253 SmallVectorImpl &InVals) {
256254
257255 // Analyze operands of the call, assigning locations to each operand.
258256 SmallVector ArgLocs;
259 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
260
261 CCInfo.AnalyzeCallOperands(TheCall, CC_Alpha);
257 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
258 ArgLocs, *DAG.getContext());
259
260 CCInfo.AnalyzeCallOperands(Outs, CC_Alpha);
262261
263262 // Get a count of how many bytes are to be pushed on the stack.
264263 unsigned NumBytes = CCInfo.getNextStackOffset();
274273 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
275274 CCValAssign &VA = ArgLocs[i];
276275
277 // Arguments start after the 5 first operands of ISD::CALL
278 SDValue Arg = TheCall->getArg(i);
276 SDValue Arg = Outs[i].Val;
279277
280278 // Promote the value if needed.
281279 switch (VA.getLocInfo()) {
354352
355353 // Handle result values, copying them out of physregs into vregs that we
356354 // return.
357 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
358 Op.getResNo());
359 }
360
361 /// LowerCallResult - Lower the result values of an ISD::CALL into the
362 /// appropriate copies out of appropriate physical registers. This assumes that
363 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
364 /// being lowered. Returns a SDNode with the same number of values as the
365 /// ISD::CALL.
366 SDNode*
355 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
356 Ins, dl, DAG, InVals);
357 }
358
359 /// LowerCallResult - Lower the result values of a call into the
360 /// appropriate copies out of appropriate physical registers.
361 ///
362 SDValue
367363 AlphaTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
368 CallSDNode *TheCall,
369 unsigned CallingConv,
370 SelectionDAG &DAG) {
371 bool isVarArg = TheCall->isVarArg();
372 DebugLoc dl = TheCall->getDebugLoc();
364 unsigned CallConv, bool isVarArg,
365 const SmallVectorImpl &Ins,
366 DebugLoc dl, SelectionDAG &DAG,
367 SmallVectorImpl &InVals) {
373368
374369 // Assign locations to each value returned by this call.
375370 SmallVector RVLocs;
376 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs,
371 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
377372 *DAG.getContext());
378373
379 CCInfo.AnalyzeCallResult(TheCall, RetCC_Alpha);
380 SmallVector ResultVals;
374 CCInfo.AnalyzeCallResult(Ins, RetCC_Alpha);
381375
382376 // Copy all of the result registers out of their specified physreg.
383377 for (unsigned i = 0; i != RVLocs.size(); ++i) {
401395 if (VA.getLocInfo() != CCValAssign::Full)
402396 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
403397
404 ResultVals.push_back(RetValue);
405 }
406
407 ResultVals.push_back(Chain);
408
409 // Merge everything together with a MERGE_VALUES node.
410 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
411 &ResultVals[0], ResultVals.size()).getNode();
412 }
413
414 static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
415 int &VarArgsBase,
416 int &VarArgsOffset) {
398 InVals.push_back(RetValue);
399 }
400
401 return Chain;
402 }
403
404 SDValue
405 AlphaTargetLowering::LowerFormalArguments(SDValue Chain,
406 unsigned CallConv, bool isVarArg,
407 const SmallVectorImpl
408 &Ins,
409 DebugLoc dl, SelectionDAG &DAG,
410 SmallVectorImpl &InVals) {
411
417412 MachineFunction &MF = DAG.getMachineFunction();
418413 MachineFrameInfo *MFI = MF.getFrameInfo();
419 std::vector ArgValues;
420 SDValue Root = Op.getOperand(0);
421 DebugLoc dl = Op.getDebugLoc();
422414
423415 unsigned args_int[] = {
424416 Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
425417 unsigned args_float[] = {
426418 Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
427419
428 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) {
420 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
429421 SDValue argt;
430 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
422 MVT ObjectVT = Ins[ArgNo].VT;
431423 SDValue ArgVal;
432424
433425 if (ArgNo < 6) {
437429 case MVT::f64:
438430 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
439431 &Alpha::F8RCRegClass);
440 ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT);
432 ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
441433 break;
442434 case MVT::f32:
443435 args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
444436 &Alpha::F4RCRegClass);
445 ArgVal = DAG.getCopyFromReg(Root, dl, args_float[ArgNo], ObjectVT);
437 ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
446438 break;
447439 case MVT::i64:
448440 args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
449441 &Alpha::GPRCRegClass);
450 ArgVal = DAG.getCopyFromReg(Root, dl, args_int[ArgNo], MVT::i64);
442 ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], MVT::i64);
451443 break;
452444 }
453445 } else { //more args
457449 // Create the SelectionDAG nodes corresponding to a load
458450 //from this parameter
459451 SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
460 ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
461 }
462 ArgValues.push_back(ArgVal);
452 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0);
453 }
454 InVals.push_back(ArgVal);
463455 }
464456
465457 // If the functions takes variable number of arguments, copy all regs to stack
466 bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0;
467458 if (isVarArg) {
468 VarArgsOffset = (Op.getNode()->getNumValues()-1) * 8;
459 VarArgsOffset = Ins.size() * 8;
469460 std::vector LS;
470461 for (int i = 0; i < 6; ++i) {
471462 if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
472463 args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
473 SDValue argt = DAG.getCopyFromReg(Root, dl, args_int[i], MVT::i64);
464 SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], MVT::i64);
474465 int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
475466 if (i == 0) VarArgsBase = FI;
476467 SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
477 LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0));
468 LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0));
478469
479470 if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
480471 args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
481 argt = DAG.getCopyFromReg(Root, dl, args_float[i], MVT::f64);
472 argt = DAG.getCopyFromReg(Chain, dl, args_float[i], MVT::f64);
482473 FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
483474 SDFI = DAG.getFrameIndex(FI, MVT::i64);
484 LS.push_back(DAG.getStore(Root, dl, argt, SDFI, NULL, 0));
475 LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0));
485476 }
486477
487478 //Set up a token factor with all the stack traffic
488 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size());
489 }
490
491 ArgValues.push_back(Root);
492
493 // Return the new list of results.
494 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
495 &ArgValues[0], ArgValues.size());
496 }
497
498 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
499 DebugLoc dl = Op.getDebugLoc();
500 SDValue Copy = DAG.getCopyToReg(Op.getOperand(0), dl, Alpha::R26,
501 DAG.getNode(AlphaISD::GlobalRetAddr,
502 DebugLoc::getUnknownLoc(),
503 MVT::i64),
504 SDValue());
505 switch (Op.getNumOperands()) {
479 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size());
480 }
481
482 return Chain;
483 }
484
485 SDValue
486 AlphaTargetLowering::LowerReturn(SDValue Chain,
487 unsigned CallConv, bool isVarArg,
488 const SmallVectorImpl &Outs,
489 DebugLoc dl, SelectionDAG &DAG) {
490
491 SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
492 DAG.getNode(AlphaISD::GlobalRetAddr,
493 DebugLoc::getUnknownLoc(),
494 MVT::i64),
495 SDValue());
496 switch (Outs.size()) {
506497 default:
507498 llvm_unreachable("Do not know how to return this many arguments!");
508 case 1:
499 case 0:
509500 break;
510501 //return SDValue(); // ret void is legal
511 case 3: {
512 MVT ArgVT = Op.getOperand(1).getValueType();
502 case 1: {
503 MVT ArgVT = Outs[0].Val.getValueType();
513504 unsigned ArgReg;
514505 if (ArgVT.isInteger())
515506 ArgReg = Alpha::R0;
518509 ArgReg = Alpha::F0;
519510 }
520511 Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
521 Op.getOperand(1), Copy.getValue(1));
512 Outs[0].Val, Copy.getValue(1));
522513 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
523514 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
524515 break;
525516 }
526 case 5: {
527 MVT ArgVT = Op.getOperand(1).getValueType();
517 case 2: {
518 MVT ArgVT = Outs[0].Val.getValueType();
528519 unsigned ArgReg1, ArgReg2;
529520 if (ArgVT.isInteger()) {
530521 ArgReg1 = Alpha::R0;
535526 ArgReg2 = Alpha::F1;
536527 }
537528 Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
538 Op.getOperand(1), Copy.getValue(1));
529 Outs[0].Val, Copy.getValue(1));
539530 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
540531 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
541532 == DAG.getMachineFunction().getRegInfo().liveout_end())
542533 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
543534 Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
544 Op.getOperand(3), Copy.getValue(1));
535 Outs[1].Val, Copy.getValue(1));
545536 if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
546537 DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
547538 == DAG.getMachineFunction().getRegInfo().liveout_end())
588579 DebugLoc dl = Op.getDebugLoc();
589580 switch (Op.getOpcode()) {
590581 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
591 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
592 VarArgsBase,
593 VarArgsOffset);
594 case ISD::CALL: return LowerCALL(Op, DAG);
595 case ISD::RET: return LowerRET(Op,DAG);
596582 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
597583
598584 case ISD::INTRINSIC_WO_CHAIN: {
8181 // Friendly names for dumps
8282 const char *getTargetNodeName(unsigned Opcode) const;
8383
84 SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
85 SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
86 unsigned CallingConv, SelectionDAG &DAG);
84 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
85 unsigned CallConv, bool isVarArg,
86 const SmallVectorImpl &Ins,
87 DebugLoc dl, SelectionDAG &DAG,
88 SmallVectorImpl &InVals);
8789
8890 ConstraintType getConstraintType(const std::string &Constraint) const;
8991
106108 void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
107109 SelectionDAG &DAG);
108110
111 virtual SDValue
112 LowerFormalArguments(SDValue Chain,
113 unsigned CallConv, bool isVarArg,
114 const SmallVectorImpl &Ins,
115 DebugLoc dl, SelectionDAG &DAG,
116 SmallVectorImpl &InVals);
117
118 virtual SDValue
119 LowerCall(SDValue Chain, SDValue Callee,
120 unsigned CallConv, bool isVarArg, bool isTailCall,
121 const SmallVectorImpl &Outs,
122 const SmallVectorImpl &Ins,
123 DebugLoc dl, SelectionDAG &DAG,
124 SmallVectorImpl &InVals);
125
126 virtual SDValue
127 LowerReturn(SDValue Chain,
128 unsigned CallConv, bool isVarArg,
129 const SmallVectorImpl &Outs,
130 DebugLoc dl, SelectionDAG &DAG);
109131 };
110132 }
111133
122122 setOperationAction(ISD::VAEND, MVT::Other, Expand);
123123 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
124124 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
125
126 // RET must be custom lowered, to meet ABI requirements
127 setOperationAction(ISD::RET, MVT::Other, Custom);
128125 }
129126
130127 const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
159156 return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
160157 }
161158
162 // FORMAL_ARGUMENTS(CHAIN, CC#, ISVARARG, FLAG0, ..., FLAGn) - This node
163 // represents the formal arguments for a function. CC# is a Constant value
164 // indicating the calling convention of the function, and ISVARARG is a
165 // flag that indicates whether the function is varargs or not. This node
166 // has one result value for each incoming argument, plus one for the output
167 // chain.
168 SDValue BlackfinTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
169 SelectionDAG &DAG) {
170 DebugLoc dl = Op.getDebugLoc();
171 SDValue Root = Op.getOperand(0);
172 unsigned CC = Op.getConstantOperandVal(1);
173 bool isVarArg = Op.getConstantOperandVal(2);
159 SDValue
160 BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
161 unsigned CallConv, bool isVarArg,
162 const SmallVectorImpl
163 &Ins,
164 DebugLoc dl, SelectionDAG &DAG,
165 SmallVectorImpl &InVals) {
166
174167 MachineFunction &MF = DAG.getMachineFunction();
175168 MachineFrameInfo *MFI = MF.getFrameInfo();
176169
177170 SmallVector ArgLocs;
178 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
171 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
172 ArgLocs, *DAG.getContext());
179173 CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space
180 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Blackfin);
181
182 SmallVector ArgValues;
174 CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin);
175
183176 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
184177 CCValAssign &VA = ArgLocs[i];
185178
192185
193186 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
194187 MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
195 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
188 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
196189
197190 // If this is an 8 or 16-bit value, it is really passed promoted to 32
198191 // bits. Insert an assert[sz]ext to capture this, then truncate to the
207200 if (VA.getLocInfo() != CCValAssign::Full)
208201 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
209202
210 ArgValues.push_back(ArgValue);
203 InVals.push_back(ArgValue);
211204 } else {
212205 assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
213206 unsigned ObjSize = VA.getLocVT().getStoreSizeInBits()/8;
214207 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
215208 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
216 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
209 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
217210 }
218211 }
219212
220 ArgValues.push_back(Root);
221
222 // Return the new list of results.
223 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
224 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
225 }
226
227 SDValue BlackfinTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
213 return Chain;
214 }
215
216 SDValue
217 BlackfinTargetLowering::LowerReturn(SDValue Chain,
218 unsigned CallConv, bool isVarArg,
219 const SmallVectorImpl &Outs,
220 DebugLoc dl, SelectionDAG &DAG) {
221
228222 // CCValAssign - represent the assignment of the return value to locations.
229223 SmallVector RVLocs;
230 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
231 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
232 DebugLoc dl = Op.getDebugLoc();
233224
234225 // CCState - Info about the registers and stack slot.
235 CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs, *DAG.getContext());
236
237 // Analize return values of ISD::RET
238 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Blackfin);
226 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(),
227 RVLocs, *DAG.getContext());
228
229 // Analize return values.
230 CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin);
239231
240232 // If this is the first return lowered for this function, add the regs to the
241233 // liveout set for the function.
244236 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
245237 }
246238
247 SDValue Chain = Op.getOperand(0);
248239 SDValue Flag;
249240
250241 // Copy the result values into the output registers.
251242 for (unsigned i = 0; i != RVLocs.size(); ++i) {
252243 CCValAssign &VA = RVLocs[i];
253244 assert(VA.isRegLoc() && "Can only return in registers!");
254 SDValue Opi = Op.getOperand(i*2+1);
245 SDValue Opi = Outs[i].Val;
255246
256247 // Expand to i32 if necessary
257248 switch (VA.getLocInfo()) {
267258 Opi = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Opi);
268259 break;
269260 }
270 // ISD::RET => ret chain, (regnum1,val1), ...
271 // So i*2+1 index only the regnums.
272261 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue());
273262 // Guarantee that all emitted copies are stuck together with flags.
274263 Flag = Chain.getValue(1);
281270 }
282271 }
283272
284 SDValue BlackfinTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
285 CallSDNode *TheCall = cast(Op.getNode());
286 unsigned CallingConv = TheCall->getCallingConv();
287 SDValue Chain = TheCall->getChain();
288 SDValue Callee = TheCall->getCallee();
289 bool isVarArg = TheCall->isVarArg();
290 DebugLoc dl = TheCall->getDebugLoc();
273 SDValue
274 BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
275 unsigned CallConv, bool isVarArg,
276 bool isTailCall,
277 const SmallVectorImpl &Outs,
278 const SmallVectorImpl &Ins,
279 DebugLoc dl, SelectionDAG &DAG,
280 SmallVectorImpl &InVals) {
291281
292282 // Analyze operands of the call, assigning locations to each operand.
293283 SmallVector ArgLocs;
294 CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs,
284 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs,
295285 *DAG.getContext());
296286 CCInfo.AllocateStack(12, 4); // ABI requires 12 bytes stack space
297 CCInfo.AnalyzeCallOperands(TheCall, CC_Blackfin);
287 CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
298288
299289 // Get the size of the outgoing arguments stack space requirement.
300290 unsigned ArgsSize = CCInfo.getNextStackOffset();
306296 // Walk the register/memloc assignments, inserting copies/loads.
307297 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
308298 CCValAssign &VA = ArgLocs[i];
309
310 // Arguments start after the 5 first operands of ISD::CALL
311 SDValue Arg = TheCall->getArg(i);
299 SDValue Arg = Outs[i].Val;
312300
313301 // Promote the value if needed.
314302 switch (VA.getLocInfo()) {
382370
383371 // Assign locations to each value returned by this call.
384372 SmallVector RVLocs;
385 CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs,
373 CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), RVLocs,
386374 *DAG.getContext());
387375
388 RVInfo.AnalyzeCallResult(TheCall, RetCC_Blackfin);
389 SmallVector ResultVals;
376 RVInfo.AnalyzeCallResult(Ins, RetCC_Blackfin);
390377
391378 // Copy all of the result registers out of their specified physreg.
392379 for (unsigned i = 0; i != RVLocs.size(); ++i) {
416403 // Truncate to valtype
417404 if (RV.getLocInfo() != CCValAssign::Full)
418405 Val = DAG.getNode(ISD::TRUNCATE, dl, RV.getValVT(), Val);
419 ResultVals.push_back(Val);
420 }
421
422 ResultVals.push_back(Chain);
423
424 // Merge everything together with a MERGE_VALUES node.
425 SDValue merge = DAG.getNode(ISD::MERGE_VALUES, dl,
426 TheCall->getVTList(), &ResultVals[0],
427 ResultVals.size());
428 return merge;
406 InVals.push_back(Val);
407 }
408
409 return Chain;
429410 }
430411
431412 // Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
476457 // Frame & Return address. Currently unimplemented
477458 case ISD::FRAMEADDR: return SDValue();
478459 case ISD::RETURNADDR: return SDValue();
479 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
480 case ISD::CALL: return LowerCALL(Op, DAG);
481 case ISD::RET: return LowerRET(Op, DAG);
482460 case ISD::ADDE:
483461 case ISD::SUBE: return LowerADDE(Op, DAG);
484462 }
5050 private:
5151 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
5252 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
53 SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
54 SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
55 SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
5653 SDValue LowerADDE(SDValue Op, SelectionDAG &DAG);
54
55 virtual SDValue
56 LowerFormalArguments(SDValue Chain,
57 unsigned CallConv, bool isVarArg,
58 const SmallVectorImpl &Ins,
59 DebugLoc dl, SelectionDAG &DAG,
60 SmallVectorImpl &InVals);
61 virtual SDValue
62 LowerCall(SDValue Chain, SDValue Callee,
63 unsigned CallConv, bool isVarArg, bool isTailCall,
64 const SmallVectorImpl &Outs,
65 const SmallVectorImpl &Ins,
66 DebugLoc dl, SelectionDAG &DAG,
67 SmallVectorImpl &InVals);
68
69 virtual SDValue
70 LowerReturn(SDValue Chain,
71 unsigned CallConv, bool isVarArg,
72 const SmallVectorImpl &Outs,
73 DebugLoc dl, SelectionDAG &DAG);
5774 };
5875 } // end namespace llvm
5976
114114 const Type *RetTy = Op.getNode()->getValueType(0).getTypeForMVT();
115115 std::pair CallInfo =
116116 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
117 0, CallingConv::C, false, Callee, Args, DAG,
117 0, CallingConv::C, false,
118 /*isReturnValueUsed=*/true,
119 Callee, Args, DAG,
118120 Op.getDebugLoc());
119121
120122 return CallInfo.first;
394396 setOperationAction(ISD::ConstantPool, VT, Custom);
395397 setOperationAction(ISD::JumpTable, VT, Custom);
396398 }
397
398 // RET must be custom lowered, to meet ABI requirements
399 setOperationAction(ISD::RET, MVT::Other, Custom);
400399
401400 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
402401 setOperationAction(ISD::VASTART , MVT::Other, Custom);
10071006 return SDValue();
10081007 }
10091008
1010 static SDValue
1011 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
1012 {
1009 SDValue
1010 SPUTargetLowering::LowerFormalArguments(SDValue Chain,
1011 unsigned CallConv, bool isVarArg,
1012 const SmallVectorImpl
1013 &Ins,
1014 DebugLoc dl, SelectionDAG &DAG,
1015 SmallVectorImpl &InVals) {
1016
10131017 MachineFunction &MF = DAG.getMachineFunction();
10141018 MachineFrameInfo *MFI = MF.getFrameInfo();
10151019 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1016 SmallVector ArgValues;
1017 SDValue Root = Op.getOperand(0);
1018 bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0;
1019 DebugLoc dl = Op.getDebugLoc();
10201020
10211021 const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
10221022 const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
10281028 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
10291029
10301030 // Add DAG nodes to load the arguments or copy them out of registers.
1031 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues() - 1;
1032 ArgNo != e; ++ArgNo) {
1033 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1031 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1032 MVT ObjectVT = Ins[ArgNo].VT;
10341033 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
10351034 SDValue ArgVal;
10361035
10411040 default: {
10421041 std::string msg;
10431042 raw_string_ostream Msg(msg);
1044 Msg << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
1043 Msg << "LowerFormalArguments Unhandled argument type: "
10451044 << ObjectVT.getMVTString();
10461045 llvm_report_error(Msg.str());
10471046 }
10781077
10791078 unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass);
10801079 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
1081 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
1080 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
10821081 ++ArgRegIdx;
10831082 } else {
10841083 // We need to load the argument to a virtual register if we determined
10861085 // or we're forced to do vararg
10871086 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
10881087 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1089 ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
1088 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0);
10901089 ArgOffset += StackSlotSize;
10911090 }
10921091
1093 ArgValues.push_back(ArgVal);
1092 InVals.push_back(ArgVal);
10941093 // Update the chain
1095 Root = ArgVal.getOperand(0);
1094 Chain = ArgVal.getOperand(0);
10961095 }
10971096
10981097 // vararg handling:
11071106 VarArgsFrameIndex = MFI->CreateFixedObject(StackSlotSize, ArgOffset);
11081107 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
11091108 SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], MVT::v16i8);
1110 SDValue Store = DAG.getStore(Root, dl, ArgVal, FIN, NULL, 0);
1111 Root = Store.getOperand(0);
1109 SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, NULL, 0);
1110 Chain = Store.getOperand(0);
11121111 MemOps.push_back(Store);
11131112
11141113 // Increment address by stack slot size for the next stored argument
11151114 ArgOffset += StackSlotSize;
11161115 }
11171116 if (!MemOps.empty())
1118 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1119 &MemOps[0], MemOps.size());
1120 }
1121
1122 ArgValues.push_back(Root);
1123
1124 // Return the new list of results.
1125 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1126 &ArgValues[0], ArgValues.size());
1117 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1118 &MemOps[0], MemOps.size());
1119 }
1120
1121 return Chain;
11271122 }
11281123
11291124 /// isLSAAddress - Return the immediate to use if the specified
11401135 return DAG.getConstant((int)C->getZExtValue() >> 2, MVT::i32).getNode();
11411136 }
11421137
1143 static SDValue
1144 LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
1145 CallSDNode *TheCall = cast(Op.getNode());
1146 SDValue Chain = TheCall->getChain();
1147 SDValue Callee = TheCall->getCallee();
1148 unsigned NumOps = TheCall->getNumArgs();
1138 SDValue
1139 SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1140 unsigned CallConv, bool isVarArg,
1141 bool isTailCall,
1142 const SmallVectorImpl &Outs,
1143 const SmallVectorImpl &Ins,
1144 DebugLoc dl, SelectionDAG &DAG,
1145 SmallVectorImpl &InVals) {
1146
1147 const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
1148 unsigned NumOps = Outs.size();
11491149 unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
11501150 const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
11511151 const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
1152 DebugLoc dl = TheCall->getDebugLoc();
11531152
11541153 // Handy pointer type
11551154 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
11751174 SmallVector MemOpChains;
11761175
11771176 for (unsigned i = 0; i != NumOps; ++i) {
1178 SDValue Arg = TheCall->getArg(i);
1177 SDValue Arg = Outs[i].Val;
11791178
11801179 // PtrOff will be used to store the current argument to the stack if a
11811180 // register cannot be found for it.
13071306
13081307 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumStackBytes, true),
13091308 DAG.getIntPtrConstant(0, true), InFlag);
1310 if (TheCall->getValueType(0) != MVT::Other)
1309 if (!Ins.empty())
13111310 InFlag = Chain.getValue(1);
13121311
1313 SDValue ResultVals[3];
1314 unsigned NumResults = 0;
1312 // If the function returns void, just return the chain.
1313 if (Ins.empty())
1314 return Chain;
13151315
13161316 // If the call has results, copy the values out of the ret val registers.
1317 switch (TheCall->getValueType(0).getSimpleVT()) {
1317 switch (Ins[0].VT.getSimpleVT()) {
13181318 default: llvm_unreachable("Unexpected ret value!");
13191319 case MVT::Other: break;
13201320 case MVT::i32:
1321 if (TheCall->getValueType(1) == MVT::i32) {
1321 if (Ins.size() > 1 && Ins[1].VT == MVT::i32) {
13221322 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4,
13231323 MVT::i32, InFlag).getValue(1);
1324 ResultVals[0] = Chain.getValue(0);
1324 InVals.push_back(Chain.getValue(0));
13251325 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
13261326 Chain.getValue(2)).getValue(1);
1327 ResultVals[1] = Chain.getValue(0);
1328 NumResults = 2;
1327 InVals.push_back(Chain.getValue(0));
13291328 } else {
13301329 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32,
13311330 InFlag).getValue(1);
1332 ResultVals[0] = Chain.getValue(0);
1333 NumResults = 1;
1331 InVals.push_back(Chain.getValue(0));
13341332 }
13351333 break;
13361334 case MVT::i64:
13371335 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i64,
13381336 InFlag).getValue(1);
1339 ResultVals[0] = Chain.getValue(0);
1340 NumResults = 1;
1337 InVals.push_back(Chain.getValue(0));
13411338 break;
13421339 case MVT::i128:
13431340 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i128,
13441341 InFlag).getValue(1);
1345 ResultVals[0] = Chain.getValue(0);
1346 NumResults = 1;
1342 InVals.push_back(Chain.getValue(0));
13471343 break;
13481344 case MVT::f32:
13491345 case MVT::f64:
1350 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, TheCall->getValueType(0),
1346 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, Ins[0].VT,
13511347 InFlag).getValue(1);
1352 ResultVals[0] = Chain.getValue(0);
1353 NumResults = 1;
1348 InVals.push_back(Chain.getValue(0));
13541349 break;
13551350 case MVT::v2f64:
13561351 case MVT::v2i64:
13581353 case MVT::v4i32:
13591354 case MVT::v8i16:
13601355 case MVT::v16i8:
1361 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, TheCall->getValueType(0),
1356 Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, Ins[0].VT,
13621357 InFlag).getValue(1);
1363 ResultVals[0] = Chain.getValue(0);
1364 NumResults = 1;
1358 InVals.push_back(Chain.getValue(0));
13651359 break;
13661360 }
13671361
1368 // If the function returns void, just return the chain.
1369 if (NumResults == 0)
1370 return Chain;
1371
1372 // Otherwise, merge everything together with a MERGE_VALUES node.
1373 ResultVals[NumResults++] = Chain;
1374 SDValue Res = DAG.getMergeValues(ResultVals, NumResults, dl);
1375 return Res.getValue(Op.getResNo());
1376 }
1377
1378 static SDValue
1379 LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM) {
1362 return Chain;
1363 }
1364
1365 SDValue
1366 SPUTargetLowering::LowerReturn(SDValue Chain,
1367 unsigned CallConv, bool isVarArg,
1368 const SmallVectorImpl &Outs,
1369 DebugLoc dl, SelectionDAG &DAG) {
1370
13801371 SmallVector RVLocs;
1381 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1382 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1383 DebugLoc dl = Op.getDebugLoc();
1384 CCState CCInfo(CC, isVarArg, TM, RVLocs, *DAG.getContext());
1385 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SPU);
1372 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1373 RVLocs, *DAG.getContext());
1374 CCInfo.AnalyzeReturn(Outs, RetCC_SPU);
13861375
13871376 // If this is the first return lowered for this function, add the regs to the
13881377 // liveout set for the function.
13911380 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
13921381 }
13931382
1394 SDValue Chain = Op.getOperand(0);
13951383 SDValue Flag;
13961384
13971385 // Copy the result values into the output registers.
13991387 CCValAssign &VA = RVLocs[i];
14001388 assert(VA.isRegLoc() && "Can only return in registers!");
14011389 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1402 Op.getOperand(i*2+1), Flag);
1390 Outs[i].Val, Flag);
14031391 Flag = Chain.getValue(1);
14041392 }
14051393
26472635 return LowerJumpTable(Op, DAG, SPUTM.getSubtargetImpl());
26482636 case ISD::ConstantFP:
26492637 return LowerConstantFP(Op, DAG);
2650 case ISD::FORMAL_ARGUMENTS:
2651 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
2652 case ISD::CALL:
2653 return LowerCALL(Op, DAG, SPUTM.getSubtargetImpl());
2654 case ISD::RET:
2655 return LowerRET(Op, DAG, getTargetMachine());
26562638
26572639 // i8, i64 math ops:
26582640 case ISD::ADD:
149149
150150 /// getFunctionAlignment - Return the Log2 alignment of this function.
151151 virtual unsigned getFunctionAlignment(const Function *F) const;
152
153 virtual SDValue
154 LowerFormalArguments(SDValue Chain,
155 unsigned CallConv, bool isVarArg,
156 const SmallVectorImpl &Ins,
157 DebugLoc dl, SelectionDAG &DAG,
158 SmallVectorImpl &InVals);
159
160 virtual SDValue
161 LowerCall(SDValue Chain, SDValue Callee,
162 unsigned CallConv, bool isVarArg,
163 bool isTailCall,
164 const SmallVectorImpl &Outs,
165 const SmallVectorImpl &Ins,
166 DebugLoc dl, SelectionDAG &DAG,
167 SmallVectorImpl &InVals);
168
169 virtual SDValue
170 LowerReturn(SDValue Chain,
171 unsigned CallConv, bool isVarArg,
172 const SmallVectorImpl &Outs,
173 DebugLoc dl, SelectionDAG &DAG);
152174 };
153175 }
154176
44304430 (ILHr8 imm:$imm)>;
44314431
44324432 //===----------------------------------------------------------------------===//
4433 // Call instruction patterns:
4434 //===----------------------------------------------------------------------===//
4435 // Return void
4436 def : Pat<(ret),
4437 (RET)>;
4438
4439 //===----------------------------------------------------------------------===//
44404433 // Zero/Any/Sign extensions
44414434 //===----------------------------------------------------------------------===//
44424435
7979 setOperationAction(ISD::ROTR, MVT::i8, Expand);
8080 setOperationAction(ISD::ROTL, MVT::i16, Expand);
8181 setOperationAction(ISD::ROTR, MVT::i16, Expand);
82 setOperationAction(ISD::RET, MVT::Other, Custom);
8382 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
8483 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
8584 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
128127
129128 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
130129 switch (Op.getOpcode()) {
131 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
132130 case ISD::SHL: // FALLTHROUGH
133131 case ISD::SRL:
134132 case ISD::SRA: return LowerShifts(Op, DAG);
135 case ISD::RET: return LowerRET(Op, DAG);
136 case ISD::CALL: return LowerCALL(Op, DAG);
137133 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
138134 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
139135 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
156152
157153 #include "MSP430GenCallingConv.inc"
158154
159 SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
160 SelectionDAG &DAG) {
161 unsigned CC = cast(Op.getOperand(1))->getZExtValue();
162 switch (CC) {
155 SDValue
156 MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
157 unsigned CallConv,
158 bool isVarArg,
159 const SmallVectorImpl
160 &Ins,
161 DebugLoc dl,
162 SelectionDAG &DAG,
163 SmallVectorImpl &InVals) {
164
165 switch (CallConv) {
163166 default:
164167 llvm_unreachable("Unsupported calling convention");
165168 case CallingConv::C:
166169 case CallingConv::Fast:
167 return LowerCCCArguments(Op, DAG);
168 }
169 }
170
171 SDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
172 CallSDNode *TheCall = cast(Op.getNode());
173 unsigned CallingConv = TheCall->getCallingConv();
174 switch (CallingConv) {
170 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
171 }
172 }
173
174 SDValue
175 MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
176 unsigned CallConv, bool isVarArg,
177 bool isTailCall,
178 const SmallVectorImpl &Outs,
179 const SmallVectorImpl &Ins,
180 DebugLoc dl, SelectionDAG &DAG,
181 SmallVectorImpl &InVals) {
182
183 switch (CallConv) {
175184 default:
176185 llvm_unreachable("Unsupported calling convention");
177186 case CallingConv::Fast:
178187 case CallingConv::C:
179 return LowerCCCCallTo(Op, DAG, CallingConv);
188 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
189 Outs, Ins, dl, DAG, InVals);
180190 }
181191 }
182192
184194 /// generate load operations for arguments places on the stack.
185195 // FIXME: struct return stuff
186196 // FIXME: varargs
187 SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
188 SelectionDAG &DAG) {
197 SDValue
198 MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
199 unsigned CallConv,
200 bool isVarArg,
201 const SmallVectorImpl
202 &Ins,
203 DebugLoc dl,
204 SelectionDAG &DAG,
205 SmallVectorImpl &InVals) {
189206 MachineFunction &MF = DAG.getMachineFunction();
190207 MachineFrameInfo *MFI = MF.getFrameInfo();
191208 MachineRegisterInfo &RegInfo = MF.getRegInfo();
192 SDValue Root = Op.getOperand(0);
193 bool isVarArg = cast(Op.getOperand(2))->getZExtValue() != 0;
194 unsigned CC = MF.getFunction()->getCallingConv();
195 DebugLoc dl = Op.getDebugLoc();
196209
197210 // Assign locations to all of the incoming arguments.
198211 SmallVector ArgLocs;
199 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
200 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430);
212 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
213 ArgLocs, *DAG.getContext());
214 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
201215
202216 assert(!isVarArg && "Varargs not supported yet");
203217
204 SmallVector ArgValues;
205218 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
206219 CCValAssign &VA = ArgLocs[i];
207220 if (VA.isRegLoc()) {
211224 default:
212225 {
213226 #ifndef NDEBUG
214 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
227 cerr << "LowerFormalArguments Unhandled argument type: "
215228 << RegVT.getSimpleVT() << "\n";
216229 #endif
217230 llvm_unreachable(0);
220233 unsigned VReg =
221234 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
222235 RegInfo.addLiveIn(VA.getLocReg(), VReg);
223 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
236 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
224237
225238 // If this is an 8-bit value, it is really passed promoted to 16
226239 // bits. Insert an assert[sz]ext to capture this, then truncate to the
235248 if (VA.getLocInfo() != CCValAssign::Full)
236249 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
237250
238 ArgValues.push_back(ArgValue);
251 InVals.push_back(ArgValue);
239252 }
240253 } else {
241254 // Sanity check
243256 // Load the argument to a virtual register
244257 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
245258 if (ObjSize > 2) {
246 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
259 cerr << "LowerFormalArguments Unhandled argument type: "
247260 << VA.getLocVT().getSimpleVT()
248261 << "\n";
249262 }
253266 // Create the SelectionDAG nodes corresponding to a load
254267 //from this parameter
255268 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
256 ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
257 PseudoSourceValue::getFixedStack(FI), 0));
269 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
270 PseudoSourceValue::getFixedStack(FI), 0));
258271 }
259272 }
260273
261 ArgValues.push_back(Root);
262
263 // Return the new list of results.
264 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
265 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
266 }
267
268 SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
274 return Chain;
275 }
276
277 SDValue
278 MSP430TargetLowering::LowerReturn(SDValue Chain,
279 unsigned CallConv, bool isVarArg,
280 const SmallVectorImpl &Outs,
281 DebugLoc dl, SelectionDAG &DAG) {
282
269283 // CCValAssign - represent the assignment of the return value to a location
270284 SmallVector RVLocs;
271 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
272 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
273 DebugLoc dl = Op.getDebugLoc();
274285
275286 // CCState - Info about the registers and stack slot.
276 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, *DAG.getContext());
277
278 // Analize return values of ISD::RET
279 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430);
287 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
288 RVLocs, *DAG.getContext());
289
290 // Analize return values.
291 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
280292
281293 // If this is the first return lowered for this function, add the regs to the
282294 // liveout set for the function.
286298 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
287299 }
288300
289 // The chain is always operand #0
290 SDValue Chain = Op.getOperand(0);
291301 SDValue Flag;
292302
293303 // Copy the result values into the output registers.
295305 CCValAssign &VA = RVLocs[i];
296306 assert(VA.isRegLoc() && "Can only return in registers!");
297307
298 // ISD::RET => ret chain, (regnum1,val1), ...
299 // So i*2+1 index only the regnums
300308 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
301 Op.getOperand(i*2+1), Flag);
309 Outs[i].Val, Flag);
302310
303311 // Guarantee that all emitted copies are stuck together,
304312 // avoiding something bad.
315323 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
316324 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
317325 /// TODO: sret.
318 SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
319 unsigned CC) {
320 CallSDNode *TheCall = cast(Op.getNode());
321 SDValue Chain = TheCall->getChain();
322 SDValue Callee = TheCall->getCallee();
323 bool isVarArg = TheCall->isVarArg();
324 DebugLoc dl = Op.getDebugLoc();
325
326 SDValue
327 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
328 unsigned CallConv, bool isVarArg,
329 bool isTailCall,
330 const SmallVectorImpl
331 &Outs,
332 const SmallVectorImpl &Ins,
333 DebugLoc dl, SelectionDAG &DAG,
334 SmallVectorImpl &InVals) {
326335 // Analyze operands of the call, assigning locations to each operand.
327336 SmallVector ArgLocs;
328 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext());
329
330 CCInfo.AnalyzeCallOperands(TheCall, CC_MSP430);
337 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
338 ArgLocs, *DAG.getContext());
339
340 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
331341
332342 // Get a count of how many bytes are to be pushed on the stack.
333343 unsigned NumBytes = CCInfo.getNextStackOffset();
343353 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
344354 CCValAssign &VA = ArgLocs[i];
345355
346 // Arguments start after the 5 first operands of ISD::CALL
347 SDValue Arg = TheCall->getArg(i);
356 SDValue Arg