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[X86] Regenerate cmpxchg tests Add 64-bit cmpxchg8b tests git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326380 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 2 years ago
3 changed file(s) with 131 addition(s) and 23 deletion(s). Raw diff Collapse all Expand all
None ; RUN: llc -mcpu=core-avx2 -mtriple=x86_64 -o - %s | FileCheck %s
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=core-avx2 | FileCheck %s
12
23 define i1 @try_cmpxchg(i128* %addr, i128 %desired, i128 %new) {
34 ; CHECK-LABEL: try_cmpxchg:
4 ; CHECK: cmpxchg16b
5 ; CHECK-NOT: cmp
6 ; CHECK: sete %al
7 ; CHECK: retq
5 ; CHECK: # %bb.0:
6 ; CHECK-NEXT: pushq %rbx
7 ; CHECK-NEXT: .cfi_def_cfa_offset 16
8 ; CHECK-NEXT: .cfi_offset %rbx, -16
9 ; CHECK-NEXT: movq %rcx, %r9
10 ; CHECK-NEXT: movq %rsi, %rax
11 ; CHECK-NEXT: movq %r8, %rcx
12 ; CHECK-NEXT: movq %r9, %rbx
13 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
14 ; CHECK-NEXT: sete %al
15 ; CHECK-NEXT: popq %rbx
16 ; CHECK-NEXT: retq
817 %pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
918 %success = extractvalue { i128, i1 } %pair, 1
1019 ret i1 %success
1221
1322 define void @cmpxchg_flow(i128* %addr, i128 %desired, i128 %new) {
1423 ; CHECK-LABEL: cmpxchg_flow:
15 ; CHECK: cmpxchg16b
16 ; CHECK-NOT: cmp
17 ; CHECK-NOT: set
18 ; CHECK: {{jne|jeq}}
24 ; CHECK: # %bb.0:
25 ; CHECK-NEXT: pushq %rbx
26 ; CHECK-NEXT: .cfi_def_cfa_offset 16
27 ; CHECK-NEXT: .cfi_offset %rbx, -16
28 ; CHECK-NEXT: movq %rcx, %r9
29 ; CHECK-NEXT: movq %rsi, %rax
30 ; CHECK-NEXT: movq %r8, %rcx
31 ; CHECK-NEXT: movq %r9, %rbx
32 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
33 ; CHECK-NEXT: jne .LBB1_2
34 ; CHECK-NEXT: # %bb.1: # %true
35 ; CHECK-NEXT: callq foo
36 ; CHECK-NEXT: popq %rbx
37 ; CHECK-NEXT: retq
38 ; CHECK-NEXT: .LBB1_2: # %false
39 ; CHECK-NEXT: callq bar
40 ; CHECK-NEXT: popq %rbx
41 ; CHECK-NEXT: retq
1942 %pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
2043 %success = extractvalue { i128, i1 } %pair, 1
2144 br i1 %success, label %true, label %false
3255 ; Can't use the flags here because cmpxchg16b only sets ZF.
3356 define i1 @cmpxchg_arithcmp(i128* %addr, i128 %desired, i128 %new) {
3457 ; CHECK-LABEL: cmpxchg_arithcmp:
35 ; CHECK: cmpxchg16b
36 ; CHECK: cmpq
37 ; CHECK: retq
58 ; CHECK: # %bb.0:
59 ; CHECK-NEXT: pushq %rbx
60 ; CHECK-NEXT: .cfi_def_cfa_offset 16
61 ; CHECK-NEXT: .cfi_offset %rbx, -16
62 ; CHECK-NEXT: movq %rcx, %r9
63 ; CHECK-NEXT: movq %rdx, %r10
64 ; CHECK-NEXT: movq %rsi, %rax
65 ; CHECK-NEXT: movq %r8, %rcx
66 ; CHECK-NEXT: movq %r9, %rbx
67 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
68 ; CHECK-NEXT: cmpq %rsi, %rax
69 ; CHECK-NEXT: sbbq %r10, %rdx
70 ; CHECK-NEXT: setge %al
71 ; CHECK-NEXT: popq %rbx
72 ; CHECK-NEXT: retq
3873 %pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
3974 %oldval = extractvalue { i128, i1 } %pair, 0
4075 %success = icmp sge i128 %oldval, %desired
4378
4479 define i128 @cmpxchg_zext(i128* %addr, i128 %desired, i128 %new) {
4580 ; CHECK-LABEL: cmpxchg_zext:
46 ; CHECK: xorl
47 ; CHECK: cmpxchg16b
48 ; CHECK-NOT: cmpq
49 ; CHECK: sete
81 ; CHECK: # %bb.0:
82 ; CHECK-NEXT: pushq %rbx
83 ; CHECK-NEXT: .cfi_def_cfa_offset 16
84 ; CHECK-NEXT: .cfi_offset %rbx, -16
85 ; CHECK-NEXT: movq %rcx, %r9
86 ; CHECK-NEXT: xorl %r10d, %r10d
87 ; CHECK-NEXT: movq %rsi, %rax
88 ; CHECK-NEXT: movq %r8, %rcx
89 ; CHECK-NEXT: movq %r9, %rbx
90 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
91 ; CHECK-NEXT: sete %r10b
92 ; CHECK-NEXT: xorl %edx, %edx
93 ; CHECK-NEXT: movq %r10, %rax
94 ; CHECK-NEXT: popq %rbx
95 ; CHECK-NEXT: retq
5096 %pair = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
5197 %success = extractvalue { i128, i1 } %pair, 1
5298 %mask = zext i1 %success to i128
56102
57103 define i128 @cmpxchg_use_eflags_and_val(i128* %addr, i128 %offset) {
58104 ; CHECK-LABEL: cmpxchg_use_eflags_and_val:
59
60 ; CHECK: cmpxchg16b
61 ; CHECK-NOT: cmpq
62 ; CHECK: jne
105 ; CHECK: # %bb.0: # %entry
106 ; CHECK-NEXT: pushq %rbx
107 ; CHECK-NEXT: .cfi_def_cfa_offset 16
108 ; CHECK-NEXT: .cfi_offset %rbx, -16
109 ; CHECK-NEXT: movq %rdx, %r8
110 ; CHECK-NEXT: xorl %eax, %eax
111 ; CHECK-NEXT: xorl %edx, %edx
112 ; CHECK-NEXT: xorl %ecx, %ecx
113 ; CHECK-NEXT: xorl %ebx, %ebx
114 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
115 ; CHECK-NEXT: .p2align 4, 0x90
116 ; CHECK-NEXT: .LBB4_1: # %loop
117 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
118 ; CHECK-NEXT: movq %rdx, %r9
119 ; CHECK-NEXT: movq %rax, %r10
120 ; CHECK-NEXT: movq %rax, %rbx
121 ; CHECK-NEXT: addq %rsi, %rbx
122 ; CHECK-NEXT: movq %rdx, %rcx
123 ; CHECK-NEXT: adcq %r8, %rcx
124 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
125 ; CHECK-NEXT: jne .LBB4_1
126 ; CHECK-NEXT: # %bb.2: # %done
127 ; CHECK-NEXT: movq %r10, %rax
128 ; CHECK-NEXT: movq %r9, %rdx
129 ; CHECK-NEXT: popq %rbx
130 ; CHECK-NEXT: retq
63131 entry:
64132 %init = load atomic i128, i128* %addr seq_cst, align 16
65133 br label %loop
None ; RUN: llc < %s -mtriple=x86_64-- -mcpu=core2 | FileCheck %s
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK
12
23 ; Basic 128-bit cmpxchg
34 define void @t1(i128* nocapture %p) nounwind ssp {
5 ; CHECK-LABEL: t1:
6 ; CHECK: # %bb.0: # %entry
7 ; CHECK-NEXT: pushq %rbx
8 ; CHECK-NEXT: xorl %eax, %eax
9 ; CHECK-NEXT: xorl %edx, %edx
10 ; CHECK-NEXT: xorl %ecx, %ecx
11 ; CHECK-NEXT: movl $1, %ebx
12 ; CHECK-NEXT: lock cmpxchg16b (%rdi)
13 ; CHECK-NEXT: popq %rbx
14 ; CHECK-NEXT: retq
415 entry:
5 ; CHECK: movl $1, %ebx
6 ; CHECK: lock cmpxchg16b
716 %r = cmpxchg i128* %p, i128 0, i128 1 seq_cst seq_cst
817 ret void
918 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=i686-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X86
2 ; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X64
3
4 ; Basic 64-bit cmpxchg
5 define void @t1(i64* nocapture %p) nounwind ssp {
6 ; X86-LABEL: t1:
7 ; X86: # %bb.0: # %entry
8 ; X86-NEXT: pushl %ebx
9 ; X86-NEXT: pushl %esi
10 ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
11 ; X86-NEXT: xorl %eax, %eax
12 ; X86-NEXT: xorl %edx, %edx
13 ; X86-NEXT: xorl %ecx, %ecx
14 ; X86-NEXT: movl $1, %ebx
15 ; X86-NEXT: lock cmpxchg8b (%esi)
16 ; X86-NEXT: popl %esi
17 ; X86-NEXT: popl %ebx
18 ; X86-NEXT: retl
19 ;
20 ; X64-LABEL: t1:
21 ; X64: # %bb.0: # %entry
22 ; X64-NEXT: movl $1, %ecx
23 ; X64-NEXT: xorl %eax, %eax
24 ; X64-NEXT: lock cmpxchgq %rcx, (%rdi)
25 ; X64-NEXT: retq
26 entry:
27 %r = cmpxchg i64* %p, i64 0, i64 1 seq_cst seq_cst
28 ret void
29 }
30