llvm.org GIT mirror llvm / 98a366d
Instead of passing in an unsigned value for the optimization level, use an enum, which better identifies what the optimization is doing. And is more flexible for future uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70440 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 11 years ago
81 changed file(s) with 377 addition(s) and 251 deletion(s). Raw diff Collapse all Expand all
1515 #ifndef LLVM_CODEGEN_ASMPRINTER_H
1616 #define LLVM_CODEGEN_ASMPRINTER_H
1717
18 #include "llvm/ADT/DenseMap.h"
1819 #include "llvm/CodeGen/MachineFunctionPass.h"
1920 #include "llvm/Support/DataTypes.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/Target/TargetMachine.h"
2122 #include
2223
2324 namespace llvm {
6566 std::set ExtWeakSymbols;
6667
6768 /// OptLevel - Generating code at a specific optimization level.
68 unsigned OptLevel;
69 CodeGenOpt::Level OptLevel;
6970 public:
7071 /// Output stream on which we're printing assembly code.
7172 ///
110111
111112 protected:
112113 explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
113 const TargetAsmInfo *T, unsigned OL, bool V);
114 const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V);
114115
115116 public:
116117 virtual ~AsmPrinter();
2020 #define LLVM_CODEGEN_DWARFWRITER_H
2121
2222 #include "llvm/Pass.h"
23 #include "llvm/Target/TargetMachine.h"
2324
2425 namespace llvm {
2526
8081 void EndFunction(MachineFunction *MF);
8182
8283 /// ValidDebugInfo - Return true if V represents valid debug info value.
83 bool ValidDebugInfo(Value *V, unsigned OptLevel);
84 bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel);
8485
8586 /// RecordSourceLine - Register a source line with debug info. Returns a
8687 /// unique label ID used to generate a label and provide correspondence to
1717 #include "llvm/CodeGen/Passes.h"
1818 #include "llvm/CodeGen/SchedulerRegistry.h"
1919 #include "llvm/CodeGen/GCs.h"
20 #include "llvm/Target/TargetMachine.h"
2021
2122 namespace {
2223 struct ForceCodegenLinking {
4142 llvm::linkOcamlGC();
4243 llvm::linkShadowStackGC();
4344
44 (void) llvm::createBURRListDAGScheduler(NULL, 3);
45 (void) llvm::createTDRRListDAGScheduler(NULL, 3);
46 (void) llvm::createTDListDAGScheduler(NULL, 3);
47 (void) llvm::createFastDAGScheduler(NULL, 3);
48 (void) llvm::createDefaultScheduler(NULL, 3);
45 (void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
46 (void) llvm::createTDRRListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
47 (void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default);
48 (void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default);
49 (void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default);
4950
5051 }
5152 } ForceCodegenLinking; // Force link by creating a global definition.
1515 #define LLVM_CODEGENSCHEDULERREGISTRY_H
1616
1717 #include "llvm/CodeGen/MachinePassRegistry.h"
18 #include "llvm/Target/TargetMachine.h"
1819
1920 namespace llvm {
2021
3132
3233 class RegisterScheduler : public MachinePassRegistryNode {
3334 public:
34 typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*, unsigned);
35 typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
36 CodeGenOpt::Level);
3537
3638 static MachinePassRegistry Registry;
3739
6365 /// createBURRListDAGScheduler - This creates a bottom up register usage
6466 /// reduction list scheduler.
6567 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
66 unsigned OptLevel);
68 CodeGenOpt::Level OptLevel);
6769
6870 /// createTDRRListDAGScheduler - This creates a top down register usage
6971 /// reduction list scheduler.
7072 ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
71 unsigned OptLevel);
73 CodeGenOpt::Level OptLevel);
7274
7375 /// createTDListDAGScheduler - This creates a top-down list scheduler with
7476 /// a hazard recognizer.
7577 ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
76 unsigned OptLevel);
78 CodeGenOpt::Level OptLevel);
7779
7880 /// createFastDAGScheduler - This creates a "fast" scheduler.
7981 ///
8082 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
81 unsigned OptLevel);
83 CodeGenOpt::Level OptLevel);
8284
8385 /// createDefaultScheduler - This creates an instruction scheduler appropriate
8486 /// for the target.
8587 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
86 unsigned OptLevel);
88 CodeGenOpt::Level OptLevel);
8789
8890 } // end namespace llvm
8991
1919 #include "llvm/ADT/FoldingSet.h"
2020 #include "llvm/ADT/StringMap.h"
2121 #include "llvm/CodeGen/SelectionDAGNodes.h"
22
22 #include "llvm/Target/TargetMachine.h"
2323 #include
2424 #include
2525 #include
2929
3030 class AliasAnalysis;
3131 class TargetLowering;
32 class TargetMachine;
3332 class MachineModuleInfo;
3433 class DwarfWriter;
3534 class MachineFunction;
201200 /// certain types of nodes together, or eliminating superfluous nodes. The
202201 /// Level argument controls whether Combine is allowed to produce nodes and
203202 /// types that are illegal on the target.
204 void Combine(CombineLevel Level, AliasAnalysis &AA, unsigned OptLevel);
203 void Combine(CombineLevel Level, AliasAnalysis &AA,
204 CodeGenOpt::Level OptLevel);
205205
206206 /// LegalizeTypes - This transforms the SelectionDAG into a SelectionDAG that
207207 /// only uses types natively supported by the target. Returns "true" if it
217217 ///
218218 /// Note that this is an involved process that may invalidate pointers into
219219 /// the graph.
220 void Legalize(bool TypesNeedLegalizing, unsigned OptLevel);
220 void Legalize(bool TypesNeedLegalizing, CodeGenOpt::Level OptLevel);
221221
222222 /// RemoveDeadNodes - This method deletes all unreachable nodes in the
223223 /// SelectionDAG.
5050 MachineBasicBlock *BB;
5151 AliasAnalysis *AA;
5252 GCFunctionInfo *GFI;
53 unsigned OptLevel;
53 CodeGenOpt::Level OptLevel;
5454 static char ID;
5555
56 explicit SelectionDAGISel(TargetMachine &tm, unsigned OL = 3);
56 explicit SelectionDAGISel(TargetMachine &tm,
57 CodeGenOpt::Level OL = CodeGenOpt::Default);
5758 virtual ~SelectionDAGISel();
5859
5960 TargetLowering &getTargetLowering() { return TLI; }
1717 #include
1818 #include
1919 #include
20 #include "llvm/ADT/SmallVector.h"
2021 #include "llvm/System/Mutex.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/Target/TargetMachine.h"
2223
2324 namespace llvm {
2425
8384 // libraries, the JIT and Interpreter set these functions to ctor pointers
8485 // at startup time if they are linked in.
8586 typedef ExecutionEngine *(*EECtorFn)(ModuleProvider*, std::string*,
86 unsigned OptLevel);
87 CodeGenOpt::Level OptLevel);
8788 static EECtorFn JITCtor, InterpCtor;
8889
8990 /// LazyFunctionCreator - If an unknown function is needed, this function
113114 static ExecutionEngine *create(ModuleProvider *MP,
114115 bool ForceInterpreter = false,
115116 std::string *ErrorStr = 0,
116 unsigned OptLevel = 3);
117 CodeGenOpt::Level OptLevel =
118 CodeGenOpt::Default);
117119
118120 /// create - This is the factory method for creating an execution engine which
119121 /// is appropriate for the current machine. This takes ownership of the
126128 static ExecutionEngine *createJIT(ModuleProvider *MP,
127129 std::string *ErrorStr = 0,
128130 JITMemoryManager *JMM = 0,
129 unsigned OptLevel = 3);
130
131
132
131 CodeGenOpt::Level OptLevel =
132 CodeGenOpt::Default);
133
133134 /// addModuleProvider - Add a ModuleProvider to the list of modules that we
134135 /// can JIT from. Note that this takes ownership of the ModuleProvider: when
135136 /// the ExecutionEngine is destroyed, it destroys the MP as well.
6767 };
6868 }
6969
70 // Code generation optimization level.
71 namespace CodeGenOpt {
72 enum Level {
73 Default,
74 None,
75 One,
76 Two,
77 Size,
78 Aggressive,
79 LTO
80 };
81 }
82
7083 //===----------------------------------------------------------------------===//
7184 ///
7285 /// TargetMachine - Primary interface to the complete machine description for
212225 virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
213226 raw_ostream &,
214227 CodeGenFileType,
215 unsigned /* OptLevel */) {
228 CodeGenOpt::Level) {
216229 return FileModel::None;
217230 }
218231
222235 ///
223236 virtual bool addPassesToEmitFileFinish(PassManagerBase &,
224237 MachineCodeEmitter *,
225 unsigned /* OptLevel */) {
238 CodeGenOpt::Level) {
226239 return true;
227240 }
228241
234247 ///
235248 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
236249 MachineCodeEmitter &,
237 unsigned /* OptLevel */) {
250 CodeGenOpt::Level) {
238251 return true;
239252 }
240253
244257 virtual bool WantsWholeFile() const { return false; }
245258 virtual bool addPassesToEmitWholeFile(PassManager &, raw_ostream &,
246259 CodeGenFileType,
247 unsigned /* OptLevel */) {
260 CodeGenOpt::Level) {
248261 return true;
249262 }
250263 };
259272 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
260273 /// both emitting to assembly files or machine code output.
261274 ///
262 bool addCommonCodeGenPasses(PassManagerBase &, unsigned /* OptLevel */);
275 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level);
263276
264277 public:
265278
266279 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
267280 /// specified file emitted. Typically this will involve several steps of code
268 /// generation. If OptLevel is 0, the code generator should emit code as fast
281 /// generation. If OptLevel is None, the code generator should emit code as fast
269282 /// as possible, though the generated code may be less efficient. This method
270283 /// should return FileModel::Error if emission of this file type is not
271284 /// supported.
277290 virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
278291 raw_ostream &Out,
279292 CodeGenFileType FileType,
280 unsigned OptLevel);
293 CodeGenOpt::Level);
281294
282295 /// addPassesToEmitFileFinish - If the passes to emit the specified file had
283296 /// to be split up (e.g., to add an object writer pass), this method can be
285298 ///
286299 virtual bool addPassesToEmitFileFinish(PassManagerBase &PM,
287300 MachineCodeEmitter *MCE,
288 unsigned OptLevel);
301 CodeGenOpt::Level);
289302
290303 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
291304 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
295308 ///
296309 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
297310 MachineCodeEmitter &MCE,
298 unsigned OptLevel);
311 CodeGenOpt::Level);
299312
300313 /// Target-Independent Code Generator Pass Configuration Options.
301314
302315 /// addInstSelector - This method should add any "last minute" LLVM->LLVM
303316 /// passes, then install an instruction selector pass, which converts from
304317 /// LLVM code to machine instructions.
305 virtual bool addInstSelector(PassManagerBase &, unsigned /* OptLevel */) {
318 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
306319 return true;
307320 }
308321
309322 /// addPreRegAllocPasses - This method may be implemented by targets that want
310323 /// to run passes immediately before register allocation. This should return
311324 /// true if -print-machineinstrs should print after these passes.
312 virtual bool addPreRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
325 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
313326 return false;
314327 }
315328
317330 /// want to run passes after register allocation but before prolog-epilog
318331 /// insertion. This should return true if -print-machineinstrs should print
319332 /// after these passes.
320 virtual bool addPostRegAlloc(PassManagerBase &, unsigned /* OptLevel */) {
333 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
321334 return false;
322335 }
323336
324337 /// addPreEmitPass - This pass may be implemented by targets that want to run
325338 /// passes immediately before machine code is emitted. This should return
326339 /// true if -print-machineinstrs should print out the code after the passes.
327 virtual bool addPreEmitPass(PassManagerBase &, unsigned /* OptLevel */) {
340 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
328341 return false;
329342 }
330343
332345 /// addAssemblyEmitter - This pass should be overridden by the target to add
333346 /// the asmprinter, if asm emission is supported. If this is not supported,
334347 /// 'true' should be returned.
335 virtual bool addAssemblyEmitter(PassManagerBase &, unsigned /* OptLevel */,
348 virtual bool addAssemblyEmitter(PassManagerBase &, CodeGenOpt::Level,
336349 bool /* VerboseAsmDefault */, raw_ostream &) {
337350 return true;
338351 }
340353 /// addCodeEmitter - This pass should be overridden by the target to add a
341354 /// code emitter, if supported. If this is not supported, 'true' should be
342355 /// returned. If DumpAsm is true, the generated assembly is printed to cerr.
343 virtual bool addCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
356 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
344357 bool /*DumpAsm*/, MachineCodeEmitter &) {
345358 return true;
346359 }
349362 /// a code emitter (without setting flags), if supported. If this is not
350363 /// supported, 'true' should be returned. If DumpAsm is true, the generated
351364 /// assembly is printed to cerr.
352 virtual bool addSimpleCodeEmitter(PassManagerBase &, unsigned /* OptLevel */,
365 virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
353366 bool /*DumpAsm*/, MachineCodeEmitter &) {
354367 return true;
355368 }
2626 #include "llvm/Target/TargetAsmInfo.h"
2727 #include "llvm/Target/TargetData.h"
2828 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetMachine.h"
3029 #include "llvm/Target/TargetOptions.h"
3130 #include "llvm/Target/TargetRegisterInfo.h"
3231 #include "llvm/ADT/SmallPtrSet.h"
4140
4241 char AsmPrinter::ID = 0;
4342 AsmPrinter::AsmPrinter(raw_ostream &o, TargetMachine &tm,
44 const TargetAsmInfo *T, unsigned OL, bool VDef)
43 const TargetAsmInfo *T, CodeGenOpt::Level OL, bool VDef)
4544 : MachineFunctionPass(&ID), FunctionNumber(0), OptLevel(OL), O(o),
4645 TM(tm), TAI(T), TRI(tm.getRegisterInfo()),
4746 IsInTextSection(false)
33503350 }
33513351
33523352 /// ValidDebugInfo - Return true if V represents valid debug info value.
3353 bool ValidDebugInfo(Value *V, unsigned OptLevel) {
3353 bool ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) {
33543354 if (!V)
33553355 return false;
33563356
33923392 case DW_TAG_lexical_block:
33933393 /// FIXME. This interfers with the qualitfy of generated code when
33943394 /// during optimization.
3395 if (OptLevel != 0)
3395 if (OptLevel != CodeGenOpt::None)
33963396 return false;
33973397 default:
33983398 break;
47304730 }
47314731
47324732 /// ValidDebugInfo - Return true if V represents valid debug info value.
4733 bool DwarfWriter::ValidDebugInfo(Value *V, unsigned OptLevel) {
4733 bool DwarfWriter::ValidDebugInfo(Value *V, CodeGenOpt::Level OptLevel) {
47344734 return DD && DD->ValidDebugInfo(V, OptLevel);
47354735 }
47364736
5454 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
5555 raw_ostream &Out,
5656 CodeGenFileType FileType,
57 unsigned OptLevel) {
57 CodeGenOpt::Level OptLevel) {
5858 // Add common CodeGen passes.
5959 if (addCommonCodeGenPasses(PM, OptLevel))
6060 return FileModel::Error;
6868 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
6969 PM.add(createMachineFunctionPrinterPass(cerr));
7070
71 if (OptLevel != 0)
71 if (OptLevel != CodeGenOpt::None)
7272 PM.add(createLoopAlignerPass());
7373
7474 switch (FileType) {
9393 /// finish up adding passes to emit the file, if necessary.
9494 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
9595 MachineCodeEmitter *MCE,
96 unsigned OptLevel) {
96 CodeGenOpt::Level OptLevel) {
9797 if (MCE)
9898 addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
9999
113113 ///
114114 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
115115 MachineCodeEmitter &MCE,
116 unsigned OptLevel) {
116 CodeGenOpt::Level OptLevel) {
117117 // Add common CodeGen passes.
118118 if (addCommonCodeGenPasses(PM, OptLevel))
119119 return true;
131131 return false; // success!
132132 }
133133
134 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
135 /// both emitting to assembly files or machine code output.
134 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
135 /// emitting to assembly files or machine code output.
136136 ///
137137 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
138 unsigned OptLevel) {
138 CodeGenOpt::Level OptLevel) {
139139 // Standard LLVM-Level Passes.
140140
141141 // Run loop strength reduction before anything else.
142 if (OptLevel != 0) {
142 if (OptLevel != CodeGenOpt::None) {
143143 PM.add(createLoopStrengthReducePass(getTargetLowering()));
144144 if (PrintLSR)
145145 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
153153 // Make sure that no unreachable blocks are instruction selected.
154154 PM.add(createUnreachableBlockEliminationPass());
155155
156 if (OptLevel != 0)
156 if (OptLevel != CodeGenOpt::None)
157157 PM.add(createCodeGenPreparePass(getTargetLowering()));
158158
159159 PM.add(createStackProtectorPass(getTargetLowering()));
167167
168168 // Enable FastISel with -fast, but allow that to be overridden.
169169 if (EnableFastISelOption == cl::BOU_TRUE ||
170 (OptLevel == 0 && EnableFastISelOption != cl::BOU_FALSE))
170 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
171171 EnableFastISel = true;
172172
173173 // Ask the target for an isel.
178178 if (PrintMachineCode)
179179 PM.add(createMachineFunctionPrinterPass(cerr));
180180
181 if (OptLevel != 0) {
181 if (OptLevel != CodeGenOpt::None) {
182182 PM.add(createMachineLICMPass());
183183 PM.add(createMachineSinkingPass());
184184 }
191191 PM.add(createRegisterAllocator());
192192
193193 // Perform stack slot coloring.
194 if (OptLevel != 0)
194 if (OptLevel != CodeGenOpt::None)
195195 PM.add(createStackSlotColoringPass());
196196
197197 if (PrintMachineCode) // Print the register-allocated code
216216 PM.add(createMachineFunctionPrinterPass(cerr));
217217
218218 // Second pass scheduler.
219 if (OptLevel != 0 && !DisablePostRAScheduler) {
219 if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
220220 PM.add(createPostRAScheduler());
221221
222222 if (PrintMachineCode)
224224 }
225225
226226 // Branch folding must be run after regalloc and prolog/epilog insertion.
227 if (OptLevel != 0)
227 if (OptLevel != CodeGenOpt::None)
228228 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
229229
230230 if (PrintMachineCode)
5656 SelectionDAG &DAG;
5757 const TargetLowering &TLI;
5858 CombineLevel Level;
59 unsigned OptLevel;
59 CodeGenOpt::Level OptLevel;
6060 bool LegalOperations;
6161 bool LegalTypes;
6262
253253 }
254254
255255 public:
256 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, unsigned OL)
256 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
257257 : DAG(D),
258258 TLI(D.getTargetLoweringInfo()),
259259 Level(Unrestricted),
47834783 SDValue Ptr = LD->getBasePtr();
47844784
47854785 // Try to infer better alignment information than the load already has.
4786 if (OptLevel != 0 && LD->isUnindexed()) {
4786 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
47874787 if (unsigned Align = InferAlignment(Ptr, DAG)) {
47884788 if (Align > LD->getAlignment())
47894789 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
49034903 SDValue Ptr = ST->getBasePtr();
49044904
49054905 // Try to infer better alignment information than the store already has.
4906 if (OptLevel != 0 && ST->isUnindexed()) {
4906 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
49074907 if (unsigned Align = InferAlignment(Ptr, DAG)) {
49084908 if (Align > ST->getAlignment())
49094909 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
60926092 // SelectionDAG::Combine - This is the entry point for the file.
60936093 //
60946094 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
6095 unsigned OptLevel) {
6095 CodeGenOpt::Level OptLevel) {
60966096 /// run - This is the main entry point to this class.
60976097 ///
60986098 DAGCombiner(*this, AA, OptLevel).Run(Level);
326326 default: break;
327327 case Intrinsic::dbg_stoppoint: {
328328 DbgStopPointInst *SPI = cast(I);
329 if (DW && DW->ValidDebugInfo(SPI->getContext(), 0)) {
329 if (DW && DW->ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) {
330330 DICompileUnit CU(cast(SPI->getContext()));
331331 std::string Dir, FN;
332332 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
343343 }
344344 case Intrinsic::dbg_region_start: {
345345 DbgRegionStartInst *RSI = cast(I);
346 if (DW && DW->ValidDebugInfo(RSI->getContext(), 0)) {
346 if (DW && DW->ValidDebugInfo(RSI->getContext(), CodeGenOpt::None)) {
347347 unsigned ID =
348348 DW->RecordRegionStart(cast(RSI->getContext()));
349349 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
353353 }
354354 case Intrinsic::dbg_region_end: {
355355 DbgRegionEndInst *REI = cast(I);
356 if (DW && DW->ValidDebugInfo(REI->getContext(), 0)) {
356 if (DW && DW->ValidDebugInfo(REI->getContext(), CodeGenOpt::None)) {
357357 unsigned ID = 0;
358358 DISubprogram Subprogram(cast(REI->getContext()));
359359 if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
379379 DbgFuncStartInst *FSI = cast(I);
380380 Value *SP = FSI->getSubprogram();
381381
382 if (DW->ValidDebugInfo(SP, 0)) {
382 if (DW->ValidDebugInfo(SP, CodeGenOpt::None)) {
383383 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
384384 // (most?) gdb expects.
385385 DebugLoc PrevLoc = DL;
424424 case Intrinsic::dbg_declare: {
425425 DbgDeclareInst *DI = cast(I);
426426 Value *Variable = DI->getVariable();
427 if (DW && DW->ValidDebugInfo(Variable, 0)) {
427 if (DW && DW->ValidDebugInfo(Variable, CodeGenOpt::None)) {
428428 // Determine the address of the declared object.
429429 Value *Address = DI->getAddress();
430430 if (BitCastInst *BCI = dyn_cast(Address))
5454 class VISIBILITY_HIDDEN SelectionDAGLegalize {
5555 TargetLowering &TLI;
5656 SelectionDAG &DAG;
57 unsigned OptLevel;
57 CodeGenOpt::Level OptLevel;
5858 bool TypesNeedLegalizing;
5959
6060 // Libcall insertion helpers.
138138
139139 public:
140140 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
141 unsigned ol);
141 CodeGenOpt::Level ol);
142142
143143 /// getTypeAction - Return how we should legalize values of this type, either
144144 /// it is already legal or we need to expand it into multiple registers of
349349 }
350350
351351 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
352 bool types, unsigned ol)
352 bool types, CodeGenOpt::Level ol)
353353 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
354354 TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) {
355355 assert(MVT::LAST_VALUETYPE <= 32 &&
12751275 unsigned Line = DSP->getLine();
12761276 unsigned Col = DSP->getColumn();
12771277
1278 if (OptLevel == 0) {
1278 if (OptLevel == CodeGenOpt::None) {
12791279 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
12801280 // won't hurt anything.
12811281 if (useDEBUG_LOC) {
85708570
85718571 // SelectionDAG::Legalize - This is the entry point for the file.
85728572 //
8573 void SelectionDAG::Legalize(bool TypesNeedLegalizing, unsigned OptLevel) {
8573 void SelectionDAG::Legalize(bool TypesNeedLegalizing,
8574 CodeGenOpt::Level OptLevel) {
85748575 /// run - This is the main entry point to this class.
85758576 ///
85768577 SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG();
629629 //===----------------------------------------------------------------------===//
630630
631631 llvm::ScheduleDAGSDNodes *
632 llvm::createFastDAGScheduler(SelectionDAGISel *IS, unsigned) {
632 llvm::createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
633633 return new ScheduleDAGFast(*IS->MF);
634634 }
260260 /// new hazard recognizer. This scheduler takes ownership of the hazard
261261 /// recognizer and deletes it when done.
262262 ScheduleDAGSDNodes *
263 llvm::createTDListDAGScheduler(SelectionDAGISel *IS, unsigned) {
263 llvm::createTDListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
264264 return new ScheduleDAGList(*IS->MF,
265265 new LatencyPriorityQueue(),
266266 IS->CreateTargetHazardRecognizer());
15041504 //===----------------------------------------------------------------------===//
15051505
15061506 llvm::ScheduleDAGSDNodes *
1507 llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
1507 llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
15081508 const TargetMachine &TM = IS->TM;
15091509 const TargetInstrInfo *TII = TM.getInstrInfo();
15101510 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
15181518 }
15191519
15201520 llvm::ScheduleDAGSDNodes *
1521 llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, unsigned) {
1521 llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
15221522 const TargetMachine &TM = IS->TM;
15231523 const TargetInstrInfo *TII = TM.getInstrInfo();
15241524 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
4444 #include "llvm/Target/TargetInstrInfo.h"
4545 #include "llvm/Target/TargetIntrinsicInfo.h"
4646 #include "llvm/Target/TargetLowering.h"
47 #include "llvm/Target/TargetMachine.h"
4847 #include "llvm/Target/TargetOptions.h"
4948 #include "llvm/Support/Compiler.h"
5049 #include "llvm/Support/CommandLine.h"
334333 DwarfWriter *DW = DAG.getDwarfWriter();
335334 DbgStopPointInst *SPI = cast(I);
336335
337 if (DW && DW->ValidDebugInfo(SPI->getContext(), false)) {
336 if (DW && DW->ValidDebugInfo(SPI->getContext(),
337 CodeGenOpt::Default)) {
338338 DICompileUnit CU(cast(SPI->getContext()));
339339 std::string Dir, FN;
340340 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
353353 DbgFuncStartInst *FSI = cast(I);
354354 Value *SP = FSI->getSubprogram();
355355
356 if (DW->ValidDebugInfo(SP, false)) {
356 if (DW->ValidDebugInfo(SP, CodeGenOpt::Default)) {
357357 DISubprogram Subprogram(cast(SP));
358358 DICompileUnit CU(Subprogram.getCompileUnit());
359359 std::string Dir, FN;
38983898 DbgStopPointInst &SPI = cast(I);
38993899 if (DW && DW->ValidDebugInfo(SPI.getContext(), OptLevel)) {
39003900 MachineFunction &MF = DAG.getMachineFunction();
3901 if (OptLevel == 0)
3901 if (OptLevel == CodeGenOpt::None)
39023902 DAG.setRoot(DAG.getDbgStopPoint(getRoot(),
39033903 SPI.getLine(),
39043904 SPI.getColumn(),
39393939 && strcmp(SPName.c_str(), MF.getFunction()->getNameStart())) {
39403940 // This is end of inlined function. Debugging information for
39413941 // inlined function is not handled yet (only supported by FastISel).
3942 if (OptLevel == 0) {
3942 if (OptLevel == CodeGenOpt::None) {
39433943 unsigned ID = DW->RecordInlinedFnEnd(Subprogram);
39443944 if (ID != 0)
39453945 // Returned ID is 0 if this is unbalanced "end of inlined
39673967 Value *SP = FSI.getSubprogram();
39683968 if (SP && DW->ValidDebugInfo(SP, OptLevel)) {
39693969 MachineFunction &MF = DAG.getMachineFunction();
3970 if (OptLevel == 0) {
3970 if (OptLevel == CodeGenOpt::None) {
39713971 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
39723972 // (most?) gdb expects.
39733973 DebugLoc PrevLoc = CurDebugLoc;
40384038 return 0;
40394039 }
40404040 case Intrinsic::dbg_declare: {
4041 if (OptLevel == 0) {
4041 if (OptLevel == CodeGenOpt::None) {
40424042 DwarfWriter *DW = DAG.getDwarfWriter();
40434043 DbgDeclareInst &DI = cast(I);
40444044 Value *Variable = DI.getVariable();
2222 #include "llvm/CodeGen/SelectionDAGNodes.h"
2323 #include "llvm/CodeGen/ValueTypes.h"
2424 #include "llvm/Support/CallSite.h"
25 #include "llvm/Target/TargetMachine.h"
2526 #include
2627 #include
2728
356357
357358 /// OptLevel - What optimization level we're generating code for.
358359 ///
359 unsigned OptLevel;
360 CodeGenOpt::Level OptLevel;
360361
361362 /// GFI - Garbage collection metadata for the function.
362363 GCFunctionInfo *GFI;
363364
364365 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
365 FunctionLoweringInfo &funcinfo, unsigned ol)
366 FunctionLoweringInfo &funcinfo,
367 CodeGenOpt::Level ol)
366368 : CurDebugLoc(DebugLoc::getUnknownLoc()),
367369 TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol) {
368370 }
135135 /// createDefaultScheduler - This creates an instruction scheduler appropriate
136136 /// for the target.
137137 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
138 unsigned OptLevel) {
138 CodeGenOpt::Level OptLevel) {
139139 const TargetLowering &TLI = IS->getTargetLowering();
140140
141 if (OptLevel == 0)
141 if (OptLevel == CodeGenOpt::None)
142142 return createFastDAGScheduler(IS, OptLevel);
143143 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency)
144144 return createTDListDAGScheduler(IS, OptLevel);
261261 // SelectionDAGISel code
262262 //===----------------------------------------------------------------------===//
263263
264 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, unsigned OL) :
264 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, CodeGenOpt::Level OL) :
265265 FunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
266266 FuncInfo(new FunctionLoweringInfo(TLI)),
267267 CurDAG(new SelectionDAG(TLI, *FuncInfo)),
644644
645645 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
646646
647 if (OptLevel != 0)
647 if (OptLevel != CodeGenOpt::None)
648648 ComputeLiveOutVRegInfo();
649649
650650 // Third, instruction select all of the operations to machine code, adding the
382382 ExecutionEngine *ExecutionEngine::create(ModuleProvider *MP,
383383 bool ForceInterpreter,
384384 std::string *ErrorStr,
385 unsigned OptLevel) {
385 CodeGenOpt::Level OptLevel) {
386386 ExecutionEngine *EE = 0;
387387
388388 // Make sure we can resolve symbols in the program as well. The zero arg
113113
114114 int LLVMCreateJITCompiler(LLVMExecutionEngineRef *OutJIT,
115115 LLVMModuleProviderRef MP,
116 unsigned OptLevel,
116 CodeGenOpt::Level OptLevel,
117117 char **OutError) {
118118 std::string Error;
119119 if (ExecutionEngine *JIT = ExecutionEngine::createJIT(unwrap(MP), &Error, 0,
3636 /// create - Create a new interpreter object. This can never fail.
3737 ///
3838 ExecutionEngine *Interpreter::create(ModuleProvider *MP, std::string* ErrStr,
39 unsigned OptLevel /*unused*/) {
39 CodeGenOpt::Level OptLevel /*unused*/) {
4040 // Tell this ModuleProvide to materialize and release the module
4141 if (!MP->materializeModule(ErrStr))
4242 // We got an error, just return 0
107107 /// create - Create an interpreter ExecutionEngine. This can never fail.
108108 ///
109109 static ExecutionEngine *create(ModuleProvider *M, std::string *ErrorStr = 0,
110 unsigned OptLevel /*unused*/ = 3);
110 CodeGenOpt::Level = CodeGenOpt::Default);
111111
112112 /// run - Start execution with the specified function and arguments.
113113 ///
195195 ExecutionEngine *ExecutionEngine::createJIT(ModuleProvider *MP,
196196 std::string *ErrorStr,
197197 JITMemoryManager *JMM,
198 unsigned OptLevel) {
198 CodeGenOpt::Level OptLevel) {
199199 ExecutionEngine *EE = JIT::createJIT(MP, ErrorStr, JMM, OptLevel);
200200 if (!EE) return 0;
201201
206206 }
207207
208208 JIT::JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
209 JITMemoryManager *JMM, unsigned OptLevel)
209 JITMemoryManager *JMM, CodeGenOpt::Level OptLevel)
210210 : ExecutionEngine(MP), TM(tm), TJI(tji) {
211211 setTargetData(TM.getTargetData());
212212
271271
272272 // Turn the machine code intermediate representation into bytes in memory
273273 // that may be executed.
274 if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
274 if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) {
275275 cerr << "Target does not support machine code emission!\n";
276276 abort();
277277 }
304304
305305 // Turn the machine code intermediate representation into bytes in memory
306306 // that may be executed.
307 if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
307 if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) {
308308 cerr << "Target does not support machine code emission!\n";
309309 abort();
310310 }
336336
337337 // Turn the machine code intermediate representation into bytes in memory
338338 // that may be executed.
339 if (TM.addPassesToEmitMachineCode(PM, *MCE, 3 /* OptLevel */)) {
339 if (TM.addPassesToEmitMachineCode(PM, *MCE, CodeGenOpt::Default)) {
340340 cerr << "Target does not support machine code emission!\n";
341341 abort();
342342 }
5454 JITState *jitstate;
5555
5656 JIT(ModuleProvider *MP, TargetMachine &tm, TargetJITInfo &tji,
57 JITMemoryManager *JMM, unsigned OptLevel);
57 JITMemoryManager *JMM, CodeGenOpt::Level OptLevel);
5858 public:
5959 ~JIT();
6060
7070 /// for the current target. Otherwise, return null.
7171 ///
7272 static ExecutionEngine *create(ModuleProvider *MP, std::string *Err,
73 unsigned OptLevel = 3) {
73 CodeGenOpt::Level OptLevel =
74 CodeGenOpt::Default) {
7475 return createJIT(MP, Err, 0, OptLevel);
7576 }
7677
147148 MachineCodeEmitter *getCodeEmitter() const { return MCE; }
148149
149150 static ExecutionEngine *createJIT(ModuleProvider *MP, std::string *Err,
150 JITMemoryManager *JMM, unsigned OptLevel);
151 JITMemoryManager *JMM,
152 CodeGenOpt::Level OptLevel);
151153
152154 private:
153155 static MachineCodeEmitter *createEmitter(JIT &J, JITMemoryManager *JMM);
4141 /// available for the current target. Otherwise, return null.
4242 ///
4343 ExecutionEngine *JIT::createJIT(ModuleProvider *MP, std::string *ErrorStr,
44 JITMemoryManager *JMM, unsigned OptLevel) {
44 JITMemoryManager *JMM,
45 CodeGenOpt::Level OptLevel) {
4546 const TargetMachineRegistry::entry *TheArch = MArch;
4647 if (TheArch == 0) {
4748 std::string Error;
1414 #ifndef TARGET_ARM_H
1515 #define TARGET_ARM_H
1616
17 #include "llvm/Target/TargetMachine.h"
1718 #include
1819
1920 namespace llvm {
9091 FunctionPass *createARMISelDag(ARMTargetMachine &TM);
9192 FunctionPass *createARMCodePrinterPass(raw_ostream &O,
9293 ARMTargetMachine &TM,
93 unsigned OptLevel, bool Verbose);
94 CodeGenOpt::Level OptLevel,
95 bool Verbose);
9496 FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
9597 MachineCodeEmitter &MCE);
9698 FunctionPass *createARMLoadStoreOptimizationPass();
137137
138138
139139 // Pass Pipeline Configuration
140 bool ARMTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
140 bool ARMTargetMachine::addInstSelector(PassManagerBase &PM,
141 CodeGenOpt::Level OptLevel) {
141142 PM.add(createARMISelDag(*this));
142143 return false;
143144 }
144145
145 bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
146 bool ARMTargetMachine::addPreEmitPass(PassManagerBase &PM,
147 CodeGenOpt::Level OptLevel) {
146148 // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
147 if (OptLevel != 0 && !DisableLdStOpti && !Subtarget.isThumb())
149 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
148150 PM.add(createARMLoadStoreOptimizationPass());
149151
150 if (OptLevel != 0 && !DisableIfConversion && !Subtarget.isThumb())
152 if (OptLevel != CodeGenOpt::None &&
153 !DisableIfConversion && !Subtarget.isThumb())
151154 PM.add(createIfConverterPass());
152155
153156 PM.add(createARMConstantIslandPass());
155158 }
156159
157160 bool ARMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
158 unsigned OptLevel,
161 CodeGenOpt::Level OptLevel,
159162 bool Verbose,
160163 raw_ostream &Out) {
161164 // Output assembly language.
167170 }
168171
169172
170 bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
171 bool DumpAsm, MachineCodeEmitter &MCE) {
173 bool ARMTargetMachine::addCodeEmitter(PassManagerBase &PM,
174 CodeGenOpt::Level OptLevel,
175 bool DumpAsm,
176 MachineCodeEmitter &MCE) {
172177 // FIXME: Move this to TargetJITInfo!
173178 if (DefRelocModel == Reloc::Default)
174179 setRelocationModel(Reloc::Static);
185190 }
186191
187192 bool ARMTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
188 unsigned OptLevel,
193 CodeGenOpt::Level OptLevel,
189194 bool DumpAsm,
190195 MachineCodeEmitter &MCE) {
191196 // Machine code emitter pass for ARM.
4040 // set this functions to ctor pointer at startup time if they are linked in.
4141 typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
4242 ARMTargetMachine &tm,
43 unsigned OptLevel, bool verbose);
43 CodeGenOpt::Level OptLevel,
44 bool verbose);
4445 static AsmPrinterCtorFn AsmPrinterCtor;
4546
4647 public:
6869 virtual const TargetAsmInfo *createTargetAsmInfo() const;
6970
7071 // Pass Pipeline Configuration
71 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
72 virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
73 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
72 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
73 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
74 virtual bool addAssemblyEmitter(PassManagerBase &PM,
75 CodeGenOpt::Level OptLevel,
7476 bool Verbose, raw_ostream &Out);
75 virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
77 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
7678 bool DumpAsm, MachineCodeEmitter &MCE);
77 virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
78 bool DumpAsm, MachineCodeEmitter &MCE);
79 virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
80 CodeGenOpt::Level OptLevel,
81 bool DumpAsm,
82 MachineCodeEmitter &MCE);
7983 };
8084
8185 /// ThumbTargetMachine - Thumb target machine.
8080 bool InCPMode;
8181 public:
8282 explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
83 const TargetAsmInfo *T, unsigned OL, bool V)
83 const TargetAsmInfo *T, CodeGenOpt::Level OL,
84 bool V)
8485 : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(NULL), AFI(NULL), MCP(NULL),
8586 InCPMode(false) {
8687 Subtarget = &TM.getSubtarget();
10601061 ///
10611062 FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
10621063 ARMTargetMachine &tm,
1063 unsigned OptLevel, bool verbose) {
1064 CodeGenOpt::Level OptLevel,
1065 bool verbose) {
10641066 return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
10651067 }
10661068
1414 #ifndef TARGET_ALPHA_H
1515 #define TARGET_ALPHA_H
1616
17 #include "llvm/Target/TargetMachine.h"
18
1719 namespace llvm {
1820
1921 class AlphaTargetMachine;
2022 class FunctionPass;
21 class TargetMachine;
2223 class MachineCodeEmitter;
2324 class raw_ostream;
2425
2526 FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
2627 FunctionPass *createAlphaCodePrinterPass(raw_ostream &OS,
2728 TargetMachine &TM,
28 unsigned OptLevel, bool Verbose);
29 CodeGenOpt::Level OptLevel,
30 bool Verbose);
2931 FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
3032 FunctionPass *createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
3133 MachineCodeEmitter &MCE);
7676 //===----------------------------------------------------------------------===//
7777
7878 bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
79 unsigned OptLevel) {
79 CodeGenOpt::Level OptLevel) {
8080 PM.add(createAlphaISelDag(*this));
8181 return false;
8282 }
8383 bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
84 unsigned OptLevel) {
84 CodeGenOpt::Level OptLevel) {
8585 // Must run branch selection immediately preceding the asm printer
8686 PM.add(createAlphaBranchSelectionPass());
8787 return false;
8888 }
8989 bool AlphaTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
90 unsigned OptLevel,
90 CodeGenOpt::Level OptLevel,
9191 bool Verbose,
9292 raw_ostream &Out) {
9393 PM.add(createAlphaLLRPPass(*this));
9494 PM.add(createAlphaCodePrinterPass(Out, *this, OptLevel, Verbose));
9595 return false;
9696 }
97 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
97 bool AlphaTargetMachine::addCodeEmitter(PassManagerBase &PM,
98 CodeGenOpt::Level OptLevel,
9899 bool DumpAsm, MachineCodeEmitter &MCE) {
99100 PM.add(createAlphaCodeEmitterPass(*this, MCE));
100101 if (DumpAsm)
102103 return false;
103104 }
104105 bool AlphaTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
105 unsigned OptLevel, bool DumpAsm,
106 CodeGenOpt::Level OptLevel,
107 bool DumpAsm,
106108 MachineCodeEmitter &MCE) {
107109 return addCodeEmitter(PM, OptLevel, DumpAsm, MCE);
108110 }
5757 static unsigned getModuleMatchQuality(const Module &M);
5858
5959 // Pass Pipeline Configuration
60 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
61 virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
62 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
60 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
61 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
62 virtual bool addAssemblyEmitter(PassManagerBase &PM,
63 CodeGenOpt::Level OptLevel,
6364 bool Verbose, raw_ostream &Out);
64 virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
65 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
6566 bool DumpAsm, MachineCodeEmitter &MCE);
66 virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
67 bool DumpAsm, MachineCodeEmitter &MCE);
67 virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
68 CodeGenOpt::Level OptLevel,
69 bool DumpAsm,
70 MachineCodeEmitter &MCE);
6871 };
6972
7073 } // end namespace llvm
3636 ///
3737
3838 explicit AlphaAsmPrinter(raw_ostream &o, TargetMachine &tm,
39 const TargetAsmInfo *T, unsigned OL, bool V)
39 const TargetAsmInfo *T, CodeGenOpt::Level OL,
40 bool V)
4041 : AsmPrinter(o, tm, T, OL, V) {}
4142
4243 virtual const char *getPassName() const {
6768 ///
6869 FunctionPass *llvm::createAlphaCodePrinterPass(raw_ostream &o,
6970 TargetMachine &tm,
70 unsigned OptLevel,
71 CodeGenOpt::Level OptLevel,
7172 bool verbose) {
7273 return new AlphaAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
7374 }
35863586 bool CTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
35873587 raw_ostream &o,
35883588 CodeGenFileType FileType,
3589 unsigned OptLevel) {
3589 CodeGenOpt::Level OptLevel) {
35903590 if (FileType != TargetMachine::AssemblyFile) return true;
35913591
35923592 PM.add(createGCLoweringPass());
2727 virtual bool WantsWholeFile() const { return true; }
2828 virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
2929 CodeGenFileType FileType,
30 unsigned OptLevel);
30 CodeGenOpt::Level OptLevel);
3131
3232 // This class always works, but must be requested explicitly on
3333 // llc command line.
4848 std::set FnStubs, GVStubs;
4949 public:
5050 explicit SPUAsmPrinter(raw_ostream &O, TargetMachine &TM,
51 const TargetAsmInfo *T, unsigned OL, bool V) :
51 const TargetAsmInfo *T, CodeGenOpt::Level OL,
52 bool V) :
5253 AsmPrinter(O, TM, T, OL, V) {}
5354
5455 virtual const char *getPassName() const {
287288 DwarfWriter *DW;
288289 MachineModuleInfo *MMI;
289290 public:
290 LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
291 const TargetAsmInfo *T, bool F, bool V)
291 explicit LinuxAsmPrinter(raw_ostream &O, SPUTargetMachine &TM,
292 const TargetAsmInfo *T, CodeGenOpt::Level F,
293 bool V)
292294 : SPUAsmPrinter(O, TM, T, F, V), DW(0), MMI(0) {}
293295
294296 virtual const char *getPassName() const {
614616 ///
615617 FunctionPass *llvm::createSPUAsmPrinterPass(raw_ostream &o,
616618 SPUTargetMachine &tm,
617 unsigned OptLevel, bool verbose) {
619 CodeGenOpt::Level OptLevel,
620 bool verbose) {
618621 return new LinuxAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
619622 }
1515 #define LLVM_TARGET_IBMCELLSPU_H
1616
1717 #include "llvm/Support/DataTypes.h"
18 #include "llvm/Target/TargetMachine.h"
1819
1920 namespace llvm {
2021 class SPUTargetMachine;
2425 FunctionPass *createSPUISelDag(SPUTargetMachine &TM);
2526 FunctionPass *createSPUAsmPrinterPass(raw_ostream &o,
2627 SPUTargetMachine &tm,
27 unsigned OptLevel, bool verbose);
28 CodeGenOpt::Level OptLevel,
29 bool verbose);
2830
2931 /*--== Utility functions/predicates/etc used all over the place: --==*/
3032 //! Predicate test for a signed 10-bit value
8080 //===----------------------------------------------------------------------===//
8181
8282 bool
83 SPUTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel)
83 SPUTargetMachine::addInstSelector(PassManagerBase &PM,
84 CodeGenOpt::Level OptLevel)
8485 {
8586 // Install an instruction selector.
8687 PM.add(createSPUISelDag(*this));
8889 }
8990
9091 bool SPUTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
91 unsigned OptLevel,
92 CodeGenOpt::Level OptLevel,
9293 bool Verbose,
9394 raw_ostream &Out) {
9495 PM.add(createSPUAsmPrinterPass(Out, *this, OptLevel, Verbose));
8282 }
8383
8484 // Pass Pipeline Configuration
85 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
86 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
85 virtual bool addInstSelector(PassManagerBase &PM,
86 CodeGenOpt::Level OptLevel);
87 virtual bool addAssemblyEmitter(PassManagerBase &PM,
88 CodeGenOpt::Level OptLevel,
8789 bool Verbose, raw_ostream &Out);
8890 };
8991
19941994 bool CPPTargetMachine::addPassesToEmitWholeFile(PassManager &PM,
19951995 raw_ostream &o,
19961996 CodeGenFileType FileType,
1997 unsigned OptLevel) {
1997 CodeGenOpt::Level OptLevel) {
19981998 if (FileType != TargetMachine::AssemblyFile) return true;
19991999 PM.add(new CppWriter(o));
20002000 return false;
2929 virtual bool WantsWholeFile() const { return true; }
3030 virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
3131 CodeGenFileType FileType,
32 unsigned OptLevel);
32 CodeGenOpt::Level OptLevel);
3333
3434 // This class always works, but shouldn't be the default in most cases.
3535 static unsigned getModuleMatchQuality(const Module &M) { return 1; }
2424 #include "llvm/CodeGen/DwarfWriter.h"
2525 #include "llvm/CodeGen/MachineFunctionPass.h"
2626 #include "llvm/Target/TargetAsmInfo.h"
27 #include "llvm/Target/TargetMachine.h"
2827 #include "llvm/Support/Mangler.h"
2928 #include "llvm/Support/raw_ostream.h"
3029 #include "llvm/ADT/Statistic.h"
3736 std::set ExternalFunctionNames, ExternalObjectNames;
3837 public:
3938 explicit IA64AsmPrinter(raw_ostream &O, TargetMachine &TM,
40 const TargetAsmInfo *T, unsigned OL, bool V)
39 const TargetAsmInfo *T, CodeGenOpt::Level OL,
40 bool V)
4141 : AsmPrinter(O, TM, T, OL, V) {}
4242
4343 virtual const char *getPassName() const {
369369 ///
370370 FunctionPass *llvm::createIA64CodePrinterPass(raw_ostream &o,
371371 IA64TargetMachine &tm,
372 unsigned OptLevel,
372 CodeGenOpt::Level OptLevel,
373373 bool verbose) {
374374 return new IA64AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
375375 }
1212
1313 #ifndef TARGET_IA64_H
1414 #define TARGET_IA64_H
15
16 #include "llvm/Target/TargetMachine.h"
1517
1618 namespace llvm {
1719
3638 ///
3739 FunctionPass *createIA64CodePrinterPass(raw_ostream &o,
3840 IA64TargetMachine &tm,
39 unsigned OptLevel, bool verbose);
41 CodeGenOpt::Level OptLevel,
42 bool verbose);
4043
4144 } // End llvm namespace
4245
7171 // Pass Pipeline Configuration
7272 //===----------------------------------------------------------------------===//
7373
74 bool IA64TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLEvel){
74 bool IA64TargetMachine::addInstSelector(PassManagerBase &PM,
75 CodeGenOpt::Level OptLevel){
7576 PM.add(createIA64DAGToDAGInstructionSelector(*this));
7677 return false;
7778 }
7879
79 bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
80 bool IA64TargetMachine::addPreEmitPass(PassManagerBase &PM,
81 CodeGenOpt::Level OptLevel) {
8082 // Make sure everything is bundled happily
8183 PM.add(createIA64BundlingPass(*this));
8284 return true;
8385 }
8486 bool IA64TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
85 unsigned OptLevel,
87 CodeGenOpt::Level OptLevel,
8688 bool Verbose,
8789 raw_ostream &Out) {
8890 PM.add(createIA64CodePrinterPass(Out, *this, OptLevel, Verbose));
5050 static unsigned getModuleMatchQuality(const Module &M);
5151
5252 // Pass Pipeline Configuration
53 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
54 virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
55 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
53 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55 virtual bool addAssemblyEmitter(PassManagerBase &PM,
56 CodeGenOpt::Level OptLevel,
5657 bool Verbose, raw_ostream &Out);
5758 };
5859 } // End llvm namespace
3535 virtual bool WantsWholeFile() const { return true; }
3636 virtual bool addPassesToEmitWholeFile(PassManager &PM, raw_ostream &Out,
3737 CodeGenFileType FileType,
38 unsigned OptLevel);
38 CodeGenOpt::Level OptLevel);
3939
4040 // This class always works, but shouldn't be the default in most cases.
4141 static unsigned getModuleMatchQuality(const Module &M) { return 1; }
16631663
16641664 bool MSILTarget::addPassesToEmitWholeFile(PassManager &PM, raw_ostream &o,
16651665 CodeGenFileType FileType,
1666 unsigned OptLevel)
1666 CodeGenOpt::Level OptLevel)
16671667 {
16681668 if (FileType != TargetMachine::AssemblyFile) return true;
16691669 MSILWriter* Writer = new MSILWriter(o);
4949 const MipsSubtarget *Subtarget;
5050 public:
5151 explicit MipsAsmPrinter(raw_ostream &O, MipsTargetMachine &TM,
52 const TargetAsmInfo *T, unsigned OL, bool V)
52 const TargetAsmInfo *T, CodeGenOpt::Level OL,
53 bool V)
5354 : AsmPrinter(O, TM, T, OL, V) {
5455 Subtarget = &TM.getSubtarget();
5556 }
9091 /// regardless of whether the function is in SSA form.
9192 FunctionPass *llvm::createMipsCodePrinterPass(raw_ostream &o,
9293 MipsTargetMachine &tm,
93 unsigned OptLevel, bool verbose) {
94 CodeGenOpt::Level OptLevel,
95 bool verbose) {
9496 return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
9597 }
9698
1414 #ifndef TARGET_MIPS_H
1515 #define TARGET_MIPS_H
1616
17 #include "llvm/Target/TargetMachine.h"
18
1719 namespace llvm {
1820 class MipsTargetMachine;
1921 class FunctionPass;
2426 FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM);
2527 FunctionPass *createMipsCodePrinterPass(raw_ostream &OS,
2628 MipsTargetMachine &TM,
27 unsigned OptLevel, bool Verbose);
29 CodeGenOpt::Level OptLevel,
30 bool Verbose);
2831 } // end namespace llvm;
2932
3033 // Defines symbolic names for Mips registers. This defines a mapping from
104104 // Install an instruction selector pass using
105105 // the ISelDag to gen Mips code.
106106 bool MipsTargetMachine::
107 addInstSelector(PassManagerBase &PM, unsigned OptLevel)
107 addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
108108 {
109109 PM.add(createMipsISelDag(*this));
110110 return false;
114114 // machine code is emitted. return true if -print-machineinstrs should
115115 // print out the code after the passes.
116116 bool MipsTargetMachine::
117 addPreEmitPass(PassManagerBase &PM, unsigned OptLevel)
117 addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel)
118118 {
119119 PM.add(createMipsDelaySlotFillerPass(*this));
120120 return true;
123123 // Implements the AssemblyEmitter for the target. Must return
124124 // true if AssemblyEmitter is supported
125125 bool MipsTargetMachine::
126 addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
126 addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
127127 bool Verbose, raw_ostream &Out)
128128 {
129129 // Output assembly language.
5656 static unsigned getModuleMatchQuality(const Module &M);
5757
5858 // Pass Pipeline Configuration
59 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
60 virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
61 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
59 virtual bool addInstSelector(PassManagerBase &PM,
60 CodeGenOpt::Level OptLevel);
61 virtual bool addPreEmitPass(PassManagerBase &PM,
62 CodeGenOpt::Level OptLevel);
63 virtual bool addAssemblyEmitter(PassManagerBase &PM,
64 CodeGenOpt::Level OptLevel,
6265 bool Verbose, raw_ostream &Out);
6366 };
6467
1414 #ifndef LLVM_TARGET_PIC16_H
1515 #define LLVM_TARGET_PIC16_H
1616
17 #include "llvm/Target/TargetMachine.h"
1718 #include
1819 #include
1920
7475 FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
7576 FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
7677 PIC16TargetMachine &TM,
77 unsigned OptLevel, bool Verbose);
78 CodeGenOpt::Level OptLevel,
79 bool Verbose);
7880 } // end namespace llvm;
7981
8082 // Defines symbolic names for PIC16 registers. This defines a mapping from
160160 ///
161161 FunctionPass *llvm::createPIC16CodePrinterPass(raw_ostream &o,
162162 PIC16TargetMachine &tm,
163 unsigned OptLevel,
163 CodeGenOpt::Level OptLevel,
164164 bool verbose) {
165165 return new PIC16AsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
166166 }
2424 namespace llvm {
2525 struct VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter {
2626 explicit PIC16AsmPrinter(raw_ostream &O, PIC16TargetMachine &TM,
27 const TargetAsmInfo *T, unsigned OL, bool V)
27 const TargetAsmInfo *T, CodeGenOpt::Level OL,
28 bool V)
2829 : AsmPrinter(O, TM, T, OL, V) {
2930 CurBank = "";
3031 FunctionLabelBegin = '@';
5555 }
5656
5757 bool PIC16TargetMachine::addInstSelector(PassManagerBase &PM,
58 unsigned OptLevel) {
58 CodeGenOpt::Level OptLevel) {
5959 // Install an instruction selector.
6060 PM.add(createPIC16ISelDag(*this));
6161 return false;
6262 }
6363
6464 bool PIC16TargetMachine::
65 addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel, bool Verbose,
66 raw_ostream &Out) {
65 addAssemblyEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
66 bool Verbose, raw_ostream &Out) {
6767 // Output assembly language.
6868 PM.add(createPIC16CodePrinterPass(Out, *this, OptLevel, Verbose));
6969 return false;
5656 return const_cast(&TLInfo);
5757 }
5858
59 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
60 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
59 virtual bool addInstSelector(PassManagerBase &PM,
60 CodeGenOpt::Level OptLevel);
61 virtual bool addAssemblyEmitter(PassManagerBase &PM,
62 CodeGenOpt::Level OptLevel,
6163 bool Verbose, raw_ostream &Out);
6264 }; // PIC16TargetMachine.
6365
5454 const PPCSubtarget &Subtarget;
5555 public:
5656 explicit PPCAsmPrinter(raw_ostream &O, TargetMachine &TM,
57 const TargetAsmInfo *T, unsigned OL, bool V)
57 const TargetAsmInfo *T, CodeGenOpt::Level OL,
58 bool V)
5859 : AsmPrinter(O, TM, T, OL, V),
5960 Subtarget(TM.getSubtarget()) {}
6061
297298 MachineModuleInfo *MMI;
298299 public:
299300 explicit PPCLinuxAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
300 const TargetAsmInfo *T, unsigned OL, bool V)
301 const TargetAsmInfo *T, CodeGenOpt::Level OL,
302 bool V)
301303 : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {}
302304
303305 virtual const char *getPassName() const {
326328 raw_ostream &OS;
327329 public:
328330 explicit PPCDarwinAsmPrinter(raw_ostream &O, PPCTargetMachine &TM,
329 const TargetAsmInfo *T, unsigned OL, bool V)
331 const TargetAsmInfo *T, CodeGenOpt::Level OL,
332 bool V)
330333 : PPCAsmPrinter(O, TM, T, OL, V), DW(0), MMI(0), OS(O) {}
331334
332335 virtual const char *getPassName() const {
11751178 ///
11761179 FunctionPass *llvm::createPPCAsmPrinterPass(raw_ostream &o,
11771180 PPCTargetMachine &tm,
1178 unsigned OptLevel, bool verbose) {
1181 CodeGenOpt::Level OptLevel,
1182 bool verbose) {
11791183 const PPCSubtarget *Subtarget = &tm.getSubtarget();
11801184
11811185 if (Subtarget->isDarwin()) {
1717 // GCC #defines PPC on Linux but we use it as our namespace name
1818 #undef PPC
1919
20 #include "llvm/Target/TargetMachine.h"
21
2022 namespace llvm {
2123 class PPCTargetMachine;
2224 class FunctionPass;
2729 FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
2830 FunctionPass *createPPCAsmPrinterPass(raw_ostream &OS,
2931 PPCTargetMachine &TM,
30 unsigned OptLevel, bool Verbose);
32 CodeGenOpt::Level OptLevel, bool Verbose);
3133 FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
3234 MachineCodeEmitter &MCE);
3335 } // end namespace llvm;
128128 // Pass Pipeline Configuration
129129 //===----------------------------------------------------------------------===//
130130
131 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
131 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
132 CodeGenOpt::Level OptLevel) {
132133 // Install an instruction selector.
133134 PM.add(createPPCISelDag(*this));
134135 return false;
135136 }
136137
137 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel) {
138
138 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
139 CodeGenOpt::Level OptLevel) {
139140 // Must run branch selection immediately preceding the asm printer.
140141 PM.add(createPPCBranchSelectionPass());
141142 return false;
142143 }
143144
144145 bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
145 unsigned OptLevel,
146 CodeGenOpt::Level OptLevel,
146147 bool Verbose,
147148 raw_ostream &Out) {
148149 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
152153 return false;
153154 }
154155
155 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
156 bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
157 CodeGenOpt::Level OptLevel,
156158 bool DumpAsm, MachineCodeEmitter &MCE) {
157159 // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
158160 // FIXME: This should be moved to TargetJITInfo!!
183185 return false;
184186 }
185187
186 bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
188 bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
189 CodeGenOpt::Level OptLevel,
187190 bool DumpAsm, MachineCodeEmitter &MCE) {
188191 // Machine code emitter pass for PowerPC.
189192 PM.add(createPPCCodeEmitterPass(*this, MCE));
4545 // set this functions to ctor pointer at startup time if they are linked in.
4646 typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
4747 PPCTargetMachine &tm,
48 unsigned OptLevel, bool verbose);
48 CodeGenOpt::Level OptLevel,
49 bool verbose);
4950 static AsmPrinterCtorFn AsmPrinterCtor;
5051
5152 public:
7576 }
7677
7778 // Pass Pipeline Configuration
78 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
79 virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
80 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
79 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
80 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
81 virtual bool addAssemblyEmitter(PassManagerBase &PM,
82 CodeGenOpt::Level OptLevel,
8183 bool Verbose, raw_ostream &Out);
82 virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
84 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
8385 bool DumpAsm, MachineCodeEmitter &MCE);
84 virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
86 virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
87 CodeGenOpt::Level OptLevel,
8588 bool DumpAsm, MachineCodeEmitter &MCE);
8689 virtual bool getEnableTailMergeDefault() const;
8790 };
4848 ValueMapTy NumberForBB;
4949 public:
5050 explicit SparcAsmPrinter(raw_ostream &O, TargetMachine &TM,
51 const TargetAsmInfo *T, unsigned OL, bool V)
51 const TargetAsmInfo *T, CodeGenOpt::Level OL,
52 bool V)
5253 : AsmPrinter(O, TM, T, OL, V) {}
5354
5455 virtual const char *getPassName() const {
8182 ///
8283 FunctionPass *llvm::createSparcCodePrinterPass(raw_ostream &o,
8384 TargetMachine &tm,
84 unsigned OptLevel,
85 CodeGenOpt::Level OptLevel,
8586 bool verbose) {
8687 return new SparcAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
8788 }
1414 #ifndef TARGET_SPARC_H
1515 #define TARGET_SPARC_H
1616
17 #include "llvm/Target/TargetMachine.h"
1718 #include
1819
1920 namespace llvm {
2021 class FunctionPass;
21 class TargetMachine;
2222 class SparcTargetMachine;
2323 class raw_ostream;
2424
2525 FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
2626 FunctionPass *createSparcCodePrinterPass(raw_ostream &OS, TargetMachine &TM,
27 unsigned OptLevel, bool Verbose);
27 CodeGenOpt::Level OptLevel,
28 bool Verbose);
2829 FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
2930 FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
3031 } // end namespace llvm;
6868 }
6969
7070 bool SparcTargetMachine::addInstSelector(PassManagerBase &PM,
71 unsigned OptLevel) {
71 CodeGenOpt::Level OptLevel) {
7272 PM.add(createSparcISelDag(*this));
7373 return false;
7474 }
7676 /// addPreEmitPass - This pass may be implemented by targets that want to run
7777 /// passes immediately before machine code is emitted. This should return
7878 /// true if -print-machineinstrs should print out the code after the passes.
79 bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, unsigned OptLevel){
79 bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM,
80 CodeGenOpt::Level OptLevel){
8081 PM.add(createSparcFPMoverPass(*this));
8182 PM.add(createSparcDelaySlotFillerPass(*this));
8283 return true;
8384 }
8485
8586 bool SparcTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
86 unsigned OptLevel,
87 CodeGenOpt::Level OptLevel,
8788 bool Verbose,
8889 raw_ostream &Out) {
8990 // Output assembly language.
5050 static unsigned getModuleMatchQuality(const Module &M);
5151
5252 // Pass Pipeline Configuration
53 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
54 virtual bool addPreEmitPass(PassManagerBase &PM, unsigned OptLevel);
55 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
53 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55 virtual bool addAssemblyEmitter(PassManagerBase &PM,
56 CodeGenOpt::Level OptLevel,
5657 bool Verbose, raw_ostream &Out);
5758 };
5859
3333 const X86Subtarget *Subtarget;
3434 public:
3535 explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
36 const TargetAsmInfo *T, unsigned OL, bool V)
36 const TargetAsmInfo *T, CodeGenOpt::Level OL,
37 bool V)
3738 : AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
3839 Subtarget = &TM.getSubtarget();
3940 }
2424 ///
2525 FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
2626 X86TargetMachine &tm,
27 unsigned OptLevel, bool verbose) {
27 CodeGenOpt::Level OptLevel,
28 bool verbose) {
2829 const X86Subtarget *Subtarget = &tm.getSubtarget();
2930
3031 if (Subtarget->isFlavorIntel()) {
2525
2626 struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
2727 explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
28 const TargetAsmInfo *T, unsigned OL, bool V)
28 const TargetAsmInfo *T, CodeGenOpt::Level OL,
29 bool V)
2930 : AsmPrinter(O, TM, T, OL, V) {}
3031
3132 virtual const char *getPassName() const {
1414 #ifndef TARGET_X86_H
1515 #define TARGET_X86_H
1616
17 #include "llvm/Target/TargetMachine.h"
18
1719 namespace llvm {
1820
1921 class X86TargetMachine;
2426 /// createX86ISelDag - This pass converts a legalized DAG into a
2527 /// X86-specific DAG, ready for instruction scheduling.
2628 ///
27 FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize);
29 FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel);
2830
2931 /// createX86FloatingPointStackifierPass - This function returns a pass which
3032 /// converts floating point register references and pseudo instructions into
4345 ///
4446 FunctionPass *createX86CodePrinterPass(raw_ostream &o,
4547 X86TargetMachine &tm,
46 unsigned OptLevel, bool Verbose);
48 CodeGenOpt::Level OptLevel,
49 bool Verbose);
4750
4851 /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
4952 /// to the specified MCE object.
133133 bool OptForSize;
134134
135135 public:
136 explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
136 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
137137 : SelectionDAGISel(tm, OptLevel),
138138 TM(tm), X86Lowering(*TM.getTargetLowering()),
139139 Subtarget(&TM.getSubtarget()),
305305
306306 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
307307 SDNode *Root) const {
308 if (OptLevel == 0) return false;
308 if (OptLevel == CodeGenOpt::None) return false;
309309
310310 if (U == Root)
311311 switch (U->getOpcode()) {
713713 OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
714714
715715 DEBUG(BB->dump());
716 if (OptLevel != 0)
716 if (OptLevel != CodeGenOpt::None)
717717 PreprocessForRMW();
718718
719719 // FIXME: This should only happen when not compiled with -O0.
17431743 /// createX86ISelDag - This pass converts a legalized DAG into a
17441744 /// X86-specific DAG, ready for instruction scheduling.
17451745 ///
1746 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) {
1746 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
1747 llvm::CodeGenOpt::Level OptLevel) {
17471748 return new X86DAGToDAGISel(TM, OptLevel);
17481749 }
179179 // Pass Pipeline Configuration
180180 //===----------------------------------------------------------------------===//
181181
182 bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
182 bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
183 CodeGenOpt::Level OptLevel) {
183184 // Install an instruction selector.
184185 PM.add(createX86ISelDag(*this, OptLevel));
185186
193194 return false;
194195 }
195196
196 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
197 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
198 CodeGenOpt::Level OptLevel) {
197199 // Calculate and set max stack object alignment early, so we can decide
198200 // whether we will need stack realignment (and thus FP).
199201 PM.add(createX86MaxStackAlignmentCalculatorPass());
200202 return false; // -print-machineinstr shouldn't print after this.
201203 }
202204
203 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
205 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
206 CodeGenOpt::Level OptLevel) {
204207 PM.add(createX86FloatingPointStackifierPass());
205208 return true; // -print-machineinstr should print after this.
206209 }
207210
208211 bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
209 unsigned OptLevel,
212 CodeGenOpt::Level OptLevel,
210213 bool Verbose,
211214 raw_ostream &Out) {
212215 assert(AsmPrinterCtor && "AsmPrinter was not linked in");
215218 return false;
216219 }
217220
218 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
221 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
222 CodeGenOpt::Level OptLevel,
219223 bool DumpAsm, MachineCodeEmitter &MCE) {
220224 // FIXME: Move this to TargetJITInfo!
221225 // On Darwin, do not override 64-bit setting made in X86TargetMachine().
244248 }
245249
246250 bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
247 unsigned OptLevel, bool DumpAsm,
251 CodeGenOpt::Level OptLevel,
252 bool DumpAsm,
248253 MachineCodeEmitter &MCE) {
249254 PM.add(createX86CodeEmitterPass(*this, MCE));
250255 if (DumpAsm) {
4444 // set this functions to ctor pointer at startup time if they are linked in.
4545 typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
4646 X86TargetMachine &tm,
47 unsigned OptLevel, bool verbose);
47 CodeGenOpt::Level OptLevel,
48 bool verbose);
4849 static AsmPrinterCtorFn AsmPrinterCtor;
4950
5051 public:
7374 }
7475
7576 // Set up the pass pipeline.
76 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
77 virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel);
78 virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel);
79 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
77 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
78 virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
79 virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
80 virtual bool addAssemblyEmitter(PassManagerBase &PM,
81 CodeGenOpt::Level OptLevel,
8082 bool Verbose, raw_ostream &Out);
81 virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
83 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
8284 bool DumpAsm, MachineCodeEmitter &MCE);
83 virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
85 virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
86 CodeGenOpt::Level OptLevel,
8487 bool DumpAsm, MachineCodeEmitter &MCE);
8588
8689 /// symbolicAddressesAreRIPRel - Return true if symbolic addresses are
1414 #ifndef TARGET_XCORE_H
1515 #define TARGET_XCORE_H
1616
17 #include "llvm/Target/TargetMachine.h"
18
1719 namespace llvm {
1820 class FunctionPass;
1921 class TargetMachine;
2325 FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM);
2426 FunctionPass *createXCoreCodePrinterPass(raw_ostream &OS,
2527 XCoreTargetMachine &TM,
26 unsigned OptLevel, bool Verbose);
28 CodeGenOpt::Level OptLevel,
29 bool Verbose);
2730 } // end namespace llvm;
2831
2932 // Defines symbolic names for XCore registers. This defines a mapping from
5656 DwarfWriter *DW;
5757 const XCoreSubtarget &Subtarget;
5858 public:
59 XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
60 const TargetAsmInfo *T, unsigned OL, bool V)
59 explicit XCoreAsmPrinter(raw_ostream &O, XCoreTargetMachine &TM,
60 const TargetAsmInfo *T, CodeGenOpt::Level OL,
61 bool V)
6162 : AsmPrinter(O, TM, T, OL, V), DW(0),
6263 Subtarget(*TM.getSubtargetImpl()) {}
6364
104105 ///
105106 FunctionPass *llvm::createXCoreCodePrinterPass(raw_ostream &o,
106107 XCoreTargetMachine &tm,
107 unsigned OptLevel,
108 CodeGenOpt::Level OptLevel,
108109 bool verbose) {
109110 return new XCoreAsmPrinter(o, tm, tm.getTargetAsmInfo(), OptLevel, verbose);
110111 }
5555 }
5656
5757 bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM,
58 unsigned OptLevel) {
58 CodeGenOpt::Level OptLevel) {
5959 PM.add(createXCoreISelDag(*this));
6060 return false;
6161 }
6262
6363 bool XCoreTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
64 unsigned OptLevel,
64 CodeGenOpt::Level OptLevel,
6565 bool Verbose,
6666 raw_ostream &Out) {
6767 // Output assembly language.
5151 static unsigned getModuleMatchQuality(const Module &M);
5252
5353 // Pass Pipeline Configuration
54 virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
55 virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
54 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55 virtual bool addAssemblyEmitter(PassManagerBase &PM,
56 CodeGenOpt::Level OptLevel,
5657 bool Verbose, raw_ostream &Out);
5758 };
5859
5555 static cl::opt Force("f", cl::desc("Overwrite output files"));
5656
5757 // Determine optimization level. Level -O0 is equivalent to "fast" code gen.
58 static cl::opt<unsigned>
58 static cl::opt<char>
5959 OptLevel("O",
60 cl::desc("Optimization level. Similar to llvm-gcc -O. (default: -O3)"),
60 cl::desc("Optimization level. Similar to llvm-gcc -O."),
6161 cl::Prefix,
6262 cl::ZeroOrMore,
63 cl::init(3));
63 cl::init(' '));
6464
6565 static cl::opt
6666 TargetTriple("mtriple", cl::desc("Override target triple for module"));
252252 raw_ostream *Out = GetOutputStream(argv[0]);
253253 if (Out == 0) return 1;
254254
255 CodeGenOpt::Level OLvl = CodeGenOpt::Aggressive;
256
257 switch (OptLevel) {
258 default:
259 case ' ': break;
260 case '0': OLvl = CodeGenOpt::None; break;
261 case '1': OLvl = CodeGenOpt::One; break;
262 case '2': OLvl = CodeGenOpt::Two; break;
263 case 's': OLvl = CodeGenOpt::Size; break;
264 case '3': OLvl = CodeGenOpt::Aggressive; break;
265 case '4': OLvl = CodeGenOpt::LTO; break;
266 }
267
255268 // If this target requires addPassesToEmitWholeFile, do it now. This is
256269 // used by strange things like the C backend.
257270 if (Target.WantsWholeFile()) {
261274 PM.add(createVerifierPass());
262275
263276 // Ask the target to add backend passes as necessary.
264 if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OptLevel)) {
277 if (Target.addPassesToEmitWholeFile(PM, *Out, FileType, OLvl)) {
265278 std::cerr << argv[0] << ": target does not support generation of this"
266279 << " file type!\n";
267280 if (Out != &outs()) delete Out;
287300 // Override default to generate verbose assembly.
288301 Target.setAsmVerbosityDefault(true);
289302
290 switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OptLevel)) {
303 switch (Target.addPassesToEmitFile(Passes, *Out, FileType, OLvl)) {
291304 default:
292305 assert(0 && "Invalid file model!");
293306 return 1;
308321 break;
309322 }
310323
311 if (Target.addPassesToEmitFileFinish(Passes, MCE, OptLevel)) {
324 if (Target.addPassesToEmitFileFinish(Passes, MCE, OLvl)) {
312325 std::cerr << argv[0] << ": target does not support generation of this"
313326 << " file type!\n";
314327 if (Out != &outs()) delete Out;
121121 if (!TargetTriple.empty())
122122 Mod->setTargetTriple(TargetTriple);
123123
124 EE = ExecutionEngine::create(MP, ForceInterpreter, &ErrorMsg, Fast);
124 EE = ExecutionEngine::create(MP, ForceInterpreter, &ErrorMsg,
125 Fast ?
126 CodeGenOpt::None : CodeGenOpt::Aggressive);
125127 if (!EE && !ErrorMsg.empty()) {
126128 std::cerr << argv[0] << ":error creating EE: " << ErrorMsg << "\n";
127129 exit(1);
441441 MachineCodeEmitter* mce = NULL;
442442
443443 switch (_target->addPassesToEmitFile(*codeGenPasses, out,
444 TargetMachine::AssemblyFile, 3)) {
444 TargetMachine::AssemblyFile,
445 CodeGenOpt::Default)) {
445446 case FileModel::MachOFile:
446447 mce = AddMachOWriter(*codeGenPasses, out, *_target);
447448 break;
456457 return true;
457458 }
458459
459 if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce, 3)) {
460 if (_target->addPassesToEmitFileFinish(*codeGenPasses, mce,
461 CodeGenOpt::Default)) {
460462 errMsg = "target does not support generation of this file type";
461463 return true;
462464 }
649649 O << "\";\n\n";
650650
651651 O << " if (TAI->doesSupportDebugInformation() &&\n"
652 << " DW->ShouldEmitDwarfDebug() && OptLevel != 0) {\n"
652 << " DW->ShouldEmitDwarfDebug() && OptLevel != CodeGenOpt::None) {\n"
653653 << " DebugLoc CurDL = MI->getDebugLoc();\n\n"
654654 << " if (!CurDL.isUnknown()) {\n"
655655 << " static DebugLocTuple PrevDLT(~0U, ~0U, ~0U);\n"
464464 NumInputRootOps = N->getNumChildren();
465465
466466 if (DisablePatternForFastISel(N, CGP))
467 emitCheck("OptLevel != 0");
467 emitCheck("OptLevel != CodeGenOpt::None");
468468
469469 emitCheck(PredicateCheck);
470470 }