llvm.org GIT mirror llvm / 987df33
Merging r358042: ------------------------------------------------------------------------ r358042 | jimlin | 2019-04-09 18:56:32 -0700 (Tue, 09 Apr 2019) | 34 lines [Sparc] Fix incorrect MI insertion position for spilling f128. Summary: Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset should be inserted before new created MI for storing even register into memory. So the insertion position should be *StMI instead of II. before fixed: std %f0, [%g1+80] sethi 4, %g1 <<< add %g1, %sp, %g1 <<< this two instructions should be put before "std %f0, [%g1+80]". sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] after fixed: sethi 4, %g1 add %g1, %sp, %g1 std %f0, [%g1+80] sethi 4, %g1 add %g1, %sp, %g1 std %f2, [%g1+88] Reviewers: venkatra, jyknight Reviewed By: jyknight Subscribers: jyknight, fedor.sergeev, jrtc27, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60397 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_80@363010 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 months ago
2 changed file(s) with 25 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
188188 MachineInstr *StMI =
189189 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
190190 .addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
191 replaceFI(MF, II, *StMI, dl, 0, Offset, FrameReg);
191 replaceFI(MF, *StMI, *StMI, dl, 0, Offset, FrameReg);
192192 MI.setDesc(TII.get(SP::STDFri));
193193 MI.getOperand(2).setReg(SrcOddReg);
194194 Offset += 8;
200200 MachineInstr *StMI =
201201 BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
202202 .addReg(FrameReg).addImm(0);
203 replaceFI(MF, II, *StMI, dl, 1, Offset, FrameReg);
203 replaceFI(MF, *StMI, *StMI, dl, 1, Offset, FrameReg);
204204
205205 MI.setDesc(TII.get(SP::LDDFri));
206206 MI.getOperand(0).setReg(DestOddReg);
4949 %0 = load fp128, fp128* %a, align 8
5050 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
5151 store fp128 %0, fp128* %scalar.result, align 8
52 ret void
53 }
54
55 ; CHECK-LABEL: f128_spill_large:
56 ; CHECK: sethi 4, %g1
57 ; CHECK: sethi 4, %g1
58 ; CHECK-NEXT: add %g1, %sp, %g1
59 ; CHECK-NEXT: std %f{{.+}}, [%g1]
60 ; CHECK: sethi 4, %g1
61 ; CHECK-NEXT: add %g1, %sp, %g1
62 ; CHECK-NEXT: std %f{{.+}}, [%g1+8]
63 ; CHECK: sethi 4, %g1
64 ; CHECK-NEXT: add %g1, %sp, %g1
65 ; CHECK-NEXT: ldd [%g1], %f{{.+}}
66 ; CHECK: sethi 4, %g1
67 ; CHECK-NEXT: add %g1, %sp, %g1
68 ; CHECK-NEXT: ldd [%g1+8], %f{{.+}}
69
70 define void @f128_spill_large(<251 x fp128>* noalias sret %scalar.result, <251 x fp128>* byval %a) {
71 entry:
72 %0 = load <251 x fp128>, <251 x fp128>* %a, align 8
73 call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"()
74 store <251 x fp128> %0, <251 x fp128>* %scalar.result, align 8
5275 ret void
5376 }
5477